Array substrate, manufacturing method and display panel

Abstract

The application is suitable for the technical field of display, and provides an array substrate, a manufacturing method and a display panel. The array substrate comprises a substrate, a gate electrode, a gate insulating layer, an active layer and a source electrode and a drain electrode. The gate insulating layer comprises a flat part and a first part, and the thickness of the first part is different from that of the flat part. The active layer covers the first part, and the source electrode covers the first part. On the basis of ensuring a small facing area between the source electrode and the gate electrode, a large contact area is formed between the source electrode and the active layer, the charging rate of the pixel capacitance is improved on the basis of ensuring a small parasitic capacitance between the source electrode and the gate electrode, the charging effect of the pixel capacitance is improved, the area of the TFT is reduced, and the aperture ratio is improved. The display panel with the array substrate has a small parasitic capacitance between the source electrode and the gate electrode and a high charging rate of the pixel capacitance.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method, and a display panel. Background Technology

[0002] Thin film transistors (TFTs) are suitable for large-area fabrication on glass and plastic films, and they have played a significant role in the flat panel display field. Almost all display panels use TFTs as active matrix driven electronic devices.

[0003] The basic components of a TFT include the gate, gate insulating layer, active semiconductor layer, source electrode, and drain electrode. In a display panel, to ensure a high charging rate when the TFT charges the pixel, it is necessary to ensure that the TFT has a large on-state current (Ion) during the on-state phase. Increasing the area of ​​the source and drain electrodes helps to increase the on-state current of the thin-film transistor, but it also leads to an increase in the parasitic capacitance (Cgs, Cgd) between the source / drain and the gate, which in turn affects the charging effect on the pixel. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate that solves the technical problem that existing display panels cannot simultaneously improve the on-state current of TFTs and reduce parasitic capacitance.

[0005] The embodiments of this application are implemented as follows: an array substrate includes:

[0006] Substrate;

[0007] A gate electrode disposed on the substrate;

[0008] A gate insulating layer is disposed on the gate, the gate insulating layer comprising a flat portion and a first portion, the first portion having a different thickness from the flat portion;

[0009] An active layer is disposed on the gate insulating layer and covers the first portion; and

[0010] The source and drain are disposed on the active layer, with the source covering the first portion.

[0011] In one embodiment, the thickness difference between the first portion and the flat portion is 1 / 4 to 1 / 3 of the thickness of the flat portion.

[0012] In one embodiment, the gate insulating layer further includes a second portion having a different thickness from the flat portion; the active layer also covers the second portion; and the drain covers the second portion.

[0013] In one embodiment, the thickness difference between the second portion and the flat portion is 1 / 4 to 1 / 3 of the thickness of the flat portion.

[0014] In one embodiment, the thickness of the active layer is 300 angstroms to 3000 angstroms; the thickness of the source and the drain is 2000 angstroms to 6000 angstroms.

[0015] In one embodiment, the thickness of the flat portion is 2000 angstroms to 6000 angstroms.

[0016] In one embodiment, the thickness of both the first portion and the second portion is less than the thickness of the flat portion; or, the thickness of both the first portion and the second portion is greater than the thickness of the flat portion.

[0017] Another objective of this application is to provide a method for fabricating an array substrate, comprising:

[0018] A substrate is provided, and a gate is formed on the substrate;

[0019] A gate insulating layer is formed on the gate, the gate insulating layer comprising a flat portion and a first portion having a different thickness from the flat portion;

[0020] An active layer is formed on the gate insulating layer, and the active layer covers the first portion;

[0021] A source and a drain are formed on the active layer, with the source covering the first portion.

[0022] In one embodiment, the gate insulating layer further includes a second portion having a different thickness from the flat portion; the active layer also covers the second portion; and the drain covers the second portion.

[0023] Another objective of this application is to provide a display panel, including the array substrate described in the above embodiments, a color filter substrate spaced opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

[0024] The array substrate and display panel provided in this application have the following advantages:

[0025] The array substrate provided in this application embodiment has a thick or thin region formed on a portion of its gate insulating layer relative to a flat portion. Both the active layer and the source electrode cover this thick or thin region. This allows for a large contact area between the source electrode and the active layer while maintaining a small facing area between the source and the gate. This improves the charging rate of the pixel capacitor while ensuring a small parasitic capacitance between the source and the gate, thus enhancing the charging effect of the pixel capacitor. Conversely, while maintaining the same charging effect, the size of the TFT can be designed to be smaller, which also helps to reduce the area occupied by the TFT on the array substrate and increase the aperture ratio. The display panel with this array substrate has a small parasitic capacitance between the source and the gate and a high charging rate for the pixel capacitor. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a partial structural planar schematic diagram of the array substrate provided in Embodiment 1 of this application;

[0028] Figure 2 yes Figure 1 A cross-sectional view at point AA along the middle edge;

[0029] Figure 3 yes Figure 1 Another cross-sectional view at point AA along the middle;

[0030] Figure 4 This is a flowchart of a method for fabricating an array substrate according to an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of the structure formed in step S1 of the method for manufacturing an array substrate provided in this application embodiment;

[0032] Figure 6 This is a schematic diagram of the structure formed in step S21 of step S2 in the method for manufacturing an array substrate provided in this application embodiment;

[0033] Figure 7 This is a schematic diagram of the structure formed in step S22 of step S2 in the method for manufacturing an array substrate provided in this application embodiment;

[0034] Figure 8 This is a schematic diagram of the structure formed in step S23 of step S2 in the method for manufacturing an array substrate provided in this application embodiment;

[0035] Figure 9 This is a schematic diagram of the structure formed in step S24 of step S2 in the method for manufacturing an array substrate provided in this application embodiment;

[0036] Figure 10 This is a schematic diagram of the structure formed in step S3 of the method for manufacturing an array substrate provided in this application embodiment;

[0037] Figure 11 This is a schematic diagram of the structure formed in step S4 of the method for manufacturing an array substrate provided in this application embodiment;

[0038] Figure 12 This is a schematic diagram of the structure formed in step S5 of the method for manufacturing an array substrate provided in this application embodiment;

[0039] Figure 13 This is a schematic diagram of the structure of the display panel provided in the embodiment of this application.

[0040] The markings in the diagram mean:

[0041] 400 - Display panel, 300 - Color filter substrate, 200 - Liquid crystal layer;

[0042] 100-Array substrate;

[0043] 10 - Substrate;

[0044] 11-Gate;

[0045] 12-Gate insulating layer, 120-Planar portion, 121-First portion, 122-Second portion;

[0046] 127 - Gate insulating material layer, 128 - Photoresist pattern, 129 - Groove;

[0047] 13-Active layer, 131-Semiconductor layer, 132-Ohmic contact layer;

[0048] 14 - Source, 15 - Drain;

[0049] 16-Passivation layer. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly or indirectly fixed to or set on that other component. When a component is referred to as "connected to" another component, it can be directly or indirectly connected to that other component. The terms "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the purpose of description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this patent. The terms "first" and "second" are used only for the purpose of description and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. "A plurality" means two or more, unless otherwise explicitly specified.

[0052] Please see Figure 1 and Figure 2 As shown, this application embodiment first provides an array substrate 100, including a substrate 10, a gate 11 disposed on the substrate 10, a gate insulating layer 12 disposed on the gate 11, an active layer 13 disposed on the gate insulating layer 12, and a source electrode 14 disposed on the active layer 13.

[0053] Among them, such as Figure 2 As shown, the gate insulating layer 12 includes a flat portion 120 and a first portion 121. The first portion 121 has a different thickness than the flat portion 120; specifically, it can be thicker or thinner than the flat portion 120. That is, the first portion 121 is a thickened or thinned structure relative to the flat portion 120, meaning the thickness of the first portion 121 is different from the thickness of the flat portion 120.

[0054] The active layer 13 located on the gate insulating layer 12 covers the first portion 121; the source electrode 14 located on the active layer 13 also covers the first portion 121. That is, the edge of the projection of the first portion 121 onto the substrate 10 is located inside the edge of the projection of the source electrode 14 onto the substrate 10 (excluding the overlap of the two edges, or in other words, the two edges do not overlap at any position), and the edge of the projection of the first portion 121 onto the substrate 10 is also located inside the edge of the projection of the active layer 13 onto the substrate 10 (excluding the overlap of the two edges, or in other words, the two edges do not overlap at any position).

[0055] Of course, such as Figure 1 and Figure 2 As shown, the array substrate 100 also includes a drain 15, which is disposed on the active layer 13 and spaced apart from the source 14.

[0056] like Figure 2 and Figure 3As shown, the array substrate 100 also includes a passivation layer 16 disposed on the source electrode 14 and the drain electrode 15, and a pixel electrode layer (not shown) disposed on the passivation layer 16. Each pixel electrode in the pixel electrode layer is connected to the drain electrode 15 through a via (not shown) penetrating the passivation layer 16.

[0057] The passivation layer 16 can be made of at least one of silicon dioxide and silicon nitride, with a thickness of 1000 angstroms to 6000 angstroms, and is used to protect the underlying TFT from damage by water, oxygen, etc. The pixel electrode layer is made of a transparent conductive metal material.

[0058] The TFT is composed of the gate 11, gate insulating layer 12, active layer 13, source 14 and drain 15.

[0059] like Figure 1 and Figure 2 As shown, in a direction perpendicular to the surface of the substrate 10, a portion of the source electrode 14 faces the gate electrode 11. Therefore, a parasitic capacitance (Cgs) is formed between the source electrode 14 and the gate electrode 11. The area of ​​the area between them (i.e., the area of ​​the orthogonal projection of the source electrode 14 onto the gate electrode 11) determines the size of this parasitic capacitance. The source electrode 14 is in contact with the active layer 13. The total contact area between them determines the magnitude of the current that can pass through the source electrode 14 and the active layer 13 in the TFT, that is, the magnitude of the on-state current of the TFT. The magnitude of the on-state current, in turn, determines the charging rate of the TFT on the pixel capacitor formed by the pixel electrode and the upper common electrode (not shown, the upper common electrode may be disposed on the color filter substrate 300). The larger the total contact area between the source electrode 14 and the active layer 13, the larger the on-state current and the higher the charging rate of the pixel capacitor.

[0060] In this embodiment, by forming a first portion 121 on the gate insulating layer 12 that is thicker or thinner than the flat portion 120, the active layer 13 and the source electrode 14 sequentially cover the first portion 121. This makes the active layer 13 convex or concave relative to the first portion 121, and the source electrode 14 convex or concave relative to the first portion 121. Therefore, a contact is also formed between the active layer 13 and the source electrode 14 at the sidewall of the first portion 121, which increases the total contact area between the active layer 13 and the source electrode 14, but the projected area of ​​the source electrode 14 on the gate 11 does not increase due to the arrangement of the first portion 121.

[0061] Thus, the array substrate 100 provided in this application embodiment can achieve a large contact area between the source 14 and the active layer 13 while ensuring a small facing area between the source 14 and the gate 11. This can improve the charging rate of the pixel capacitor while ensuring a small parasitic capacitance between the source 14 and the gate 11, thereby improving the charging effect of the pixel capacitor and ensuring the display effect. Conversely, while ensuring the same charging rate, the size of the TFT can be designed to be smaller, which is also beneficial to reduce the area occupied by the TFT on the array substrate 100 and increase the aperture ratio of the array substrate 100.

[0062] Furthermore, it should be noted that in this embodiment, the active layer 13 and the source electrode 14 are made to have a convex or concave pattern by thickening or thinning a portion of the gate insulating layer 12, rather than by directly designing a convex or concave pattern on the upper surface of the active layer 13. This is because: firstly, the thickness of the active layer 13 is usually smaller than the thickness of the gate insulating layer 12, and the increase in the contact area between the active layer 13 and the source electrode 14 by the convex or concave pattern of the active layer 13 is relatively limited; secondly, the active layer 13 has higher requirements for film quality. Therefore, the solution of this application can provide a sufficient increase in on-state current while avoiding any impact on the electrical performance of the active layer 13.

[0063] Specifically, in one embodiment, the thickness of the flat portion 120 of the gate insulating layer 12 is 2000 angstroms to 6000 angstroms. The thickness difference between the first portion 121 and the flat portion 120 of the gate insulating layer 12 is 1 / 4 to 1 / 3 of the thickness of the flat portion 120. That is, if the first portion 121 is a thickened structure, its thickness exceeding that of the flat portion 120 is 1 / 4 to 1 / 3 of the thickness of the flat portion 120; if the first portion 121 is a thinned structure with a smaller thickness, the formed groove 129 (see reference) Figure 9 The depth of the flat portion 120 (as shown) is 1 / 4 to 1 / 3 of its thickness.

[0064] Specifically, in one embodiment, the thickness of the active layer 13 is 300 angstroms to 3000 angstroms (1 angstrom = 0.1 nanometers).

[0065] Typically, such as Figure 1 As shown, in a TFT, the area of ​​the source 14 is smaller than the area of ​​the drain 15. Therefore, the on-state current is mainly limited by the contact area between the source 14 and the active layer 13.

[0066] Therefore, in the above embodiments, the portion of the active layer 13 and the portion of the gate insulating layer 12 located below the drain 15 do not require a bump or recessed design, but are both flat with a uniform thickness. The purpose of this arrangement is that the formation of the first portion 121 requires the deposited gate insulating material layer 127 (see reference) to... Figure 8 The gate insulating layer 12 below the drain 15 is formed by etching (as shown), so the etching yield is high and the overall forming process of the gate insulating layer 12 can have a high yield, especially for the first part 121 of the thinned structure.

[0067] Or, such as Figure 3 As shown, in one embodiment, the portion of the active layer 13 and the portion of the gate insulating layer 12 located below the drain 15 are also designed with a bump and recess to further improve the on-state current.

[0068] Specifically, such as Figure 3 As shown, the gate insulating layer 12 further includes a second portion 122, which is either thickened or thinned relative to the flat portion 120 of the gate insulating layer 12. The active layer 13 also covers the second portion 122, and the drain 15 covers the second portion 122. Similarly, the edge of the projection of the second portion 122 onto the substrate 10 is located inside the edge of the projection of the drain 15 onto the substrate 10 (excluding the overlap of their edges, or in other words, the edges of the two do not overlap at any position), and the edge of the projection of the second portion 122 onto the substrate 10 is located inside the edge of the projection of the active layer 13 onto the substrate 10 (excluding the overlap of their edges, or in other words, the edges of the two do not overlap at any position).

[0069] like Figure 1 and Figure 3 As shown, in a direction perpendicular to the surface of the substrate 10, the drain 15 and the gate 11 face each other, forming a parasitic capacitance (Cgd) between them. The area of ​​the facets between them (i.e., the area of ​​the orthogonal projection of the drain 15 onto the gate 11) determines the size of the parasitic capacitance. The drain 15 is in contact with the active layer 13, and the total contact area between them determines the magnitude of the current that can pass through the drain 15 and the active layer 13 in the TFT. This also affects the magnitude of the on-state current of the TFT, and further affects the charging rate of the TFT to the pixel capacitor. The larger the total contact area between the drain 15 and the active layer 13, the larger the on-state current, and the higher the charging rate of the TFT to the pixel capacitor.

[0070] In this embodiment, a second portion 122, which is thicker or thinner than the flat portion 120, is formed on the gate insulating layer 12 below the drain 15. The active layer 13 and the drain 15 sequentially cover this second portion 122, making the active layer 13 convex or concave relative to the second portion 122, and the drain 15 convex or concave relative to the second portion 122. Therefore, a contact is also formed between the active layer 13 and the drain 15 at the sidewall of the second portion 122, which increases the total contact area between the active layer 13 and the drain 15, but the projected area of ​​the drain 15 on the gate 11 is not increased by the provision of the first portion 121.

[0071] Thus, in this embodiment, the charging rate of the pixel capacitor can be further improved while ensuring a small parasitic capacitance between the drain 15 and the gate 11, and the charging effect of the pixel capacitor can be further improved to ensure the display effect. Similarly, while ensuring the same charging rate, the size of the TFT can be further designed to be smaller, which is conducive to reducing the area occupied by the TFT on the array substrate 100 and improving the aperture ratio of the array substrate 100.

[0072] In other alternative embodiments, depending on the structure of the TFT, if the drain 15 has a smaller area than the source 14, and the main factor affecting the on-state current is the drain 15, then the gate insulating layer 12 below the drain 15 can be thickened or thinned first or primarily. For details, please refer to the description of the above embodiments, which will not be repeated here.

[0073] Specifically, in one embodiment, the thickness difference between the second portion 122 and the flat portion 120 is 1 / 4 to 1 / 3 of the thickness of the flat portion 120. That is, if the second portion 122 is a thickened structure, its thickness exceeding that of the flat portion 120 is 1 / 4 to 1 / 3 of the thickness of the flat portion 120; if the second portion 122 is a thinned structure, the resulting groove 129' (see reference) Figure 9 The depth of the flat portion 120 (as shown) is 1 / 4 to 1 / 3 of its thickness.

[0074] In one embodiment, the thickness of source 14 and drain 15 is 3000 angstroms to 6000 angstroms. Source 14 and drain 15 are formed using the same photomask.

[0075] In one embodiment, the features of the first portion 121 and the second portion 122 may be the same or not completely the same. For example, both the first portion 121 and the second portion 122 may be thickened structures, and further, the thicknesses of the first portion 121 and the second portion 122 may be equal; or, both the first portion 121 and the second portion 122 may be thinned structures, and further, the thicknesses of the first portion 121 and the second portion 122 may be equal; or, both the first portion 121 and the second portion 122 may be thickened or thinned structures, but with unequal thicknesses; or, in more embodiments, one of the first portion 121 and the second portion 122 may be a thickened structure and the other a thinned structure. Specific examples are not exhaustive.

[0076] Please see Figure 1 As shown, typically, the drain 15 is curved, roughly C-shaped, while the source 14 has a more regular shape, close to a trapezoidal or rectangular shape, and is inserted into the opening formed by the drain 15, spaced apart from it. The shape of the first part 121 is consistent with the shape of the source 14, which is equivalent to shrinking the edge of the source 14 inward by a certain distance. The shape of the second part 122 is consistent with the shape of the drain 15, which is equivalent to shrinking the edge of the drain 15 inward by a certain distance. This ensures that, while the first part 121 and the second part 122 are respectively covered by the source 14 and the drain 15, the first part 121 and the second part 122 each have a large total perimeter of edges, thus having a large sidewall area.

[0077] Of course, this is not the only option. In other alternative embodiments, the shapes of the first portion 121 and the second portion 122 do not necessarily need to be similar to or identical to the source 14 and the drain 15, respectively, and can be set according to specific requirements. In other further alternative embodiments, depending on the different designs of the array substrate 100, the drain 15 and the source 14...

[0078] In one embodiment, the substrate 10 is a transparent substrate, specifically a transparent glass substrate, a transparent plastic substrate, or a transparent silicon substrate, etc.

[0079] In one embodiment, the gate insulating layer 12 can be made of silicon dioxide (SiO2) and silicon nitride (SiN). X One or two of them.

[0080] In one embodiment, the gate 11 may be made of copper, aluminum, or molybdenum, or a metal composite layer structure composed of multiple metals such as copper, aluminum, or molybdenum. The specific material of the gate 11 is not particularly limited; it may be a material with good electrical conductivity and good adhesion to the substrate 10.

[0081] In one embodiment, the source 14 and drain 15 can be made of copper, aluminum, or molybdenum, or a metal composite layer structure composed of multiple metals such as copper, aluminum, or molybdenum.

[0082] In one embodiment, the active layer 13 may be a metal oxide semiconductor material layer.

[0083] Alternatively, in another embodiment, the active layer 13 includes a semiconductor layer 131 disposed on the gate insulating layer 12 and an ohmic contact layer 132 disposed on the semiconductor layer 131 (see reference). Figure 10 and Figure 11 As shown, source 14 and drain 15 are contacted with semiconductor layer 131 via ohmic contact layer 132 to ensure good ohmic contact between source 14, drain 15 and active layer 13, and reduce the impedance between them. Semiconductor layer 131 can be an amorphous silicon layer or a polycrystalline silicon layer.

[0084] The thickness of the ohmic contact layer 132 is 100 angstroms to 500 angstroms.

[0085] Next, please refer to Figure 4 This application also provides a method for manufacturing an array substrate, used to manufacture the array substrate 100 described above. Specifically, the method for manufacturing the array substrate includes:

[0086] Step S1, as follows Figure 5 As shown, a substrate 10 is provided, and a gate 11 is formed on the substrate 10;

[0087] Step S2, as follows Figures 6 to 9 As shown, a gate insulating layer 12 is formed on the gate 11, wherein the gate insulating layer 12 includes a flat portion 120, a first portion 121 and / or a second portion 122, and the thicknesses of the first portion 121, the second portion 122 and the flat portion 120 are not equal; the following description takes the gate insulating layer 12 including the first portion 121 and the second portion 122 as an example.

[0088] Step S3, as follows Figure 10 As shown, an active layer 13 is formed on the gate insulating layer 12, and the active layer 13 covers the first portion 121;

[0089] Step S4, as follows Figure 11 As shown, a source 14 and a drain 15 are formed on the active layer 13, wherein the source 14 covers the first part 121 and the drain 15 covers the second part 122.

[0090] Specifically, in step S1, the provided substrate 10 can be a transparent substrate such as a glass substrate, a flexible plastic substrate, or a silicon substrate. A first metal layer is deposited on the substrate 10 by physical vapor deposition. The first metal layer can be made of copper, aluminum, or molybdenum, or a metal composite layer structure composed of multiple metals such as copper, aluminum, or molybdenum. The thickness of the first metal layer is between 3000 angstroms and 6000 angstroms. After the first metal layer is deposited, a patterned gate 11 is formed by a photolithography process (coating photoresist, exposure, development, etching, and photoresist removal).

[0091] Specifically, in step S2, a gate insulating material layer 127 is deposited on the gate 11 by chemical vapor deposition. The gate insulating material layer 127 can be SiO2 or SiN. X At least one of them. Then, a gate insulating layer 12 having a first portion 121 and / or a second portion 122 is formed by a photolithography process (coating photoresist, exposure, development, etching and photoresist removal).

[0092] The following description further illustrates the case where both the first portion 121 and the second portion 122 are thin regions relative to the flat portion 120. In step S2, by partially removing the area on the gate insulating material layer 127 corresponding to the region where the source 14 and drain 15 are to be formed, a gate insulating layer 12 with grooves 129 and 129' is obtained, which means that the first portion 121 and the second portion 122 with smaller thickness are obtained.

[0093] Specifically, first, step S21, please refer to... Figure 6 As shown, a gate insulating material layer 127 with a thickness of 2000 angstroms to 6000 angstroms is deposited on the gate 11.

[0094] For step S22, please refer to [link / reference]. Figure 7 As shown, a photoresist material layer is coated on the gate insulating layer 12, and the photoresist material layer is exposed by a photomask. The areas on the photoresist material layer corresponding to the areas on the gate insulating layer 12 below which the first part 121 and the second part 122 are to be formed are exposed. After development, the areas on the photoresist material layer corresponding to the areas on the gate insulating layer 12 below which the first part 121 and the second part 122 are to be formed are removed, forming a photoresist pattern 128. The photoresist pattern 128 exposes the areas on the gate insulating layer 12 to which the first part 121 and the second part 122 are to be formed.

[0095] For step S23, please refer to [link / reference]. Figure 8 As shown, the gate insulating layer 12 is etched with the photoresist pattern 128 as a protection, and the part not covered by the photoresist pattern 128 is partially etched away.

[0096] For step S24, please refer to [link / reference]. Figure 9As shown, after removing the photoresist pattern 128, a gate insulating layer 12 with grooves 129 and 129' is obtained. The portions below grooves 129 and 129' are the first portion 121 and the second portion 122, respectively, and the other portions are flat portions 120.

[0097] The thickness difference between the first portion 121 and the flat portion 120 (the depth of the groove 129) accounts for 1 / 3 to 1 / 4 of the thickness of the flat portion 120 of the gate insulating layer 12. The thickness difference between the second portion 122 and the flat portion 120 (the depth of the groove 129') accounts for 1 / 3 to 1 / 4 of the thickness of the flat portion 120.

[0098] Specifically, in step S3, the active layer 13 can be a metal oxide semiconductor material layer. A metal oxide semiconductor material layer is formed on the gate insulating layer 12 by physical vapor deposition, and the patterned active layer 13 is formed by a photolithography process (coating photoresist, exposure, development, etching and photoresist removal).

[0099] Alternatively, in another embodiment, in step S3, the active layer 13 includes a semiconductor layer 131 disposed on the gate insulating layer 12 and an ohmic contact layer 132 disposed on the semiconductor layer 131. The source 14 and drain 15 are respectively contacted with the semiconductor layer 131 via the ohmic contact layer 132. The semiconductor layer 131 can be an amorphous silicon layer or a polycrystalline silicon layer. The thickness of the ohmic contact layer 132 is 100 angstroms to 500 angstroms.

[0100] In step S3, such as Figure 10 As shown, the formed active layer 13 covers the first part 121 and the second part 122, and is recessed in the form of the first part 121 and the second part 122.

[0101] Specifically, in step S4, a second metal layer is deposited on the active layer 13 and the gate insulating layer 12 using physical vapor deposition. The second metal layer can be made of copper, aluminum, or molybdenum, or a metal composite layer structure composed of multiple metals such as copper, aluminum, or molybdenum. The thickness of the second metal layer is between 3000 angstroms and 6000 angstroms. After the second metal layer is deposited, a photolithography process (coating photoresist, exposure, development, etching, and photoresist removal) is used to form patterned source 14 and drain 15.

[0102] In step S4, as Figure 11 As shown, the formed source 14 is recessed along with the groove 129 on the gate insulating layer 12, covering the first portion 121; the formed drain 15 is recessed along with the groove 129' on the gate insulating layer 12, covering the second portion 122.

[0103] In this way, the contact area between the source 14, drain 15 and active layer 13 is increased respectively, while ensuring that the source 14, drain 15 and gate 11 have a small facing area respectively, and the parasitic capacitance Cgs between the source 14 and gate 11 and the Cgd between the drain 15 and gate 11 can be small.

[0104] In another embodiment, steps S3 and S4 described above can be combined into a single grayscale mask (or halftone mask) process, which will not be elaborated further here.

[0105] Furthermore, the method for fabricating the array substrate also includes step S5, such as... Figure 4 and Figure 12 As shown, a passivation layer 16 is deposited on the source electrode 14 and the drain electrode 15 by chemical vapor deposition, and a pixel electrode layer (not shown) is formed on the passivation layer 16. Each pixel electrode in the pixel electrode layer is connected to the drain electrode 15 through a via penetrating the passivation layer 16.

[0106] The passivation layer 16 can be made of at least one of silicon dioxide and silicon nitride, with a thickness of 1000 angstroms to 6000 angstroms, and is used to protect the underlying TFT from damage by water, oxygen, etc. The pixel electrode layer is made of a transparent conductive metal material.

[0107] Please see Figure 13 This application also provides a display panel 400, which includes the array substrate 100 described in the above embodiments, a color filter substrate 300 spaced apart from the array substrate 100, and a liquid crystal layer 200 disposed between the array substrate 100 and the color filter substrate 300. The features of the array substrate 100 can be found in the descriptions of the above embodiments, and will not be repeated here.

[0108] The display panel 400 provided in this application embodiment has a large contact area between the source electrode 14 and the active layer 13 and between the drain electrode 15 and the active layer 13 in its array substrate 100. The area of ​​the source electrode 14 and the drain electrode 15 facing the gate electrode 11 is small, the parasitic capacitance between the source electrode 14 and the gate electrode 11 is small, the TFT has a high charging rate for the pixel capacitor, and has a good display effect.

[0109] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An array substrate, characterized by, The application relates to a thin film transistor, comprising: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode, the gate insulating layer comprising a flat portion, a first portion and a second portion, the thickness of the first portion being less than that of the flat portion so as to form a first groove on the side of the first portion away from the substrate, the first portion having a side wall inclined relative to the substrate, the thickness of the second portion being less than that of the flat portion so as to form a second groove on the side of the second portion away from the substrate, the second portion having a side wall inclined relative to the substrate; an active layer formed on the gate insulating layer, the orthographic projections of the first portion and the second portion on the substrate being located within the orthographic projection of the active layer on the substrate, and the shape of the partial surface of the active layer on the side away from the substrate corresponding to the shape of the side wall; a source electrode and a drain electrode formed on the active layer, the orthographic projection of the first portion on the substrate being located within the orthographic projection of the source electrode on the substrate, and a part of the source electrode being arranged on the partial surface of the active layer corresponding to the side wall so as to increase the contact area of the source electrode with the active layer; the orthographic projection of the second portion on the substrate being located within the orthographic projection of the drain electrode on the substrate, and a part of the drain electrode being arranged on the partial surface of the active layer corresponding to the side wall so as to increase the contact area of the drain electrode with the active layer. The thickness difference between the first portion and the flat portion is 1 / 4-1 / 3 of the thickness of the flat portion.

2. The array substrate of claim 1, wherein, The thickness difference between the second portion and the flat portion is 1 / 4-1 / 3 of the thickness of the flat portion.

3. The array substrate of claim 1, wherein, The thickness of the active layer is 300 angstroms-3000 angstroms, and the thickness of the source electrode and the drain electrode is 2000 angstroms-6000 angstroms.

4. The array substrate according to any one of claims 1 to 3, wherein, The thickness of the flat portion is 2000 angstroms-6000 angstroms.

5. The array substrate according to any one of claims 1 to 3, wherein, The application relates to a method for manufacturing a thin film transistor, comprising:

6. A manufacturing method of an array substrate, characterized by, providing a substrate and forming a gate electrode on the substrate; forming a gate insulating layer on the gate electrode, the gate insulating layer comprising a flat portion, a first portion and a second portion, the thickness of the first portion being less than that of the flat portion so as to form a first groove on the side of the first portion away from the substrate, the first portion having a side wall inclined relative to the substrate, the thickness of the second portion being less than that of the flat portion so as to form a second groove on the side of the second portion away from the substrate, the second portion having a side wall inclined relative to the substrate; forming an active layer on the gate insulating layer, the orthographic projections of the first portion and the second portion on the substrate being located within the orthographic projection of the active layer on the substrate, and the shape of the partial surface of the active layer on the side away from the substrate corresponding to the shape of the side wall. ​ A source electrode and a drain electrode are formed on the active layer, a planar projection of the first portion on the substrate substrate is located within a planar projection of the source electrode on the substrate substrate, and a portion of the source electrode is disposed on a portion of the surface of the active layer corresponding to the sidewall to increase a contact area of the source electrode with the active layer; A planar projection of the second portion on the substrate substrate is located within a planar projection of the drain electrode on the substrate substrate, and a portion of the drain electrode is disposed on a portion of the surface of the active layer corresponding to the sidewall to increase a contact area of the drain electrode with the active layer.

7. A display panel, characterized by, An array substrate as claimed in any one of claims 1 to 5, a color filter substrate spaced opposite the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

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