Semiconductor structure and forming method thereof
By connecting the signal leads and signal pads of the first and second coil devices in parallel within a semiconductor structure, the problem of insufficient accuracy in measuring the parameters of the sensing device is solved, resulting in higher capacitance accuracy and improved sensing device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2024-10-24
- Publication Date
- 2026-04-28
AI Technical Summary
In the existing technology, the accuracy of parameter measurement of sensing devices needs to be improved, especially in CMOS radio frequency integrated circuits, where it is necessary to eliminate the influence of parasitic parameters introduced by the test fixture itself.
Design a semiconductor structure in which a first coil device and a second coil device are connected in parallel with signal pads via signal leads to form a test path, increasing the parasitic capacitance difference and thus improving the accuracy of the capacitance value.
By using a parallel structure, the accuracy of measuring device coil parameters is improved, the influence of parasitic capacitance is reduced, the stability and reliability of signal loading are enhanced, and the quality factor of the sensing device is improved.
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Figure CN121941318A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] In integrated circuits (ICs), such as CMOS radio frequency integrated circuits (RFICs), sensing devices are crucial electrical components whose performance parameters directly impact the overall performance of the IC. Most sensing devices in integrated circuits are planar inductors, such as planar spiral inductors. Compared to traditional wire-wound inductors, planar inductors offer advantages such as lower cost, easier integration, lower noise, and lower power consumption. Furthermore, planar inductors have high compatibility with existing integrated circuit manufacturing processes.
[0003] In radio frequency (RF) measurements, the use of Ground-Signal-Ground (GSG) pads is a common technique. A GSG pad is a specially designed test fixture to ensure accurate measurements at RF and microwave frequencies. A GSG pad consists of three main parts: two ground (G) pads and a middle signal (S) pad. This design allows for ground protection on both sides as the signal travels between the device under test (DUT) and the test equipment, reducing signal interference and distortion. When measuring an inductor, the inductor's signal port is connected to the S-port, while the G-ports are interconnected as a common ground.
[0004] To accurately measure the performance of inductors, it is necessary to eliminate the influence of parasitic parameters introduced by the test fixture itself. Currently, the accuracy of parameter measurement of sensing devices needs to be improved. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the accuracy of measuring the coil parameters of the device.
[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a first device region and a second device region arranged along a first direction, and a loading region located between the first device region and the second device region; a first signal pad located in the loading region; a second signal pad located in the loading region on the side of the first signal pad, and the second signal pad and the first signal pad being arranged along the first direction; a first coil device located in the first device region; a second coil device located in the second device region; a first signal lead electrically connecting the first coil device and the first signal pad; a second signal lead electrically connecting the first coil device and the second signal pad; a third signal lead electrically connecting the second coil device and the first signal pad; and a fourth signal lead electrically connecting the second coil device and the second signal pad.
[0007] Optionally, the semiconductor structure further includes: a first through-hole interconnect structure located between a first signal pad and a first signal lead, wherein the first signal lead is electrically connected to the first signal pad through the first through-hole interconnect structure; a second through-hole interconnect structure located between a second signal pad and a second signal lead, wherein the second signal lead is electrically connected to the second signal pad through the second through-hole interconnect structure; a third through-hole interconnect structure located between a first signal pad and a third signal lead, wherein the third signal lead is electrically connected to the first signal pad through the third through-hole interconnect structure; and a fourth through-hole interconnect structure located between a second signal pad and a fourth signal lead, wherein the fourth signal lead is electrically connected to the second signal pad through the fourth through-hole interconnect structure.
[0008] Optionally, the overall structure consisting of the first coil device, the first signal lead, the second signal lead, and the first signal pad is symmetrical to the overall structure consisting of the second coil device, the third signal lead, the fourth signal lead, and the second signal pad.
[0009] Optionally, the semiconductor structure further includes: a first shielding ring structure located at the bottom of the first coil device, wherein the projection of the first coil device on the substrate is within the area of the projection of the first shielding ring structure on the substrate.
[0010] Optionally, the semiconductor structure further includes: a first grounding pad located in the loading region and distributed on both sides of the first signal pad along a second direction, wherein the first direction and the second direction are perpendicular to each other; and a first grounding lead electrically connecting the first grounding pad and the first shielding ring structure.
[0011] Optionally, the semiconductor structure further includes: a second shielding ring structure located at the bottom of the second coil device, wherein the projection of the second coil device on the substrate is within the area of the projection of the second shielding ring structure on the substrate.
[0012] Optionally, the semiconductor structure further includes: a second grounding pad located in the loading region and distributed on both sides of the second signal pad along the second direction, wherein the first direction and the second direction are perpendicular to each other; and a second grounding lead electrically connected to the second grounding pad and the second shielding ring structure.
[0013] Optionally, both the first coil device and the second coil device include inductors.
[0014] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region arranged along a first direction, and a loading region located between the first device region and the second device region; forming a first signal pad and a second signal pad in the loading region, the second signal pad being located on the side of the first signal pad and the second signal pad being arranged along the first direction with the first signal pad; forming a first coil device in the first device region and forming a second coil device in the second device region; forming a first signal lead electrically connecting the first coil device and the first signal pad, forming a second signal lead electrically connecting the first coil device and the second signal pad, forming a third signal lead electrically connecting the second coil device and the first signal pad, and forming a fourth signal lead electrically connecting the second coil device and the second signal pad.
[0015] Optionally, the step of forming the first signal lead further includes: forming a first through-hole interconnect structure on the top of the first signal pad, and electrically connecting the first signal lead to the first signal pad through the first through-hole interconnect structure; the step of forming the second signal lead further includes: forming a second through-hole interconnect structure on the top of the second signal pad, and electrically connecting the second signal lead to the second signal pad through the second through-hole interconnect structure; the step of forming the third signal lead further includes: forming a third through-hole interconnect structure on the top of the first signal pad, and electrically connecting the third signal lead to the first signal pad through the third through-hole interconnect structure; the step of forming the fourth signal lead further includes: forming a fourth through-hole interconnect structure on the top of the second signal pad, and electrically connecting the fourth signal lead to the second signal pad through the fourth through-hole interconnect structure.
[0016] Optionally, in the steps of forming the first signal lead, the second signal lead, the third signal lead, and the fourth signal lead, the overall structure formed by the first coil device, the first signal lead, the second signal lead, and the first signal pad is symmetrical to the overall structure formed by the second coil device, the third signal lead, the fourth signal lead, and the second signal pad.
[0017] Optionally, before forming the first coil device and the second coil device, the method for forming the semiconductor structure further includes: forming a first shielding ring structure in a first device region and forming a second shielding ring structure in a second device region; in the step of forming the first coil device, the first coil device is formed on top of the first shielding ring structure, and the projection of the first coil device on the substrate is located within the area of the projection of the first shielding ring structure on the substrate; in the step of forming the second coil device, the second coil device is formed on top of the second shielding ring structure, and the projection of the second coil device on the substrate is located within the area of the projection of the second shielding ring structure on the substrate.
[0018] Optionally, the step of forming the first signal pad further includes: forming a first grounding pad distributed along a second direction on both sides of the first signal pad in the loading region, wherein the first direction and the second direction are perpendicular to each other; the method of forming the semiconductor structure further includes: forming a first grounding lead that electrically connects the first grounding pad and the first shielding ring structure.
[0019] Optionally, the step of forming the second signal pad further includes: forming a second grounding pad distributed along a second direction on both sides of the second signal pad in the loading region, wherein the first direction and the second direction are perpendicular to each other; the method of forming the semiconductor structure further includes: forming a second grounding lead that electrically connects the second grounding pad and the second shielding ring structure.
[0020] Optionally, both the first coil device and the second coil device include inductors.
[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0022] In the semiconductor structure provided in this embodiment of the invention, a first signal lead is electrically connected to a first coil device and a first signal pad, a second signal lead is electrically connected to a first coil device and a second signal pad, a third signal lead is electrically connected to a second coil device and a first signal pad, and a fourth signal lead is electrically connected to a second coil device and a second signal pad. This allows the test path formed by the first coil device, the first signal pad, and the second signal pad to be connected in parallel with the test path formed by the second coil device, the first signal pad, and the second signal pad. Consequently, the difference between the overall parasitic capacitance of the first coil device, the second coil device, the first signal pad, and the second signal pad and the parasitic capacitance of the first signal pad and the second signal pad increases, thereby improving the accuracy of obtaining the capacitance values of the first coil device and the second coil device through parasitic capacitance de-embedding. This, in turn, helps to improve the accuracy of parameter measurement of the device coils (e.g., the first device coil and the second device coil).
[0023] In the semiconductor structure formation method provided by the embodiments of the present invention, a first coil device is formed in a first device region, a second coil device is formed in a second device region, a first signal lead is formed to electrically connect the first coil device and the first signal pad, a second signal lead is formed to electrically connect the first coil device and the second signal pad, a third signal lead is formed to electrically connect the second coil device and the first signal pad, and a fourth signal lead is formed to electrically connect the second coil device and the second signal pad. This allows the test path formed by the first coil device, the first signal pad, and the second signal pad to be connected in parallel with the test path formed by the second coil device, the first signal pad, and the second signal pad. Correspondingly, the difference between the overall parasitic capacitance of the first coil device, the second coil device, the first signal pad, and the second signal pad, and the parasitic capacitance of the first signal pad and the second signal pad, increases, thereby improving the accuracy of obtaining the capacitance values of the first coil device and the second coil device through parasitic capacitance de-embedding. This, in turn, helps to improve the accuracy of parameter measurement of the device coils (e.g., the first device coil and the second device coil). Attached Figure Description
[0024] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
[0025] Figure 2 This is a frequency-capacitance schematic diagram of an embodiment of the semiconductor structure of the present invention;
[0026] Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;
[0027] Figure 6 This is a frequency-capacitance schematic diagram of one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0028] As can be seen from the background technology, the accuracy of parameter measurement of sensing devices needs to be improved.
[0029] To address the technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a first device region and a second device region arranged along a first direction, and a loading region located between the first device region and the second device region; a first signal pad located in the loading region; a second signal pad located in the loading region on the side of the first signal pad, and the second signal pad and the first signal pad being arranged along the first direction; a first coil device located in the first device region; a second coil device located in the second device region; a first signal lead electrically connecting the first coil device and the first signal pad; a second signal lead electrically connecting the first coil device and the second signal pad; a third signal lead electrically connecting the second coil device and the first signal pad; and a fourth signal lead electrically connecting the second coil device and the second signal pad.
[0030] In the semiconductor structure provided in this embodiment of the invention, a first signal lead is electrically connected to a first coil device and a first signal pad, a second signal lead is electrically connected to a first coil device and a second signal pad, a third signal lead is electrically connected to a second coil device and a first signal pad, and a fourth signal lead is electrically connected to a second coil device and a second signal pad. This allows the test path formed by the first coil device, the first signal pad, and the second signal pad to be connected in parallel with the test path formed by the second coil device, the first signal pad, and the second signal pad. Consequently, the difference between the overall parasitic capacitance of the first coil device, the second coil device, the first signal pad, and the second signal pad and the parasitic capacitance of the first signal pad and the second signal pad increases, thereby improving the accuracy of obtaining the capacitance values of the first coil device and the second coil device through parasitic capacitance de-embedding. This, in turn, helps to improve the accuracy of parameter measurement of the device coils (e.g., the first device coil and the second device coil).
[0031] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0032] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
[0033] refer to Figure 1 The semiconductor structure includes: a substrate (not shown), including components along a first direction (such as...). Figure 1 The device includes a first device region 100a and a second device region 100c arranged in the X direction, and a loading region 100b located between the first device region 100a and the second device region 100c; a first signal pad 110 located in the loading region 100b; a second signal pad 111 located in the loading region 100b on the side of the first signal pad 110, and the second signal pad 111 and the first signal pad 110 are arranged along the first direction; a first coil device 100 located in the first device region 100a; a second coil device 103 located in the second device region 100c; a first signal lead 113 electrically connecting the first coil device 100 and the first signal pad 110; a second signal lead 112 electrically connecting the first coil device 100 and the second signal pad 111; a third signal lead 114 electrically connecting the second coil device 103 and the first signal pad 110; and a fourth signal lead 115 electrically connecting the second coil device 103 and the second signal pad 111.
[0034] It should be noted that the first signal lead 113 is electrically connected to the first coil device 100 and the first signal pad 110; the second signal lead 112 is electrically connected to the first coil device 100 and the second signal pad 111; the third signal lead 114 is electrically connected to the second coil device 103 and the first signal pad 110; and the fourth signal lead 115 is electrically connected to the second coil device 103 and the second signal pad 111. This ensures that the test path formed by the first coil device 100, the first signal pad 110, and the second signal pad 111 is connected to the test path formed by the second coil device 103 and the first signal pad 111. The test path formed by 110 and the second signal pad 111 is connected in parallel. Accordingly, the difference between the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110 and the second signal pad 111 and the parasitic capacitance of the first signal pad 110 and the second signal pad 111 increases, thereby improving the accuracy of obtaining the capacitance value of the first coil device 100 and the second coil device 103 by de-embedding through parasitic capacitance. This is beneficial to improving the accuracy of parameter measurement of device coils (e.g., the first device coil and the second device coil).
[0035] The substrate is used to provide a process platform for the fabrication of semiconductor structures.
[0036] In this embodiment, the substrate includes a first device region 100a and a second device region 100c arranged along a first direction, and a loading region 100b located between the first device region 100a and the second device region 100c.
[0037] Specifically, the first device area 100a is used to set the first coil device 100, the second device area 100c is used to set the second coil device 103, and the loading area 100b is used to set the first signal pad 110 and the second signal pad 111, so that the first coil device 100 and the second coil device 103 can be loaded with signals through the first signal pad 110 and the second signal pad 111.
[0038] It should be noted that the first coil device 100 and the second coil device 103 are used as induction devices.
[0039] In CMOS radio frequency integrated circuits, sensing devices are important electrical components, and their performance parameters directly affect the performance of the integrated circuit.
[0040] As an example, both the first coil device 100 and the second coil device 103 include inductors.
[0041] In this embodiment, both the first coil device 100 and the second coil device 103 are single-turn coil devices.
[0042] It should be noted that the capacitance value of a single-turn coil device is relatively small. By connecting the test path formed by the first coil device 100, the first signal pad 110, and the second signal pad 111 in parallel with the test path formed by the second coil device 103, the first signal pad 110, and the second signal pad 111, the difference between the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110, and the second signal pad 111 and the parasitic capacitance of the first signal pad 110 and the second signal pad 111 increases. This improves the accuracy of obtaining the capacitance values of the first coil device 100 and the second coil device 103 through parasitic capacitance de-embedding. Therefore, this method is suitable for the semiconductor structure provided in this embodiment.
[0043] In other embodiments, the number of turns of the coil device is not limited.
[0044] It should be noted that the first signal pad 110 is used to load signals for the first coil device 100 and the second coil device 103.
[0045] In this embodiment, the material of the first signal pad 110 is a conductive material, including Cu, W or Al.
[0046] Specifically, the second signal pad 111 is used to load signals for the first coil device 100 and the second coil device 103.
[0047] In this embodiment, the material of the second signal pad 111 is a conductive material, including Cu, W or Al.
[0048] It should be noted that the first signal lead 113 is electrically connected to the first coil device 100 and the first signal pad 110, the second signal lead 112 is electrically connected to the first coil device 100 and the second signal pad 111, the third signal lead 114 is electrically connected to the second coil device 103 and the first signal pad 110, and the fourth signal lead 115 is electrically connected to the second coil device 103 and the second signal pad 111, so that the test path formed by the first coil device 100, the first signal pad 110 and the second signal pad 111 is connected in parallel with the test path formed by the second coil device 103, the first signal pad 110 and the second signal pad 111.
[0049] It should also be noted that the test path formed by the first coil device 100, the first signal pad 110, and the second signal pad 111 is connected in parallel with the test path formed by the second coil device 103, the first signal pad 110, and the second signal pad 111. This allows the difference between the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110, and the second signal pad 111 and the parasitic capacitance of the first signal pad 110 and the second signal pad 111 to increase. This improves the accuracy of obtaining the capacitance values of the first coil device 100 and the second coil device 103 through parasitic capacitance de-embedding, and thus helps to improve the accuracy of parameter measurement of device coils (e.g., the first device coil and the second device coil).
[0050] Specifically, parasitic capacitance removal refers to obtaining the capacitance of the first coil device 100 and the second coil device 103 by acquiring the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110, and the second signal pad 111, and then subtracting the parasitic capacitance of the first signal pad 110 and the second signal pad 111.
[0051] In this embodiment, the first signal lead 113 extends from the loading area 100b to the first device area 100a and is electrically connected to the first device coil, thereby realizing the signal loading of the first coil device 100.
[0052] In this embodiment, the material of the first signal lead 113 is a conductive material, including Cu, W or Al.
[0053] In this embodiment, the second signal lead 112 extends from the loading area 100b to the first device area 100a and is electrically connected to the first coil device, thereby realizing the signal loading of the first coil device 100.
[0054] In this embodiment, the material of the second signal lead 112 is a conductive material, including Cu, W or Al.
[0055] In this embodiment, the third signal lead 114 extends from the loading area 100b to the second device area 100c and is electrically connected to the second device coil, thereby realizing the signal loading of the second coil device 103.
[0056] In this embodiment, the material of the third signal lead 114 is a conductive material, including Cu, W or Al.
[0057] In this embodiment, the fourth signal lead 115 extends from the loading area 100b to the second device area 100c and is electrically connected to the second device coil, thereby realizing the signal loading of the second coil device 103.
[0058] In this embodiment, the material of the fourth signal lead 115 is a conductive material, including Cu, W or Al.
[0059] As an example, the overall structure consisting of the first coil device 100, the first signal lead 113, the second signal lead 112, and the first signal pad 110 is symmetrical to the overall structure consisting of the second coil device 103, the third signal lead 114, the fourth signal lead 115, and the second signal pad 111.
[0060] It should be noted that the overall structure consisting of the first coil device 100, the first signal lead 113, the second signal lead 112, and the first signal pad 110 is symmetrical with the overall structure consisting of the second coil device 103, the third signal lead 114, the fourth signal lead 115, and the second signal pad 111. This can reduce the impedance discontinuity encountered by the loaded signal at the first signal pad 110 and the second signal pad 111, thereby reducing signal reflection from the first signal pad 110 to the second signal pad 111, or reducing signal reflection from the second signal pad 111 to the first signal pad 110, which in turn helps to improve the stability and reliability of the loaded signal.
[0061] In this embodiment, the semiconductor structure further includes a first through-hole interconnect structure (not shown), located between the first signal pad 110 and the first signal lead 113, and the first signal lead 113 is electrically connected to the first signal pad 110 through the first through-hole interconnect structure.
[0062] The first through-hole interconnect structure is used to realize the electrical connection between the first signal pad 110 and the first signal lead 113.
[0063] In this embodiment, the material of the first through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0064] In this embodiment, the semiconductor structure further includes a second through-hole interconnect structure (not shown), located between the second signal pad 111 and the second signal lead 112, and the second signal lead 112 is electrically connected to the second signal pad 111 through the second through-hole interconnect structure.
[0065] The second through-hole interconnect structure is used to realize the electrical connection between the second signal pad 111 and the second signal lead 112.
[0066] In this embodiment, the material of the second through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0067] In this embodiment, the semiconductor structure further includes a third through-hole interconnect structure (not shown), located between the first signal pad 110 and the third signal lead 114, and the third signal lead 114 is electrically connected to the first signal pad 110 through the third through-hole interconnect structure.
[0068] The third through-hole interconnect structure is used to realize the electrical connection between the first signal pad 110 and the third signal lead 114.
[0069] In this embodiment, the material of the third through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0070] In this embodiment, the semiconductor structure further includes a fourth through-hole interconnect structure (not shown), located between the second signal pad 111 and the fourth signal lead 115, and the fourth signal lead 115 is electrically connected to the second signal pad 111 through the fourth through-hole interconnect structure.
[0071] The fourth through-hole interconnect structure is used to realize the electrical connection between the second signal pad 111 and the fourth signal lead 115.
[0072] In this embodiment, the material of the fourth through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0073] In this embodiment, the semiconductor structure further includes a first shielding ring structure 101 located at the bottom of the first coil device 100, and the projection of the first coil device 100 on the substrate is located within the area of the projection of the first shielding ring structure 101 on the substrate.
[0074] In this embodiment, the first shielding ring structure 101 is used to isolate the first coil device 100 and the substrate, thereby reducing substrate loss.
[0075] In integrated circuits, a key indicator for evaluating the performance of sensing devices is the quality factor (Q). A higher quality factor indicates better performance. One important factor affecting the quality factor of a sensing device is substrate loss at high frequencies.
[0076] In this embodiment, the first shielding ring structure 101 is located at the bottom of the first coil device 100. The first shielding ring structure 101 is used to shield the electric field lines and induced magnetic field lines of the first coil device 100, so that most of the electric field lines and induced magnetic field lines generated by the first coil device 100 terminate at the first shielding ring structure 101 and do not enter the substrate, thereby reducing substrate loss and correspondingly improving the quality factor of the sensing device.
[0077] Specifically, the first shielding ring structure 101 is a patterned ground shield (PGS) structure.
[0078] In this embodiment, the noise current generated in the first shielding ring structure 101 is grounded through the grounding of the first shielding ring structure 101.
[0079] In this embodiment, the semiconductor structure further includes: a first grounding pad 120, located in the loading region 100b, and along a second direction (e.g., Figure 1 The first signal pads (as shown in the Y direction) are distributed on both sides of the first signal pad 110, with the first direction and the second direction being perpendicular to each other.
[0080] The first grounding pad 120 is used to ground the first shielding ring structure 101.
[0081] In this embodiment, the material of the first grounding pad 120 is a conductive material, including Cu, W or Al.
[0082] In this embodiment, the semiconductor structure further includes: a first ground lead 140, which electrically connects the first ground pad 120 and the first shielding ring structure 101.
[0083] The first grounding lead 140 is used to electrically connect the first grounding pad 120 and the first shielding ring structure 101, so that the first shielding ring structure 101 is grounded.
[0084] In this embodiment, the first grounding lead 140 extends from the loading area 100b to the first device area 100a and is electrically connected to the first shielding ring structure 101, thereby realizing the signal loading of the first shielding ring structure 101.
[0085] In this embodiment, the material of the first grounding lead 140 is a conductive material, including Cu, W or Al.
[0086] In this embodiment, the semiconductor structure further includes a second shielding ring structure 102, located at the bottom of the second coil device 103, and the projection of the second coil device 103 on the substrate is located within the area of the projection of the second shielding ring structure 102 on the substrate.
[0087] In this embodiment, the second shielding ring structure 102 is used to isolate the second coil device 103 and the substrate, thereby reducing substrate loss.
[0088] In integrated circuits, a key indicator for evaluating the performance of sensing devices is the quality factor (Q). A higher quality factor indicates better performance. One important factor affecting the quality factor of a sensing device is substrate loss at high frequencies.
[0089] In this embodiment, the second shielding ring structure 102 is located at the bottom of the second coil device 103. The second shielding ring structure 102 is used to shield the electric field lines and induced magnetic field lines of the second coil device 103, so that most of the electric field lines and induced magnetic field lines generated by the second coil device 103 terminate at the second shielding ring structure 102 and do not enter the substrate, thereby reducing substrate loss and correspondingly improving the quality factor of the sensing device.
[0090] Specifically, the second shielding ring structure 102 is a patterned ground shield (PGS) structure.
[0091] In this embodiment, the noise current generated in the second shielding ring structure 102 is grounded through the grounding of the second shielding ring structure 102.
[0092] In this embodiment, the semiconductor structure further includes: a second grounding pad 122, located in the loading region 100b, and distributed on both sides of the second signal pad 111 along the second direction, wherein the first direction and the second direction are perpendicular to each other.
[0093] The second grounding pad 122 is used to ground the second shielding ring structure 102.
[0094] In this embodiment, the material of the second grounding pad 122 is a conductive material, including Cu, W or Al.
[0095] In this embodiment, the semiconductor structure further includes: a second ground lead 141, which is electrically connected to the second ground pad 122 and the second shielding ring structure 102.
[0096] The second grounding lead 141 is used to electrically connect the second grounding pad 122 and the second shielding ring structure 102, so that the second shielding ring structure 102 is grounded.
[0097] In this embodiment, the second grounding lead 141 extends from the loading area 100b to the second device area 100c and is electrically connected to the second shielding ring structure 102, thereby realizing the signal loading of the second shielding ring structure 102.
[0098] In this embodiment, the material of the second grounding lead 141 is a conductive material, including Cu, W or Al.
[0099] In this embodiment, the first signal pad 110 and the first ground pad 120, as well as the second signal pad 111 and the second ground pad 122, constitute a ground-signal-ground (GSG) structure.
[0100] Specifically, refer to Figure 2 The horizontal axis represents frequency, and the vertical axis represents capacitance value. Figure 2(a) represents the difference between the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110, and the second signal pad 111 in a conventional semiconductor structure, and the parasitic capacitance of the first signal pad 110 and the second signal pad 111. Figure 2 (b) indicates the difference between the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110, and the second signal pad 111 and the parasitic capacitance of the first signal pad 110 and the second signal pad 111 in the semiconductor structure of the present invention. It can be seen that by adopting the semiconductor structure of the present invention, the difference between the overall parasitic capacitance of the first coil device 100, the second coil device 103, the first signal pad 110, and the second signal pad 111 and the parasitic capacitance of the first signal pad 110 and the second signal pad 111 can be increased, thereby improving the accuracy of obtaining the capacitance value of the first coil device 100 and the second coil device 103 by de-embedding the parasitic capacitance, which in turn helps to improve the accuracy of parameter measurement of coil devices (e.g., the first coil device and the second coil device).
[0101] Accordingly, the present invention also provides a method for forming a semiconductor structure. Wherein, Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0102] refer to Figure 3 Provides a substrate (not shown), the substrate including components along a first direction (e.g.) Figure 3 The first device region 200a and the second device region 200c are arranged in the X direction, and the loading region 200b is located between the first device region 200a and the second device region 200c.
[0103] The substrate is used to provide a process platform for the fabrication of semiconductor structures.
[0104] In this embodiment, the substrate includes a first device region 200a and a second device region 200c arranged along a first direction, and a loading region 200b located between the first device region 200a and the second device region 200c.
[0105] Specifically, the first device area 200a is used to set the first coil device, the second device area 200c is used to set the second coil device, and the loading area 200b is used to set the first signal pad and the second signal pad, so that the first coil device can be loaded with signals through the first signal pad and the second signal pad, and the second coil device can be loaded with signals through the first signal pad and the second signal pad.
[0106] Continue to refer to Figure 3A first signal pad 210 and a second signal pad 211 are formed in the loading area 200b. The second signal pad 211 is located on the side of the first signal pad 210, and the second signal pad 211 and the first signal pad 210 are arranged along a first direction.
[0107] It should be noted that the first signal pad 210 is used to load signals for the subsequently formed first coil device and second coil device.
[0108] In this embodiment, the material of the first signal pad 210 is a conductive material, including Cu, W or Al.
[0109] Specifically, the second signal pad 211 is used to load signals for the subsequently formed first and second coil devices.
[0110] In this embodiment, the material of the second signal pad 211 is a conductive material, including Cu, W or Al.
[0111] In this embodiment, the step of forming the first signal pad 210 further includes: forming a first grounding pad 220 in the loading area 200b that is distributed on both sides of the first signal pad 210 along a second direction, wherein the first direction and the second direction are perpendicular to each other.
[0112] Specifically, the first grounding pad 220 is used to ground the subsequently formed first shielding ring structure.
[0113] In this embodiment, the material of the first grounding pad 220 is a conductive material, including Cu, W or Al.
[0114] In this embodiment, the step of forming the second signal pad 211 further includes: forming a second grounding pad 222 in the loading area 200b that is distributed on both sides of the second signal pad 211 along a second direction, wherein the first direction is perpendicular to the second direction.
[0115] Specifically, the second grounding pad 222 is used to ground the second shielding ring structure.
[0116] In this embodiment, the material of the second grounding pad 222 is a conductive material, including Cu, W or Al.
[0117] Continue to refer to Figure 3 A first shielding ring structure 201 is formed in the first device region 200a, and a second shielding ring structure 202 is formed in the second device region 200c.
[0118] It should be noted that the first shielding ring structure 201 is used to isolate the subsequently formed first coil device and the substrate, thereby reducing substrate loss.
[0119] In integrated circuits, a key indicator for evaluating the performance of sensing devices is the quality factor (Q). A higher quality factor indicates better performance. One important factor affecting the quality factor of a sensing device is substrate loss at high frequencies.
[0120] Specifically, the first shielding ring structure 201 is a patterned ground shield (PGS) structure.
[0121] In this embodiment, the noise current generated in the first shielding ring structure 201 is grounded through the grounding of the first shielding ring structure 201.
[0122] It should be noted that the second shielding ring structure 202 is used to isolate the second coil device and the substrate, thereby reducing substrate loss.
[0123] In integrated circuits, a key indicator for evaluating the performance of sensing devices is the quality factor (Q). A higher quality factor indicates better performance. One important factor affecting the quality factor of a sensing device is substrate loss at high frequencies.
[0124] In this embodiment, the second shielding ring structure 202 is located at the bottom of the second coil device. The second shielding ring structure 202 is used to shield the electric field lines and induced magnetic field lines of the second coil device, so that most of the electric field lines and induced magnetic field lines generated by the second coil device terminate at the second shielding ring structure 202 and do not enter the substrate, thereby reducing substrate loss and improving the quality factor of the sensing device accordingly.
[0125] Specifically, the second shielding ring structure 202 is a patterned ground shield (PGS) structure.
[0126] In this embodiment, the noise current generated in the second shielding ring structure 202 is grounded through the grounding of the second shielding ring structure 202.
[0127] refer to Figure 4 The first grounding lead 240 forms an electrical connection between the first grounding pad 220 and the first shielding ring structure 201.
[0128] The first grounding lead 240 is used to electrically connect the first grounding pad 220 and the first shielding ring structure 201, so that the first shielding ring structure 201 is grounded.
[0129] In this embodiment, the first grounding lead 240 extends from the loading area 200b to the first device area 200a and is electrically connected to the first shielding ring structure 201, thereby realizing the signal loading of the first shielding ring structure 201.
[0130] In this embodiment, the material of the first grounding lead 240 is a conductive material, including Cu, W or Al.
[0131] Continue to refer to Figure 4 This forms the second grounding lead 241 that electrically connects the second grounding pad 222 and the second shielding ring structure 202.
[0132] The second grounding lead 241 is used to electrically connect the second grounding pad 222 and the second shielding ring structure 202, so that the second shielding ring structure 202 is grounded.
[0133] In this embodiment, the second grounding lead 241 extends from the loading area 200b to the second device area 200c and is electrically connected to the second shielding ring structure 202, thereby realizing the signal loading of the second shielding ring structure 202.
[0134] In this embodiment, the material of the second grounding lead 241 is a conductive material, including Cu, W or Al.
[0135] In this embodiment, the first signal pad 210 and the first ground pad 220, as well as the second signal pad 211 and the second ground pad 222, constitute a ground-signal-ground (GSG) structure.
[0136] Continue to refer to Figure 4 A first coil device 200 is formed in the first device region 200a, and a second coil device 203 is formed in the second device region 200c.
[0137] It should be noted that the first coil device 200 and the second coil device 203 are used as induction devices.
[0138] In CMOS radio frequency integrated circuits, sensing devices are important electrical components, and their performance parameters directly affect the performance of the integrated circuit.
[0139] As an example, both the first coil device 200 and the second coil device 203 include inductors.
[0140] In this embodiment, both the first coil device 200 and the second coil device 203 are single-turn coil devices.
[0141] It should be noted that the capacitance value of a single-turn coil device is relatively small. By connecting the test path formed by the first coil device 200, the first signal pad 210, and the second signal pad 211 in parallel with the test path formed by the second coil device 203, the first signal pad 210, and the second signal pad 211, the difference between the overall parasitic capacitance of the first coil device 200, the second coil device 203, the first signal pad 210, and the second signal pad 211 and the parasitic capacitance of the first signal pad 210 and the second signal pad 211 increases. This improves the accuracy of obtaining the capacitance values of the first coil device 200 and the second coil device 203 through parasitic capacitance de-embedding. Therefore, this method is suitable for the semiconductor structure provided in this embodiment.
[0142] In other embodiments, the number of turns of the coil device is not limited.
[0143] In this embodiment, in the step of forming the first coil device 200, the first coil device 200 is formed on the top of the first shielding ring structure 201, and the projection of the first coil device 200 on the substrate is located within the area of the projection of the first shielding ring structure 201 on the substrate.
[0144] It should be noted that the first coil device 200 is formed on the top of the first shielding ring structure 201. The first shielding ring structure 201 is used to shield the electric field lines and induced magnetic field lines of the first coil device 200, so that most of the electric field lines and induced magnetic field lines generated by the first coil device 200 terminate at the first shielding ring structure 201 and do not enter the substrate, thereby reducing substrate loss and correspondingly improving the quality factor of the sensing device.
[0145] In this embodiment, in the step of forming the second coil device 203, the second coil device 203 is formed on the top of the second shielding ring structure 202, and the projection of the second coil device 203 on the substrate is located within the area of the projection of the second shielding ring structure 202 on the substrate.
[0146] Specifically, the second coil device 203 is formed on the top of the second shielding ring structure 202. The second shielding ring structure 202 is used to shield the electric field lines and induced magnetic field lines of the second coil device 203, so that most of the electric field lines and induced magnetic field lines generated by the second coil device 203 terminate at the second shielding ring structure 202 and do not enter the substrate, thereby reducing substrate loss and correspondingly improving the quality factor of the sensing device.
[0147] refer to Figure 5A first signal lead 213 is formed that electrically connects the first coil device 200 and the first signal pad 210; a second signal lead 212 is formed that electrically connects the first coil device 200 and the second signal pad 211; a third signal lead 214 is formed that electrically connects the second coil device 203 and the first signal pad 210; and a fourth signal lead 215 is formed that electrically connects the second coil device 203 and the second signal pad 211.
[0148] It should be noted that a first coil device 200 is formed in the first device region 200a, and a second coil device 203 is formed in the second device region 200c. A first signal lead 213 is formed to electrically connect the first coil device 200 and the first signal pad 210; a second signal lead 212 is formed to electrically connect the first coil device 200 and the second signal pad 211; a third signal lead 214 is formed to electrically connect the second coil device 203 and the first signal pad 210; and a fourth signal lead 215 is formed to electrically connect the second coil device 203 and the second signal pad 211. This allows the first coil device 200, the first signal pad 210, and the second signal pad 211 to be connected. The test path formed by pad 211 is connected in parallel with the test path formed by the second coil device 203, the first signal pad 210, and the second signal pad 211. Correspondingly, the difference between the overall parasitic capacitance of the first coil device 200, the second coil device 203, the first signal pad 210, and the second signal pad 211 and the parasitic capacitance of the first signal pad 210 and the second signal pad 211 increases, thereby improving the accuracy of obtaining the capacitance values of the first coil device 200 and the second coil device 203 by de-embedding through parasitic capacitance, which in turn helps to improve the accuracy of parameter measurement of coil devices (such as the first coil device and the second coil device).
[0149] Specifically, parasitic capacitance removal refers to obtaining the capacitance of the first coil device 200 and the second coil device 203 by acquiring the overall parasitic capacitance of the first coil device 200, the second coil device 203, the first signal pad 210 and the second signal pad 211, and then subtracting the parasitic capacitance of the first signal pad 210 and the second signal pad 211.
[0150] In this embodiment, the first signal lead 213 extends from the loading area 200b to the first device area 200a and is electrically connected to the first device coil, thereby realizing the signal loading of the first coil device 200.
[0151] In this embodiment, the material of the first signal lead 213 is a conductive material, including Cu, W or Al.
[0152] In this embodiment, the second signal lead 212 extends from the loading area 200b to the first device area 200a and is electrically connected to the first device coil, thereby realizing the signal loading of the first coil device 200.
[0153] In this embodiment, the material of the second signal lead 212 is a conductive material, including Cu, W or Al.
[0154] In this embodiment, the third signal lead 214 extends from the loading area 200b to the second device area 200c and is electrically connected to the second device coil, thereby realizing the signal loading of the second coil device 203.
[0155] In this embodiment, the material of the third signal lead 214 is a conductive material, including Cu, W or Al.
[0156] In this embodiment, the fourth signal lead 215 extends from the loading area 200b to the second device area 200c and is electrically connected to the second device coil, thereby realizing the signal loading of the second coil device 203.
[0157] In this embodiment, the material of the fourth signal lead 215 is a conductive material, including Cu, W or Al.
[0158] In this embodiment, in the steps of forming the first signal lead 213, the second signal lead 212, the third signal lead 214, and the fourth signal lead 215, the overall structure formed by the first coil device 200, the first signal lead 213, the second signal lead 212, and the first signal pad 210 is symmetrical to the overall structure formed by the second coil device 203, the third signal lead 214, the fourth signal lead 215, and the second signal pad 211.
[0159] It should be noted that the overall structure consisting of the first coil device 200, the first signal lead 213, the second signal lead 212, and the first signal pad 210 is symmetrical with the overall structure consisting of the second coil device 203, the third signal lead 214, the fourth signal lead 215, and the second signal pad 211. This can reduce the impedance discontinuity encountered by the loaded signal at the first signal pad 210 and the second signal pad 211, thereby reducing signal reflection from the first signal pad 210 to the second signal pad 211, or reducing signal reflection from the second signal pad 211 to the first signal pad 210, which in turn helps to improve the stability and reliability of the loaded signal.
[0160] In this embodiment, the step of forming the first signal lead 213 further includes: forming a first through-hole interconnect structure on the top of the first signal pad 210, and the first signal lead 213 is electrically connected to the first signal pad 210 through the first through-hole interconnect structure.
[0161] The first through-hole interconnect structure is used to realize the electrical connection between the first signal pad 210 and the first signal lead 213.
[0162] In this embodiment, the material of the first through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0163] In this embodiment, the step of forming the second signal lead 212 further includes: forming a second through-hole interconnect structure on the top of the second signal pad 211, and the second signal lead 212 is electrically connected to the second signal pad 211 through the second through-hole interconnect structure.
[0164] The second through-hole interconnect structure is used to realize the electrical connection between the second signal pad 211 and the second signal lead 212.
[0165] In this embodiment, the material of the second through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0166] In this embodiment, the step of forming the third signal lead 214 further includes: forming a third through-hole interconnect structure on the top of the first signal pad 210, and the third signal lead 214 is electrically connected to the first signal pad 210 through the third through-hole interconnect structure.
[0167] The third through-hole interconnect structure is used to realize the electrical connection between the first signal pad 210 and the third signal lead 214.
[0168] In this embodiment, the material of the third through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0169] In this embodiment, the step of forming the fourth signal lead 215 further includes: forming a fourth through-hole interconnect structure on the top of the second signal pad 211, and the fourth signal lead 215 is electrically connected to the second signal pad 211 through the fourth through-hole interconnect structure.
[0170] The fourth through-hole interconnect structure is used to realize the electrical connection between the second signal pad 211 and the fourth signal lead 215.
[0171] In this embodiment, the material of the fourth through-hole interconnect structure is a conductive material, including Cu, W, or Al.
[0172] Specifically, refer to Figure 6 The horizontal axis represents frequency, and the vertical axis represents capacitance value. Figure 6 (a) represents the difference between the overall parasitic capacitance of the first coil device 200, the second coil device 203, the first signal pad 210, and the second signal pad 211 in a conventional semiconductor structure, and the parasitic capacitance of the first signal pad 210 and the second signal pad 211. Figure 6(b) indicates the difference between the overall parasitic capacitance of the first coil device 200, the second coil device 203, the first signal pad 210, and the second signal pad 211 and the parasitic capacitance of the first signal pad 210 and the second signal pad 211 in the semiconductor structure of the present invention. It can be seen that by adopting the semiconductor structure of the present invention, the difference between the overall parasitic capacitance of the first coil device 200, the second coil device 203, the first signal pad 210, and the second signal pad 211 and the parasitic capacitance of the first signal pad 210 and the second signal pad 211 can be increased, thereby improving the accuracy of obtaining the capacitance value of the first coil device 200 and the second coil device 203 by de-embedding the parasitic capacitance, which in turn helps to improve the accuracy of the measurement of the parameters of the device coils (e.g., the first device coil and the second device coil).
[0173] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a first device region and a second device region arranged along a first direction, and a loading region located between the first device region and the second device region; The first signal pad is located in the loading area; The second signal pad is located in the loading area on the side of the first signal pad, and the second signal pad and the first signal pad are arranged along the first direction. The first coil device is located in the first device area; The second coil device is located in the second device area; The first signal lead is electrically connected to the first coil device and the first signal pad; The second signal lead is electrically connected to the first coil device and the second signal pad; The third signal lead is electrically connected to the second coil device and the first signal pad; The fourth signal lead is electrically connected to the second coil device and the second signal pad.
2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first through-hole interconnect structure located between the first signal pad and the first signal lead, wherein the first signal lead is electrically connected to the first signal pad through the first through-hole interconnect structure; The second through-hole interconnect structure is located between the second signal pad and the second signal lead, and the second signal lead is electrically connected to the second signal pad through the second through-hole interconnect structure; The third through-hole interconnect structure is located between the first signal pad and the third signal lead, and the third signal lead is electrically connected to the first signal pad through the third through-hole interconnect structure; A fourth through-hole interconnect structure is located between the second signal pad and the fourth signal lead, and the fourth signal lead is electrically connected to the second signal pad through the fourth through-hole interconnect structure.
3. The semiconductor structure as described in claim 1, characterized in that, The overall structure consisting of the first coil device, the first signal lead, the second signal lead, and the first signal pad is symmetrical to the overall structure consisting of the second coil device, the third signal lead, the fourth signal lead, and the second signal pad.
4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first shielding ring structure located at the bottom of the first coil device, wherein the projection of the first coil device on the substrate is within the area of the projection of the first shielding ring structure on the substrate.
5. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes: a first grounding pad located in the loading region and distributed on both sides of the first signal pad along a second direction, wherein the first direction and the second direction are perpendicular to each other; The first grounding lead is electrically connected to the first grounding pad and the first shielding ring structure.
6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a second shielding ring structure located at the bottom of the second coil device, wherein the projection of the second coil device on the substrate is within the area of the projection of the second shielding ring structure on the substrate.
7. The semiconductor structure as described in claim 6, characterized in that, The semiconductor structure further includes: a second grounding pad located in the loading region and distributed on both sides of the second signal pad along a second direction, wherein the first direction and the second direction are perpendicular to each other; The second grounding lead is electrically connected to the second grounding pad and the second shielding ring structure.
8. The semiconductor structure as described in claim 1, characterized in that, Both the first coil device and the second coil device include inductors.
9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region and a second device region arranged along a first direction, and a loading region located between the first device region and the second device region; A first signal pad and a second signal pad are formed in the loading area. The second signal pad is located on the side of the first signal pad, and the second signal pad and the first signal pad are arranged along the first direction. A first coil device is formed in the first device region, and a second coil device is formed in the second device region; A first signal lead is formed to electrically connect the first coil device and the first signal pad; a second signal lead is formed to electrically connect the first coil device and the second signal pad; a third signal lead is formed to electrically connect the second coil device and the first signal pad; and a fourth signal lead is formed to electrically connect the second coil device and the second signal pad.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the first signal lead further includes: forming a first through-hole interconnect structure on the top of the first signal pad, wherein the first signal lead is electrically connected to the first signal pad through the first through-hole interconnect structure; The step of forming the second signal lead further includes: forming a second through-hole interconnect structure on the top of the second signal pad, wherein the second signal lead is electrically connected to the second signal pad through the second through-hole interconnect structure; The step of forming the third signal lead further includes: forming a third through-hole interconnect structure on the top of the first signal pad, wherein the third signal lead is electrically connected to the first signal pad through the third through-hole interconnect structure; The step of forming the fourth signal lead further includes: forming a fourth through-hole interconnect structure on the top of the second signal pad, wherein the fourth signal lead is electrically connected to the second signal pad through the fourth through-hole interconnect structure.
11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the steps of forming the first signal lead, the second signal lead, the third signal lead, and the fourth signal lead, the overall structure formed by the first coil device, the first signal lead, the second signal lead, and the first signal pad is symmetrical to the overall structure formed by the second coil device, the third signal lead, the fourth signal lead, and the second signal pad.
12. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the first coil device and the second coil device, the method for forming the semiconductor structure further includes: forming a first shielding ring structure in the first device region and forming a second shielding ring structure in the second device region; In the step of forming the first coil device, the first coil device is formed on the top of the first shielding ring structure, and the projection of the first coil device on the substrate is located within the area of the projection of the first shielding ring structure on the substrate; In the step of forming the second coil device, the second coil device is formed on top of the second shielding ring structure, and the projection of the second coil device on the substrate is located within the area of the projection of the second shielding ring structure on the substrate.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the first signal pad further includes: forming a first grounding pad distributed along a second direction on both sides of the first signal pad in the loading area, wherein the first direction is perpendicular to the second direction. The method for forming the semiconductor structure further includes: forming a first grounding lead that electrically connects the first grounding pad and the first shielding ring structure.
14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming the second signal pad further includes: forming a second grounding pad distributed along a second direction on both sides of the second signal pad in the loading area, wherein the first direction is perpendicular to the second direction; The method for forming the semiconductor structure further includes: forming a second grounding lead that electrically connects the second grounding pad and the second shielding ring structure.
15. The method for forming a semiconductor structure as described in claim 9, characterized in that, Both the first coil device and the second coil device include inductors.