Power management circuit and display device

Abstract

The present application provides a power management circuit and a display device, the power management circuit is used to control a display module, the power management circuit includes: a first input terminal; a first output terminal; a switch circuit, one end of which is connected to the first input terminal, and the second end of which is connected to the first output terminal; and a power chip, which has an enable pin and a timing pin, the enable pin can receive a start signal and a shutdown signal of the display module, and the timing pin is connected to the third end of the switch circuit; when the power chip receives the start signal of the display module from the enable pin, the power chip outputs a first control signal to the switch circuit through the timing pin to turn on the switch circuit and control the first output terminal to output an analog voltage signal. The power management circuit of the present application does not affect the operation of the enable control unit and the timing control unit in the power chip, and can realize the switch control of the switch circuit, reuse the enable pin, and reduce the hardware cost of the display device.

Description

Technical Field

[0001] The present application belongs to the technical field of display devices, and in particular, relates to a power management circuit and a display device. Background Art

[0002] The PMIC (Power Management Integrated Circuit) in the display device is mainly used to power the display panel. When the PMIC is provided with input voltage, the PMIC can output multiple voltage signals including AVDD (analog voltage), BUCK (step-down signal), VGH (high level signal), VGL (low level signal), etc.

[0003] PMIC's demand for input voltage is generally divided into two types: one is for PMIC peripheral input (for example, the input voltage generates AVDD voltage through Boost (power amplifier)), and the other is that the input voltage is directly input into the PMIC (for example, the input voltage outputs VL voltage through LDO (Low Dropout Regulator)) to generate internal logic control voltage or other outputs. In order to meet the Power ON / OFF timing of the display panel, a switching circuit is usually added to the front end of the PMIC in the prior art. The switching circuit can be composed of transistors, MOS tubes, resistors and capacitors. When the main control board outputs the display panel Power ON / OFF signal, the transistor of the switching circuit is turned on, and then the MOS tube is driven to turn on. At this time, the input voltage is input to the input port of the PMIC, and the PMIC starts working.

[0004] However, providing a switch circuit at the front end of the power management circuit will increase the hardware cost of the display device. Summary of the invention

[0005] The embodiments of the present application provide a power management circuit and a display device to solve the problem that setting a switch circuit at the front end of the power management circuit will increase the hardware cost of the display device.

[0006] An embodiment of the present application provides a power management circuit for controlling a display module, the power management circuit comprising:

[0007] A first input terminal, capable of receiving a first driving signal;

[0008] A first output terminal, capable of providing an analog voltage signal required by the display module;

[0009] a switch circuit, wherein one end of the switch circuit is connected to the first input end, and a second end of the switch circuit is connected to the first output end; and

[0010] A power chip, having an enable pin and a timing pin, wherein the enable pin can receive a start signal and a stop signal of the display module, and the timing pin is connected to the third end of the switch circuit;

[0011] When the power chip receives the start-up signal of the display module from the enable pin, the power chip outputs a first control signal to the switch circuit through the timing pin to turn on the switch circuit and control the first output terminal to output the analog voltage signal;

[0012] When the power chip receives a shutdown signal of the display module from the enable pin, the power chip outputs a second control signal to the switch circuit through the timing pin to shut down the switch circuit and disconnect the first input terminal and the first output terminal.

[0013] Optionally, the power chip includes:

[0014] A timing control unit connected to the timing pin;

[0015] an enable control unit, electrically connected to the timing control unit, the enable control unit being connected to the enable pin; and

[0016] A first input pin, the first input pin is connected to the enabling control unit, and the first input pin is connected to the first input end;

[0017] Among them, the power chip receives the first drive signal through the first input pin. When the enable pin receives the start-up signal of the display module, the enable control unit is turned on, and the power chip outputs the first control signal after the first drive signal is converted by the timing control unit to the switching circuit.

[0018] Optionally, the power management circuit further includes:

[0019] A third capacitor, one end of the third capacitor is connected to the first input pin, and the other end of the third capacitor is grounded.

[0020] Optionally, the switch circuit includes:

[0021] A first MOS transistor, wherein a gate of the first MOS transistor is connected to the timing pin, a source of the first MOS transistor is connected to the first input end, and a drain of the first MOS transistor is connected to the first output end.

[0022] Optionally, the switch circuit further includes:

[0023] A first capacitor, one end of which is connected to the source of the first MOS tube, and the other end of which is connected to the timing pin;

[0024] A second capacitor, one end of the second capacitor is connected to the drain of the first MOS tube, and the other end of the second capacitor is grounded.

[0025] Optionally, the power management circuit further includes an amplifier circuit, and the amplifier circuit is arranged between the first MOS tube and the first output end;

[0026] The power chip further includes an analog voltage control unit, which is connected to the amplifying circuit to convert the first driving signal into the analog voltage signal.

[0027] Optionally, the amplifying circuit includes:

[0028] an inductor, one end of which is connected to the drain of the first MOS tube;

[0029] a second MOS transistor, wherein a gate of the second MOS transistor is connected to the analog voltage control unit, and a drain of the second MOS transistor is connected to the other end of the inductor;

[0030] A first resistor, one end of the first resistor is connected to the source of the second MOS tube, and the other end of the first resistor is grounded.

[0031] Optionally, the power chip also includes a gate pin, a detection pin and a feedback pin, the gate pin, the detection pin and the feedback pin are all connected to the analog voltage control unit, the gate pin is connected to the gate of the second MOS tube, the detection pin is connected to the source of the second MOS tube, and the feedback pin is connected to the first output end.

[0032] Optionally, the power chip further includes a buck conversion control unit, which is electrically connected to the timing control unit, and the timing control unit controls the buck conversion control unit to output a buck signal after a delay of a first preset time length.

[0033] The present application also provides a display device, including:

[0034] Display module; and

[0035] A power management circuit is electrically connected to the display module, and the power management circuit is the power management circuit as described in any one of the above items.

[0036] In the power management circuit and display device provided in the embodiments of the present application, the enable pin and timing pin of the power chip are used to realize the switching control of the switching circuit, which does not affect the operation of the enable control unit and the timing control unit in the power chip, and can realize the switching control of the switching circuit, reuse the enable pin, and reduce the hardware cost of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0038] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings. In the following description, the same reference numerals represent the same parts.

[0039] Figure 1 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0040] Figure 2 for Figure 1 A schematic structural diagram of a power management circuit in a display device is shown.

[0041] Figure 3 for Figure 2 The working timing diagram of the power management circuit is shown. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0043] For example, see Figure 1 , Figure 1A schematic diagram of the structure of a display device provided in an embodiment of the present application. An embodiment of the present application provides a display device 1, and the display device 1 may include a display module 10, a power management circuit 20, and a main control chip 30. The display module 10 may include a display panel and a driving circuit for driving the display panel, and the display panel can display a picture. The power management circuit 20 is used to power the display module 10, that is, the power management circuit 20 can power the display panel so that the display panel can display. The main control chip 30 can send a control signal to the power management circuit 20 to control the display module 10 to turn on and off through the power management circuit 20. The display device 1 can be a mobile terminal such as a mobile phone or a tablet computer. The display device 1 can also be a device with a display function such as a television, a game device, an augmented reality (AR) device, a virtual reality (VR) device, a car computer, a laptop computer, a video playback device, a wearable device, etc., wherein the wearable device can be a smart bracelet, smart glasses, etc. The embodiment of the present application is described by taking the display device 1 as a television as an example.

[0044] It should be noted that the power management circuit 20 in the display device 1 is mainly used to power the display panel in the display module 10. When the input voltage is provided to the power management circuit 20, the power management circuit 20 can output multiple voltage signals including AVDD, BUCK, VGH, VGL, etc. The power management circuit 20 generally has two requirements for input voltage: one is for peripheral input of the power management circuit 20, for example, the input voltage can generate an analog voltage signal through a power amplifier circuit, and then the analog voltage signal is provided to the display module 10 to supply the driving chip COF IC (Chip OnFlex Integrated Circuit Chip) in the display module 10, thereby controlling the display of the display panel. The other is that the input voltage is directly input into the power management circuit 20 to generate an internal logic control voltage or other types of output. For example, the input voltage outputs a VL voltage through an LDO (Low Dropout Regulator) inside the power management circuit 20. Of course, there can be other forms of the types of voltage signals that can be output by the power management circuit 20 and the output mode, which will not be given one by one here.

[0045] Among them, in order to meet the Power ON / OFF (power switch) timing of the display module 10, in the prior art, a switch circuit is usually added to the front end of the power management circuit, and the switch circuit can be composed of a transistor, a MOS tube, and a resistor and a capacitor. When the main control chip 30 of the display device 1 outputs the Power ON / OFF signal of the display module 10, the transistor of the switch circuit is turned on, and then the MOS tube is driven to turn on. At this time, the input voltage is input to the input end of the power management circuit 20, and the power management circuit 20 starts to work. However, setting a switch circuit at the front end of the power management circuit 20 will increase the hardware cost of the display device.

[0046] In order to solve the above problems, the embodiment of the present application improves the power management circuit 20, which will be described below with reference to the accompanying drawings.

[0047] For example, please combine Figure 1 Also see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the structure of the power management circuit in the display device shown. An embodiment of the present application provides a power management circuit 20 for controlling the display module 10. The power management circuit 20 may include a first input terminal N1, a first output terminal O1, a switch circuit 21 and a power chip 23. The first input terminal N1 can receive a first drive signal, and the first drive signal can be a voltage signal, for example, the first drive signal can be a power supply voltage. The first output terminal O1 can provide an analog voltage signal required by the display module 10. One end of the switch circuit 21 is connected to the first input terminal N1, and the second end of the switch circuit 21 is connected to the first output terminal O1. The power chip 23 has an enable pin EN and a timing pin GD_O. The enable pin EN can receive a start signal and a shutdown signal of the display module 10, and the timing pin GD_O is connected to the third end of the switch circuit 21. When the power chip 23 receives a start signal of the display module 10 from the enable pin EN, the power chip 23 outputs a first control signal to the switch circuit 21 through the timing pin GD_O to turn on the switch circuit 21 and control the first output terminal O1 to output an analog voltage signal. When the power chip 23 receives a shutdown signal of the display module 10 from the enable pin EN, the power chip 23 outputs a second control signal to the switch circuit 21 through the timing pin GD_O to turn off the switch circuit 21 and disconnect the first input terminal N1 and the first output terminal O1.

[0048] In the power management circuit 20 of the embodiment of the present application, the enable pin EN and the timing pin GD_O of the power chip 23 are used to realize the switch control of the switch circuit 21, which does not affect the operation of the enable control unit and the timing control unit in the power chip 23, and can realize the switch control of the switch circuit 21. The enable pin EN is reused, thereby reducing the hardware cost of the display device 1.

[0049] Among them, the power chip 23 may include a timing control unit SC and an enable control unit ENC. The timing control unit SC is used to control the output timing of each output voltage of the power management circuit 20 to meet the different voltage requirements of the display module 10 at different times. The timing control unit SC is connected to the timing pin SD_O. The enable control unit ENC controls the input and output of the signal. The enable control unit ENC can be understood as a "switch". When the enable control unit ENC is turned on, the signal can be input and output. When the enable control unit ENC is not turned on, the signal cannot be input and output through the enable control unit ENC. The enable control unit ENC is electrically connected to the timing control unit SC. In addition, the enable control unit ENC is connected to the enable pin EN.

[0050] Exemplarily, the enabling control unit ENC can be regarded as a "switch", and the enabling control unit ENC can receive a control signal from the main control chip 30 through the enabling pin EN. The power chip 23 may also include a first input pin Vin, the first input pin Vin is connected to the enabling control unit ENC, and the first input pin Vin is connected to the first input terminal N1. It can be understood that the enabling control unit ENC receives the first driving signal of the first input terminal N1 through the first input pin Vin, that is, the first input terminal N1 can supply power to the enabling control unit ENC, and the enabling control unit ENC is turned on or off by the signal transmitted by the enabling pin EN.

[0051] Among them, the power chip 23 can receive a first drive signal from the first input terminal N1 through the first input pin Vin. When the enable pin EN receives a start signal from the display module 10, the enable control unit ENC is turned on, and the power chip 23 outputs the first control signal after the first drive signal is converted by the timing control unit SC to the switching circuit 21.

[0052] Exemplarily, the power management circuit 20 may further include a third capacitor C3, one end of the third capacitor C3 is connected to the first input pin Vin, and the other end of the third capacitor C3 is grounded GND. It should be noted that the third capacitor C3 can play a filtering role, so as to filter the first drive signal transmitted by the first input terminal N1 and transmit it to the enabling control unit ENC through the first input pin Vin.

[0053] The switch circuit 21 may be composed of various forms. Exemplarily, the switch circuit 21 may include a first MOS transistor MOS1, a gate of the first MOS transistor MOS1 connected to the timing pin GD_O, a source of the first MOS transistor MOS1 connected to the first input terminal N1, and a drain of the first MOS transistor MOS1 connected to the first output terminal O1. It is understandable that when the first MOS transistor MOS1 receives a first control signal, the first control signal may be greater than the threshold voltage of the first MOS transistor MOS1, thereby turning on the first MOS transistor MOS1, and further allowing the first drive signal input at the first input terminal N1 to be transmitted to the first output terminal O1 through the first MOS transistor MOS1. When the first MOS transistor MOS2 receives a second control signal, the second control signal may be less than the threshold voltage of the first MOS transistor MOS1, thereby turning off the first MOS transistor MOS1, that is, disconnecting the first input terminal N1 from the first output terminal O1.

[0054] It should be noted that the first MOS transistor MOS1 can be an N-type MOS transistor, or a P-type MOS transistor, which is not limited here. The above is only an example to illustrate the working process of the first MOS transistor MOS1.

[0055] The above process is the process in which the on-off signal and the off-off signal of the display module 10 sent by the main control chip 30 are transmitted to the switch circuit 21 via the enable pin EN and the timing pin SD_O. The power management circuit 20 of the embodiment of the present application reuses the enable pin EN and the enable control unit ENC, so that the switch timing control of the display module 10 and the control of each output voltage can be realized, thereby reducing the hardware cost of the display device 1.

[0056] Exemplarily, the switch circuit 21 may further include a first capacitor C1 and a second capacitor C2. One end of the first capacitor C1 is connected to the source of the first MOS tube MOS1, and the other end of the first capacitor C1 is connected to the timing pin SD_O. One end of the second capacitor C2 may be connected to the drain of the first MOS tube MOS1, and the other end of the second capacitor C2 is grounded GND. It should be noted that since the first MOS tube MOS1 is directly connected to the power chip 23, the on-off of the first MOS tube MOS1 will cause an impact on the power chip 23. In order to reduce the impact of the on-off of the first MOS tube MOS1 on the power chip 23, the first capacitor C1 and the second capacitor C2 are set as the "soft start" of the switch circuit 21, that is, the first capacitor C1 and the second capacitor C2 can play a buffering role in the on-off of the first MOS tube MOS1, so as to prevent the impact on the power chip 23 and affect the function of the power chip 23.

[0057] An interface may be provided at one end of the second capacitor C2 , and the interface may be used to detect whether the switch circuit 21 works normally.

[0058] It should be noted that, after the first drive signal passes through the first MOS tube MOS1, in order to convert the first drive signal into an analog voltage signal, a circuit for converting the first drive signal into an analog voltage signal needs to be provided between the switch circuit 21 and the first output terminal O1. Exemplarily, the power management circuit 20 may further include an amplifier circuit 25. The amplifier circuit 25 is provided between the first MOS tube MOS1 and the first output terminal O1. The power chip 23 may further include an analog voltage control unit ACL, which is connected to the amplifier circuit 25 to convert the first drive signal into an analog voltage signal.

[0059] Exemplarily, the amplifier circuit 25 may include an inductor L, a second MOS tube MOS2 and a first resistor R1. One end of the inductor L is connected to the drain of the first MOS tube MOS1. The gate of the second MOS tube MOS2 is connected to the analog voltage control unit ACL, and the drain of the second MOS tube MOS2 is connected to the other end of the inductor L. One end of the first resistor R1 is connected to the source of the second MOS tube MOS2, and the other end of the first resistor R1 is grounded GND. The amplifier circuit 25 can also be called a Boost circuit, that is, the input voltage can be converted into an analog voltage or an analog positive power supply through the Boost circuit.

[0060] Among them, an interface can be added to the drain of the second MOS transistor MOS2 to facilitate subsequent detection of the amplifying circuit 25.

[0061] In order to detect the signal output by the amplifier circuit 25 and adjust it according to the feedback of the signal output by the amplifier circuit 25, the power chip 23 also has corresponding pins to realize the above functions. Exemplarily, the power chip 23 may also include a gate pin GATE, a detection pin CS and a feedback pin FE. The gate pin GATE, the detection pin CS and the feedback pin FE are all connected to the analog voltage control unit ACL. The gate pin GATE is connected to the gate of the second MOS tube MOS2, and the analog voltage control unit ACL can adjust the output voltage of the amplifier circuit 25 through the gate pin GATE. The detection pin CS is connected to the source of the second MOS tube MOS2 to detect whether the second MOS tube MOS2 is working normally. The feedback pin FE is connected to the first output terminal O1, so that the analog voltage control unit ACL can make a judgment based on the feedback signal, and then adjust the output voltage of the amplifier circuit 25 through the gate pin GATE.

[0062] Exemplarily, the power management circuit 20 may further include a diode D1, the positive electrode of the diode D1 is connected to the other end of the inductor L, and the negative electrode of the diode D1 is connected to the first output terminal O1. The diode D1 can be arranged between the amplifier circuit 25 and the first output terminal O1 as a rectifying electrical device. The power management circuit 20 may further include a fourth capacitor C4, one end of the fourth capacitor C4 is connected to the negative electrode of the diode D1, and the other end of the fourth capacitor C4 is grounded GND. It is understandable that the fourth capacitor C4 can be used for filtering. Then the diode D1 and the fourth capacitor C4 can rectify and filter the voltage signal output by the amplifier circuit 25 and output it to the first output terminal O1, thereby meeting the voltage requirement of the display module 10.

[0063] For example, please combine Figure 1 and Figure 2 Also see Figure 3 , Figure 3 for Figure 2 The working timing diagram of the power management circuit shown. The power chip 23 may also include a buck conversion control unit BUCK, a low-level control unit VGL and other control units OC, and different control units are used to output different voltage signals to the display module 10 to facilitate the normal operation of the display module 10. The buck conversion control unit BUCK is electrically connected to the timing control unit SC, and the timing control unit SC can control the buck conversion control unit BUCK to output the buck signal after delaying for a first preset time. It should be noted that the analog voltage control unit ACL is electrically connected to the timing control unit SC, and the timing control unit SC can control the analog voltage control unit ACL to output the analog voltage signal after delaying for a second preset time. The low-level control unit VGL and other control units OC can also be electrically connected to the timing control unit SC to output corresponding voltage signals to the display module 10 through different delay time lengths. It should be noted that Figure 3 , represents the control timing of the input voltage and each output voltage. It includes the signal input of the first input pin Vin, the signal input of the enable pin EN, the buck signal output of the corresponding buck conversion unit BUCK, the output of the control signal of the timing pin SD_O, the output of the VGL voltage signal of the corresponding low-level control unit VGL, and the output of the corresponding first output terminal O1. Among them, Data load represents the situation where the power chip 23 downloads data from the register.

[0064] Among them, when the main control chip 30 gives a start signal, the main control chip 30 controls the enable control unit ENC to start through the enable pin EN, and the enable control unit ENC can control the voltage output of the step-down signal, low-level signal and analog voltage signal according to the set timing relationship. Among them, the logic power supply of the enable control unit ENC can be directly provided by the main control chip 30 through the enable pin EN, or the enable pin EN is used to control the first input pin Vin for voltage conversion. The timing logic relationship of each output voltage component can be set by the Efuse (one-time programmable memory) hardware, or the software setting can be set by Register (cache).

[0065] For circuit modules that require internal conversion of the power chip 23, the enabling control unit ENC sets the timing relationship by turning on and off the input of each module. For example, the enabling control unit ENC controls the input voltage to be input to the buck conversion control unit BUCK, and the buck conversion control unit BUCK starts working and outputs a buck signal.

[0066] For an external input module circuit, such as an analog voltage signal, the enable control unit ENC controls the timing pin GD_O to turn on the isolated first MOS tube MOS1, and then controls the analog voltage control unit ACL to start working and output an analog voltage signal.

[0067] It should be noted that when the input voltage is provided to the power management circuit 20, the power management circuit 20 can output multiple voltage signals including AVDD (analog voltage), BUCK (step-down signal), VGH (high level signal), VGL (low level signal), etc. In order to meet the output timing of different voltage signals, the timing control unit SC can adjust the different delay durations of these voltage signals. The power management circuit 20 of the embodiment of the present application controls the opening and closing of the display module 10 through the enable pin EN, and does not affect the timing control of each output voltage signal by the timing control unit SC. The solution of setting a switching circuit at the front end of the power management circuit 20 is saved, thereby reducing the hardware cost of the display device 1.

[0068] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0070] The power management circuit and display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A power management circuit for controlling a display module, characterized in that: The power management circuit comprises: A first input terminal, capable of receiving a first driving signal; A first output terminal, capable of providing an analog voltage signal required by the display module; a switch circuit, wherein one end of the switch circuit is connected to the first input end, and a second end of the switch circuit is connected to the first output end; and A power chip, having an enable pin and a timing pin, wherein the enable pin can receive a start signal and a stop signal of the display module, and the timing pin is connected to the third end of the switch circuit; When the power chip receives the start-up signal of the display module from the enable pin, the power chip outputs a first control signal to the switch circuit through the timing pin to turn on the switch circuit and control the first output terminal to output the analog voltage signal; When the power chip receives a shutdown signal of the display module from the enable pin, the power chip outputs a second control signal to the switch circuit through the timing pin to shut down the switch circuit and disconnect the first input terminal and the first output terminal.

2. The power management circuit according to claim 1, characterized in that: The power chip comprises: A timing control unit connected to the timing pin; an enable control unit, electrically connected to the timing control unit, the enable control unit being connected to the enable pin; and A first input pin, the first input pin is connected to the enabling control unit, and the first input pin is connected to the first input end; Among them, the power chip receives the first drive signal through the first input pin. When the enable pin receives the start-up signal of the display module, the enable control unit is turned on, and the power chip outputs the first control signal after the first drive signal is converted by the timing control unit to the switching circuit.

3. The power management circuit according to claim 2, characterized in that: The power management circuit further includes: A third capacitor, one end of the third capacitor is connected to the first input pin, and the other end of the third capacitor is grounded.

4. The power management circuit according to claim 2, characterized in that: The switch circuit comprises: A first MOS transistor, wherein a gate of the first MOS transistor is connected to the timing pin, a source of the first MOS transistor is connected to the first input end, and a drain of the first MOS transistor is connected to the first output end.

5. The power management circuit according to claim 4, characterized in that: The switch circuit further comprises: A first capacitor, one end of which is connected to the source of the first MOS tube, and the other end of which is connected to the timing pin; A second capacitor, one end of the second capacitor is connected to the drain of the first MOS tube, and the other end of the second capacitor is grounded.

6. The power management circuit according to claim 4, characterized in that: The power management circuit further includes an amplifier circuit, and the amplifier circuit is arranged between the first MOS tube and the first output end; The power chip further includes an analog voltage control unit, which is connected to the amplifying circuit to convert the first driving signal into the analog voltage signal.

7. The power management circuit according to claim 6, characterized in that: The amplifying circuit comprises: an inductor, one end of which is connected to the drain of the first MOS tube; a second MOS transistor, wherein a gate of the second MOS transistor is connected to the analog voltage control unit, and a drain of the second MOS transistor is connected to the other end of the inductor; A first resistor, one end of the first resistor is connected to the source of the second MOS tube, and the other end of the first resistor is grounded.

8. The power management circuit according to claim 7, characterized in that: The power chip also includes a gate pin, a detection pin and a feedback pin, wherein the gate pin, the detection pin and the feedback pin are all connected to the analog voltage control unit, the gate pin is connected to the gate of the second MOS tube, the detection pin is connected to the source of the second MOS tube, and the feedback pin is connected to the first output end.

9. The power management circuit according to claim 6, characterized in that: The power chip further includes a buck conversion control unit, which is electrically connected to the timing control unit. The timing control unit controls the buck conversion control unit to output a buck signal after delaying for a first preset time period.

10. A display device, characterized in that: include: Display module; and A power management circuit is electrically connected to the display module, and the power management circuit is the power management circuit as described in any one of claims 1-9.

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