Chip and test method supporting out-of-order finished product testing

Abstract

The present invention relates to a chip and a testing method, in particular to a chip and a testing method that supports out-of-order finished product testing. According to the technical solution provided by the present invention, the chip that supports out-of-order finished product testing includes a chip main circuit module, and also includes at least one readable and writable circuit module, and the readable and writable circuit module is adaptively connected to the chip main circuit module; when the chip main circuit module is subjected to the required finished product test, the finished product test data for one or more finished product tests is written and locked in the readable and writable circuit module, and the finished product test data correspondingly latched in the readable and writable circuit module can be read through the output terminal OUT of the chip main circuit module, so as to use the read finished product test data and the current finished product test data when the chip main circuit module is subjected to the finished product test to perform the required test processing. The present invention can effectively support out-of-order testing, improve the efficiency of testing, reduce testing costs, and be safe and reliable.

Description

Technical Field

[0001] The present invention relates to a chip and a testing method, in particular to a chip and a testing method supporting out-of-order finished product testing. Background Art

[0002] The chip production process needs to go through multiple tests, among which the two main test nodes are wafer testing after wafer production and final testing after packaging (also known as finished product testing). In each test link, it may be necessary to conduct multiple tests under different test conditions provided by different test machines. For example, in order to reduce the waiting time required to change the test temperature, tests under different temperature conditions are usually conducted on different test machines.

[0003] Since the test conditions of all chips on a whole wafer can be changed simultaneously, and the test data of different chips can be recorded according to the coordinate positions of the chips on the wafer, it is convenient to establish connections between the test results obtained by different test machines and conduct overall data analysis. Therefore, the difficulty and cost of wafer testing are relatively low.

[0004] Finished product testing is different from wafer testing. Chips have been packaged into disordered independent individuals. If you want to establish a connection between the data obtained by different machines, you can only test and transfer the chips in a predetermined order between different test machines. This requires additional automated transfer equipment and greatly increases the test time. For characteristic parameters such as chip temperature, it is generally necessary to comprehensively calculate and compare the test data of multiple machines. The efficiency of finished product testing is extremely low and the equipment cost and time cost are extremely high.

[0005] In order to improve the efficiency of finished chip testing and reduce testing costs, it is urgent to improve the chips and testing methods to meet the needs of out-of-order testing of certain parameters. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a chip and a testing method that support out-of-order finished product testing, which can effectively support out-of-order testing, improve testing efficiency, reduce testing costs, and be safe and reliable.

[0007] According to the technical solution provided by the present invention, the chip supporting out-of-order finished product testing includes a chip main circuit module and at least one readable and writable circuit module, and the readable and writable circuit module is adaptively connected to the chip main circuit module;

[0008] When the required finished product test is performed on the chip main circuit module, the finished product test data used for one or more finished product tests is written and locked in the readable and writable circuit module, and the corresponding latched finished product test data in the readable and writable circuit module can be read through the output terminal OUT of the chip main circuit module, so as to use the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module to perform the required test processing.

[0009] The finished product test data is serially written into the readable and writable circuit module, and the finished product test data written and latched in the readable and writable circuit module is output through serial reading.

[0010] It also includes a data reading state switch S1, one end of the data reading state switch S1 is connected to the output end OUT of the chip main circuit module, the other end of the data reading state switch S1 is grounded, and the control end of the data reading state switch S1 and the enable end of the chip main circuit module are connected to the read-write circuit output end of the read-write circuit module;

[0011] When the data read state switch S1 is in the on state through the data read output signal outputted from the read / write circuit output terminal of the read / write circuit module, the chip main circuit module is simultaneously in the off-enabled state by utilizing the data read output signal.

[0012] The readable and writable circuit module includes a logic input detection unit, a shift register, a data latch array and a logic operation unit;

[0013] The input end of the logic input detection unit is connected to any input port of the chip main circuit module, the shift control output end of the logic input detection unit is connected to the clock end of the shift register, the latch control output end of the logic input detection unit is connected to the data latch control end in the data latch array, the data shift output end of the shift register is adaptively connected to the data latch chip select signal end of the data latch array and the logic operation chip select signal end of the logic operation unit, the data latch output end of the data latch array is adaptively connected to the logic operation input end of the logic operation unit, and the output end of the logic operation unit is connected to the control end of the data read state switch S1 and the enable end of the chip main circuit module;

[0014] The logic input detection unit outputs a valid shift control signal Y1 through the shift control output terminal or outputs a valid latch control signal Y2 through the latch control output terminal according to the loaded input signal IN, and drives the register chip select signal output from the data shift output terminal of the shift register to shift through the valid shift control signal Y1, and the required finished product test sub-data can be latched in the corresponding data latch unit of the data latch array by using the valid latch control signal Y2 and the corresponding register chip select signal;

[0015] When reading the finished product test data latched in the data latch array, the logic operation unit operates the corresponding finished product test sub-data in the data latch array according to the register chip selection signal output from the data shift output end of the shift register and then reads them out in series.

[0016] The logic input detection unit includes a shift control signal generating unit and a latch control signal generating unit;

[0017] When the shift control signal Y1 is high level valid, the shift control signal generating unit includes a PMOS tube PM1, an NMOS tube NM2 and an inverter INV1, the source terminal of the PMOS tube PM1 is connected to the voltage VDD, the gate terminal of the PMOS tube PM1 is connected to the bias voltage VBP1, the drain terminal of the PMOS tube PM1 is connected to the input terminal of the inverter INV1 and the drain terminal of the NMOS tube NM2, the gate terminal of the NMOS tube NM2 is connected to GND, and the output terminal of the inverter INV1 forms a shift control output terminal; the source terminal of the NMOS tube NM2 receives the input signal IN, and when the input signal IN is a pulse lower than the GND potential, the high level shift control signal Y1 is output through the shift control output terminal.

[0018] When the latch control signal Y2 is high level valid, the latch control signal generating unit includes a PMOS tube PM2, an NMOS tube NM1, an inverter INV2 and an inverter INV3, wherein the source terminal of the PMOS tube PM2 receives the input signal IN, the gate terminal of the PMOS tube PM2 is connected to the voltage VDD, the drain terminal of the PMOS tube PM2 is connected to the drain terminal of the NMOS tube NM1 and the input terminal of the inverter INV2, the gate terminal of the NMOS tube NM1 is connected to the bias voltage VBN1, the source terminal of the NMOS tube NM1 is grounded, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 forms a latch control output terminal; when the input signal IN is a pulse higher than the VDD potential, a high level latch control signal Y2 is output through the latch control output terminal.

[0019] The data latch array includes a plurality of data latch units that are independent of each other and distributed in an array, and the data latch unit includes a fuse Fuse, one end of the fuse Fuse is connected to the voltage VDD, and the other end of the fuse Fuse is connected to the NMOS tube NM3, one end of the current source Iread and the input end of the inverter INV4;

[0020] The source terminal of the NMOS tube NM3 and the ground terminal of the current source Iread are both connected to GND, the gate terminal of the NMOS tube NM3 is connected to the output terminal of the AND gate U1, and the input terminal of the AND gate U1 is connected to the latch control signal Y2 and the register chip select signal of the shift register; the data latch state output terminal of the data latch unit is formed through the output terminal of the inverter INV4.

[0021] A chip testing method supporting out-of-order finished product testing includes a chip main circuit module and at least one readable and writable circuit module, wherein the readable and writable circuit module is adaptively connected to the chip main circuit module;

[0022] When the required finished product test is performed on the chip main circuit module, the finished product test data used for one or more finished product tests is written and locked in the readable and writable circuit module, and the corresponding latched finished product test data in the readable and writable circuit module can be read through the output terminal OUT of the chip main circuit module, so as to use the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module to perform the required test processing.

[0023] It also includes a data reading state switch S1, one end of which is connected to the output end OUT of the chip main circuit module, the other end of which is grounded, and the control end of the data reading state switch S1 and the enable end of the chip main circuit module are connected to the output end Y of the readable and writable circuit module;

[0024] When the data read state switch S1 is in the on state through the data read output signal outputted by the read / write circuit output terminal Y of the read / write circuit module, the chip main circuit module is simultaneously in the off-enabled state by utilizing the data read output signal.

[0025] The readable and writable circuit module includes a logic input detection unit, a shift register, a data latch array and a logic operation unit;

[0026] The input end of the logic input detection unit is connected to any input port of the chip main circuit module, the shift control output end of the logic input detection unit is connected to the clock end of the shift register, the latch control output end of the logic input detection unit is connected to the data latch control end in the data latch array, the data shift output end of the shift register is adaptively connected to the data latch chip select signal end of the data latch array and the logic operation chip select signal end of the logic operation unit, the data latch output end of the data latch array is adaptively connected to the logic operation input end of the logic operation unit, and the output end of the logic operation unit is connected to the control end of the data read state switch S1 and the enable end of the chip main circuit module;

[0027] The logic input detection unit outputs a valid shift control signal Y1 through the shift control output terminal or outputs a valid latch control signal Y2 through the latch control output terminal according to the loaded input signal IN, and drives the register chip select signal output from the data shift output terminal of the shift register to shift through the valid shift control signal Y1, and the required finished product test sub-data can be latched in the corresponding data latch unit of the data latch array by using the valid latch control signal Y2 and the corresponding register chip select signal;

[0028] When reading the finished product test data latched in the data latch array, the logic operation unit operates the corresponding finished product test sub-data in the data latch array according to the register chip selection signal output from the data shift output end of the shift register and then reads them out in series.

[0029] The advantages of the present invention are as follows: the readable and writable circuit module is adaptively connected to the chip main circuit module, the chip main circuit module is used to realize the functions and effects of the finished chip, the readable and writable circuit module can be used to latch the finished product test data once or multiple times, and the finished product test data correspondingly latched in the readable and writable circuit module can be read through the output end OUT of the chip main circuit module, so that the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module can be used to perform the required test processing, that is, it can effectively support out-of-order testing, improve test efficiency, and reduce test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural block diagram of the present invention.

[0031] Figure 2 Flowchart for testing of existing finished products.

[0032] Figure 3 The figure is a flow chart of the finished product testing of the present invention.

[0033] Figure 4 It is a circuit schematic diagram of the logic input detection unit of the present invention.

[0034] Figure 5 It is a signal schematic diagram of the logic input detection unit of the present invention when it is working.

[0035] Figure 6 It is a circuit schematic diagram of the data latch unit of the present invention.

[0036] Explanation of the reference numerals: 1- finished chip, 2- chip main circuit module, 3- readable and writable circuit module, 4- logic input detection unit, 5- shift register, 6- data latch array, 7- logic operation unit. DETAILED DESCRIPTION

[0037] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0038] like Figure 1 As shown: In order to effectively support out-of-order testing, improve test efficiency, and reduce test costs, the finished chip 1 of the present invention includes a chip main circuit module 2 and at least one readable and writable circuit module 3, and the readable and writable circuit module 3 is adaptively connected to the chip main circuit module 2;

[0039] When the required finished product test is performed on the chip main circuit module 2, the finished product test data used for one or more finished product tests is written and locked in the readable and writable circuit module 3, and the corresponding latched finished product test data in the readable and writable circuit module 3 can be read through the output terminal OUT of the chip main circuit module 2, so as to use the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module 2 to perform the required test processing.

[0040] Specifically, the finished chip 1 includes a chip main circuit module 2 and a readable and writable circuit module 3, wherein the chip main circuit module 2 is used to realize the function of the finished chip 1, that is, the chip main circuit module 2 can adopt the form of the existing finished chip 1, and the specific form and function of the chip main circuit module 2 are consistent with the existing ones, which are well known to the personnel in this technical field and will not be repeated here. In the embodiment of the present invention, a readable and writable circuit module 3 is added to the finished chip 1. Generally, the readable and writable circuit module 3 is set to be invisible in function through the technical means commonly used in this technical field, so as not to affect the operation of the chip main circuit module 2, that is, it will not affect the function and operation of the finished chip 1.

[0041] In the embodiment of the present invention, when the finished chip 1 is subjected to a finished product test, that is, the chip main circuit module 2 is subjected to a finished product test, and the specific type and process of the finished product test can be consistent with the existing ones, which are well known to the personnel in the technical field and will not be described in detail here. After the readable and writable circuit module 3 is set, the readable and writable circuit module 3 can be adapted and connected with the chip main circuit module 2, and the readable and writable circuit module 3 has data storage capability.

[0042] From the above description, it can be seen that when testing the chip main circuit module 2, that is, when it is necessary to use a new testing machine or change the test conditions to test the finished chip 1 again, the type and process of multiple finished product tests on the chip main circuit module 2 can be selected according to actual needs, which is well known to people in this technical field and will not be repeated here.

[0043] When the chip main circuit module 2 is subjected to the required finished product test by using a test machine or other methods, the finished product test data can be stored in the readable and writable circuit module 3. The readable and writable circuit module 3 can be used to store the finished product test data of one finished product test or store multiple finished product test data during multiple finished product tests in the readable and writable circuit module 3. The finished product test data can be locked in the readable and writable circuit module 3, that is, the finished product test data written in the readable and writable circuit module 3 will not be lost in the case of after the test or other conditions. That is, when the chip main circuit module 2 is subjected to a finished product test, the finished product test data of the finished product test is written into the readable and writable circuit module 3. The amount of finished product test data stored in the readable and writable circuit module 3 is related to the storage capacity of the readable and writable circuit module 3 and the actual number of finished product tests required for the chip main circuit module 2. For example, when it is necessary to perform two finished product tests on the chip main circuit module 2, the finished product test data of the first finished product test is stored in the readable and writable circuit module 3 after the first finished product test; and when it is necessary to perform three finished product tests on the chip main circuit module 2, the corresponding finished product test data after the first finished product test and the second finished product test are both stored in the readable and writable circuit module 3. The specific situation of locking the finished product test data in the readable and writable circuit module 3 can be configured according to actual selections and will not be repeated here.

[0044] In specific implementation, the finished product test data specifically refers to the test result data after testing the finished product chip 1. For example, for the temperature coefficient test of the finished product chip 1, the first finished product test data is obtained at a low temperature, and then the data is serially written into the readable and writable circuit module 3, and then the second finished product test data is obtained at a high temperature, and then the first finished product test data in the readable and writable circuit module 3 is serially read, so that the difference in test data under the two temperature conditions can be calculated. Among them, the specific temperature values ​​of high temperature and low temperature are specifically determined by the type of finished chip 1 and the specific test requirements, which are well known to those skilled in the art and will not be repeated here.

[0045] like Figure 2 As shown, it is a flow chart of the finished product test of the existing finished product chip 1. Figure 2 In the example, the finished product chip 1 is tested twice. Specifically, after the first finished product test, the first finished product test data needs to be exported. After the second finished product test, the second finished product test data and the exported first finished product test data are used for the required operation. Therefore, according to Figure 2As can be seen from the flowchart, the test sequence must be strictly followed to ensure the test requirements of the finished chip 1, otherwise, the calculation requirements of the first finished product test data and the second finished product test data cannot be achieved. In specific implementation, the calculation processing, such as the difference in the test results of a certain electrical parameter under two test conditions, can determine that the finished chip 1 is a good chip if the difference is within a certain range, otherwise, the finished chip 1 is a defective product. The specific calculation processing method and process can be selected as needed, which is well known to those in the technical field and will not be repeated here.

[0046] In the embodiment of the present invention, the finished product test data of the first finished product test can be written into the readable and writable circuit module 3, so that after the second finished product test data, the first finished product test data correspondingly latched in the readable and writable circuit module 3 can be read through the output terminal OUT of the chip main circuit module 2. After the required finished product test data is read, the read finished product test data is compared with the current finished product test data of the current finished product test of the chip main circuit module 2 for the required test processing. The specific test processing method and process are consistent with the existing ones, which are well known to the personnel in this technical field and will not be repeated here. Figure 3 As shown, it is a flow chart of the finished product test of the present invention. Since the first finished product test data has been stored in the readable and writable circuit module 3, after the first finished product test, there is no need to store it in sequence or transfer it in time. After changing the test conditions or changing the test machine, the second finished product data obtained by the test and the first finished product data in the readable and writable circuit module 3 can be read to conveniently implement the required test operation processing, thereby effectively supporting out-of-order testing, improving test efficiency, and reducing test costs.

[0047] Furthermore, the finished product test data is serially written into the readable and writable circuit module 3, and the finished product test data written and latched in the readable and writable circuit module 3 is output by serial reading. In the embodiment of the present invention, the finished product test data is serially written into the readable and writable circuit module 3, and the finished product test data is read out by serial means, thereby improving the reliability of data access and reading, and meeting the requirements of subsequent operation processing of the finished product test data.

[0048] Furthermore, it also includes a data reading state switch S1, one end of the data reading state switch S1 is connected to the output end OUT of the chip main circuit module 2, the other end of the data reading state switch S1 is grounded, and the control end of the data reading state switch S1 and the enable end of the chip main circuit module 2 are connected to the read-write circuit output end of the read-write circuit module 3;

[0049] When the data read state switch S1 is in the on state through the data read output signal outputted from the read / write circuit output terminal of the read / write circuit module 3, the chip main circuit module 2 is simultaneously in the off-enabled state by utilizing the data read output signal.

[0050] Specifically, the data reading state switch S1 can adopt the existing commonly used controllable form, such as using MOSFET devices, etc. The specific type can be selected as needed and will not be repeated here. When the data reading state switch S1 is in the on state, a low level can be obtained through the output terminal OUT of the chip main circuit module 2, and when the data reading state switch S1 is in the off state, a certain voltage value between GND and VDD can be obtained through the output terminal OUT of the chip main circuit module 2. The specific situation of the voltage value is related to the specific finished product test data. When the data reading state switch S1 is in the on state, the data reading output signal is used to simultaneously make the chip main circuit module 2 in the off-enable state, that is, the output of the chip main circuit module 2 through the output terminal OUT is turned off to avoid affecting the correct reading of the finished product test data in the readable and writable circuit module 3. When the data reading state switch S1 is in the off state, the chip main circuit module 2 is in a normal working state, that is, it will not affect the corresponding level value read through the output terminal OUT of the chip main circuit module 2.

[0051] Furthermore, the readable and writable circuit module 3 includes a logic input detection unit 4, a shift register 5, a data latch array 6 and a logic operation unit 7;

[0052] The input end of the logic input detection unit 4 is connected to any input port of the chip main circuit module 2, the shift control output end of the logic input detection unit 4 is connected to the clock end of the shift register 5, the latch control output end of the logic input detection unit 4 is connected to the data latch control end in the data latch array 6, the data shift output end of the shift register 5 is adaptively connected to the data latch chip select signal end of the data latch array 6 and the logic operation chip select signal end of the logic operation unit 7, the data latch output end of the data latch array 6 is adaptively connected to the logic operation input end of the logic operation unit 7, and the output end of the logic operation unit 7 is connected to the control end of the data read state switch S1 and the enable end of the chip main circuit module 2;

[0053] The logic input detection unit 4 outputs a valid shift control signal Y1 through the shift control output terminal or a valid latch control signal Y2 through the latch control output terminal according to the loaded input signal IN, and drives the register chip select signal output from the data shift output terminal of the shift register 5 to shift through the valid shift control signal Y1, and the required finished product test sub-data can be latched in the corresponding data latch unit of the data latch array 6 by using the valid latch control signal Y2 and the corresponding register chip select signal;

[0054] When reading the finished product test data latched in the data latch array 6, the logic operation unit 7 operates the corresponding finished product test sub-data in the data latch array 6 according to the register chip selection signal output from the data shift output terminal of the shift register 5 and reads them out in series.

[0055] In the embodiment of the present invention, the logic input detection unit 4 receives the loaded input signal IN, and the finished product test data can be input into the readable and writable circuit module 3 through the input signal IN. Specifically, according to the specific situation of the input signal IN, the logic input detection unit 4 can output a valid shift control signal Y1 through the shift control output terminal or output a valid latch control signal Y2 through the latch control output terminal, wherein the valid shift control signal Y1 can drive the register chip select signal output from the data shift output terminal of the shift register 5 to shift, and the required finished product test sub-data can be latched in the corresponding data latch unit of the data latch array 6 by using the valid latch control signal Y2 and the corresponding register chip select signal.

[0056] The shift register 5 can adopt the existing commonly used form. The shift register 5 can realize the shift of N-bit chip select signal. The size of N can be selected according to actual needs to meet the storage of finished product test data. It will not be repeated here. In the initial state, the chip select signal CS<1:N> output by the shift register 5 defaults to all 0s; when the shift control signal Y1 is valid for the first time when the CLK input of the clock end is valid, the chip select signal CS<1:N> is 0. <1> is 1, and the rest are 0; when the clock terminal CLK is valid again after the shift control signal Y1, the chip select signal CS is stored <2> The specific form and working process of the shift register 5 are consistent with the existing ones, which are well known to the technical personnel in this field and will not be described here.

[0057] The data latch array 6 generally includes at least N data latch units, which are distributed in an array, and the N data latch units are connected to the N register chip select signals of the shift register 5 in a one-to-one correspondence. At the same time, each data latch unit also receives a latch control signal Y2. For any data latch unit, when the latch control signal Y2 is in a valid state and the received register chip select signal is also "1" at the same time, the data can be latched in the current data latch unit.

[0058] As for the logic operation unit 7, the logic operation unit 7 is connected to the N register chip select signals of the shift register 5 in a one-to-one correspondence and is correspondingly connected to the output ends of the N data latch units, and the output end of the read-write circuit is formed by the output end of the logic operation unit 7. According to the sequential shifting of the N register chip select signals, the data latch state of each data latch unit in the data latch array 6 can be read out.

[0059] like Figure 3 and Figure 4 As shown, the logic input detection unit 4 includes a shift control signal generating unit and a latch control signal generating unit;

[0060] When the shift control signal Y1 is high level valid, the shift control signal generating unit includes a PMOS tube PM1, an NMOS tube NM2 and an inverter INV1, the source terminal of the PMOS tube PM1 is connected to the voltage VDD, the gate terminal of the PMOS tube PM1 is connected to the bias voltage VBP1, the drain terminal of the PMOS tube PM1 is connected to the input terminal of the inverter INV1 and the drain terminal of the NMOS tube NM2, the gate terminal of the NMOS tube NM2 is connected to GND, and the output terminal of the inverter INV1 forms a shift control output terminal; the source terminal of the NMOS tube NM2 receives the input signal IN, and when the input signal IN is a pulse lower than the GND potential, the high level shift control signal Y1 is output through the shift control output terminal.

[0061] Further, when the latch control signal Y2 is valid at a high level, the latch control signal generating unit includes a PMOS tube PM2, an NMOS tube NM1, an inverter INV2 and an inverter INV3, wherein the source terminal of the PMOS tube PM2 receives the input signal IN, the gate terminal of the PMOS tube PM2 is connected to the voltage VDD, the drain terminal of the PMOS tube PM2 is connected to the drain terminal of the NMOS tube NM1 and the input terminal of the inverter INV2, the gate terminal of the NMOS tube NM1 is connected to the bias voltage VBN1, the source terminal of the NMOS tube NM1 is grounded, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 forms a latch control output terminal; when the input signal IN is a pulse higher than the VDD potential, a high-level latch control signal Y2 is output through the latch control output terminal.

[0062] In the embodiment of the present invention, when the potential of the input signal IN is between VDD and GND, the PMOS tube PM1 and the NMOS tube NM1 are turned on, and the shift control signal Y1 and the latch control signal Y2 are both at a low level. If the input signal IN is a pulse lower than the GND potential, the NMOS tube NM2 is turned on and the degree of conduction is stronger than that of the PMOS tube PM1, and the shift control signal Y1 is a high-level pulse, that is, the shift control signal Y1 is in an effective state at this time. If the input signal IN is a pulse higher than the VDD potential, the PMOS tube PM2 is turned on and the degree of conduction is stronger than that of the NMOS tube NM1, and the latch control signal Y2 is a high-level pulse, and the latch control signal Y2 is in an effective state at this time. The specific magnitudes of the bias voltage VBN1 and the bias voltage VBP1 can be selected as needed, which are well known to those skilled in the art and will not be described in detail here.

[0063] like Figure 6As shown, the data latch array 6 includes a plurality of data latch units that are independent of each other and distributed in an array, and the data latch unit includes a fuse Fuse, one end of the fuse Fuse is connected to the voltage VDD, and the other end of the fuse Fuse is connected to the NMOS tube NM3, one end of the current source Iread and the input end of the inverter INV4;

[0064] The source terminal of the NMOS tube NM3 and the ground terminal of the current source Iread are both connected to GND, the gate terminal of the NMOS tube NM3 is connected to the output terminal of the AND gate U1, and the input terminal of the AND gate U1 is connected to the latch control signal Y2 and the register chip select signal of the shift register 5; the data latch state output terminal of the data latch unit is formed through the output terminal of the inverter INV4.

[0065] Specifically, the data latch array 6 includes at least N data latch units. Figure 6 A specific case of a data latch unit is shown in FIG. Figure 6 In the data latch unit in the initial state, the resistance of the fuse Fuse is extremely small (on the order of tens of Ω), and the voltage drop across the fuse Fuse is very small. The voltage drop of the fuse Fuse is R fsue *Iread. At this time, the input terminal of the inverter INV4 is at a high potential, and the fuse state of the output terminal of the inverter INV4 is at a low level. The current output by the current source Iread can be selected as needed. The current source Iread can specifically adopt an existing commonly used form, which is well known to those skilled in the art and will not be described in detail here. Figure 6 In the embodiment, the CS signal received by the AND gate U1 is a register chip select signal corresponding to the shift register 5, and the WRT signal received by the AND gate U1 is a latch control signal Y2.

[0066] When the chip select signal CS output by the shift register 5 is "1" (i.e., the data latch unit is selected), and the latch control signal Y2 is in a high-level valid state, the AND gate U1 outputs a high level. Under the effect of the high level output by the AND gate U1, the NMOS tube NM1 is turned on, and a large current flows through the fuse Fuse instantly, causing the resistance characteristics of the fuse Fuse to change. The resistance value of the fuse Fuse rises to the MΩ level, and the voltage drop R across the fuse Fuse is fsue*Iread becomes larger, the input terminal of the inverter INV4 is at a low potential, and the output fuse state is at a high level. The data latch unit realizes 1-bit data storage, so the data latch array 6 composed of N data latch units can realize the storage of N-bit data. In specific implementation, generally one data latch array 6 is used to realize the latching of finished product test data once. When it is necessary to latch the finished product test data multiple times, multiple data latch arrays 6 can be set. The method of using multiple data latch arrays 6 to realize multiple finished product test data latching is well known to those skilled in the art and will not be repeated here.

[0067] During specific implementation, according to the specific situation of the finished product test data, the specific level change of the corresponding input signal IN can be determined, that is, for a certain finished product test data, the input signal IN corresponding to the finished product test data can be determined, and N bits of finished product test data are obtained in the data latch array 6 according to the determined input signal. The specific correspondence between the finished product test data and the input signal IN is well known to personnel in this technical field, and it is based on the ability to completely write the finished product test data into the data latch array 6, which will not be repeated here.

[0068] In specific implementation, as the input signal IN is continuously loaded, the required effective shift control signal Y1 and latch control signal Y2 can be obtained, so that different data latch units are selected respectively under the action of the shift register 5, so that the finished product test sub-data can be latched in the corresponding data latch unit of the data latch array 6. The required finished product test data can be formed by the N-bit finished product test sub-data. Of course, the data latch unit can also have other latching forms, which can be selected according to actual needs, and will not be repeated here.

[0069] During specific operation, after writing the finished product test data into the data latch array 6 in the above manner, the entire finished product chip 1 is transferred to a new test machine or the new test conditions are changed, the finished product chip 1 is powered on again as a whole, and all the register chip select signals of the shift register 5 are reset to zero. The data stored in the data latch array 6 will not be lost, that is, the data latch unit that has been written has a data storage signal Q of 1 through the output end of the inverter INV4 therein, and the data latch unit that has not been written has a data storage signal Q of 0 through the output end of the inverter INV4 therein.

[0070] The logic input detection unit 4 is re-triggered to output a valid shift control signal Y1 to drive the register chip select signal of the shift register 5 to shift in sequence. The logic operation unit 7 performs bitwise operation according to the N register chip select signals CS<1:N> and the data storage signals Q<1:N> respectively output by the N data latch units to obtain a logic operation output value Y. Specifically, the logic operation output value Y is:

[0071] Y=CS<1>·Q<1>+CS<2>·Q<2>+…+CS <n> ·Q <n>

[0072] In the above logic operation output value Y, CS <1> is the chip select signal value of the first bit of shift register 5, Q <1> It is the data storage signal Q value corresponding to the first bit of the data latch unit in the data latch array 6. The rest of the cases are analogous and will not be listed here for further explanation.

[0073] According to the expression of the above logic operation output value Y, it can be known that the logic operation output value Y is a high potential 1 only when and only when the data latch unit selected by the chip has been programmed. When the logic operation output value Y is a high potential "1", the enable end of the chip main circuit module 2 enters a closed state under the drive of the logic operation output value Y, the data reading state switch S1 is turned on, and the output end OUT of the chip main circuit module 2 obtains a 0 potential. If the data latch unit selected by the registered chip select signal has not been programmed, the logic operation output value Y is a low level 0, and the output end OUT of the chip main circuit module 2 is controlled by the chip main circuit module 2, that is, a certain voltage value between GND and VDD.

[0074] As the N register chip select signals of the shift register 5 are continuously shifted, the finished product test sub-data latched in all the data latch units in the data latch array 6 can be output, that is, the serial reading of the finished product test data stored in the data latch array 6 can be realized.

[0075] In summary, the chip testing method supporting out-of-order finished product testing of the present invention includes a chip main circuit module 2 and at least one readable and writable circuit module 3, wherein the readable and writable circuit module 3 is adaptively connected to the chip main circuit module 2;

[0076] When the required finished product test is performed on the chip main circuit module 2, the finished product test data used for one or more finished product tests is written and locked in the readable and writable circuit module 3, and the corresponding latched finished product test data in the readable and writable circuit module 3 can be read through the output terminal OUT of the chip main circuit module 2, so as to use the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module 2 to perform the required test processing.

[0077] In the specific implementation, the coordination between the chip main circuit module 2 and the readable and writable circuit module 3, as well as the testing method of using the readable and writable circuit module 3 to implement out-of-order finished product testing of the chip main circuit module 2 are all referred to the above description and will not be repeated here.< / n> < / n>

Claims

1. A chip supporting out-of-order finished product testing, comprising a chip main circuit module (2), characterized in that: It also comprises at least one readable and writable circuit module (3), wherein the readable and writable circuit module (3) is adaptively connected to the chip main circuit module (2); When the chip main circuit module (2) is subjected to the required finished product test, finished product test data for one or more finished product tests are written into and locked in the readable and writable circuit module (3), and the corresponding finished product test data latched in the readable and writable circuit module (3) can be read through the output terminal OUT of the chip main circuit module (2), so that the required test processing can be performed using the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module (2).

2. The chip supporting out-of-order finished product testing according to claim 1, characterized in that: The finished product test data is serially written into the readable and writable circuit module (3), and the finished product test data written and latched in the readable and writable circuit module (3) is output through serial reading.

3. The chip supporting out-of-order finished product testing according to claim 1 or 2, characterized in that: It also includes a data reading state switch S1, one end of the data reading state switch S1 is connected to the output end OUT of the chip main circuit module (2), the other end of the data reading state switch S1 is grounded, and the control end of the data reading state switch S1 and the enable end of the chip main circuit module (2) are connected to the read / write circuit output end of the read / write circuit module (3); When the data reading state switch S1 is in the on state by the data reading output signal outputted from the read / write circuit output end of the read / write circuit module (3), the chip main circuit module (2) is simultaneously in the off-enabled state by utilizing the data reading output signal.

4. The chip supporting out-of-order finished product testing according to claim 3, characterized in that: The readable and writable circuit module (3) comprises a logic input detection unit (4), a shift register (5), a data latch array (6) and a logic operation unit (7); The input end of the logic input detection unit (4) is connected to any input port of the chip main circuit module (2), the shift control output end of the logic input detection unit (4) is connected to the clock end of the shift register (5), the latch control output end of the logic input detection unit (4) is connected to the data latch control end in the data latch array (6), the data shift output end of the shift register (5) is adaptively connected to the data latch chip select signal end of the data latch array (6) and the logic operation chip select signal end of the logic operation unit (7), the data latch output end of the data latch array (6) is adaptively connected to the logic operation input end of the logic operation unit (7), and the output end of the logic operation unit (7) is connected to the control end of the data read state switch S1 and the enable end of the chip main circuit module (2); The logic input detection unit (4) outputs a valid shift control signal Y1 through a shift control output terminal or a valid latch control signal Y2 through a latch control output terminal according to the loaded input signal IN, and drives the shift register (5) to shift the register chip select signal output from the data shift output terminal through the valid shift control signal Y1, and the required finished product test sub-data can be latched in the corresponding data latch unit of the data latch array (6) by using the valid latch control signal Y2 and the corresponding register chip select signal; When reading the finished product test data latched in the data latch array (6), the logic operation unit (7) operates the corresponding finished product test sub-data in the data latch array (6) according to the register chip selection signal output from the data shift output end of the shift register (5) and reads them out in series.

5. The chip supporting out-of-order finished product testing according to claim 4, characterized in that: The logic input detection unit (4) comprises a shift control signal generating unit and a latch control signal generating unit; When the shift control signal Y1 is high level valid, the shift control signal generating unit includes a PMOS tube PM1, an NMOS tube NM2 and an inverter INV1, the source terminal of the PMOS tube PM1 is connected to the voltage VDD, the gate terminal of the PMOS tube PM1 is connected to the bias voltage VBP1, the drain terminal of the PMOS tube PM1 is connected to the input terminal of the inverter INV1 and the drain terminal of the NMOS tube NM2, the gate terminal of the NMOS tube NM2 is connected to GND, and the output terminal of the inverter INV1 forms a shift control output terminal; the source terminal of the NMOS tube NM2 receives the input signal IN, and when the input signal IN is a pulse lower than the GND potential, the high level shift control signal Y1 is output through the shift control output terminal.

6. The chip supporting out-of-order finished product testing according to claim 5, characterized in that: When the latch control signal Y2 is high level valid, the latch control signal generating unit includes a PMOS tube PM2, an NMOS tube NM1, an inverter INV2 and an inverter INV3, wherein the source terminal of the PMOS tube PM2 receives the input signal IN, the gate terminal of the PMOS tube PM2 is connected to the voltage VDD, the drain terminal of the PMOS tube PM2 is connected to the drain terminal of the NMOS tube NM1 and the input terminal of the inverter INV2, the gate terminal of the NMOS tube NM1 is connected to the bias voltage VBN1, the source terminal of the NMOS tube NM1 is grounded, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 forms a latch control output terminal; when the input signal IN is a pulse higher than the VDD potential, a high level latch control signal Y2 is output through the latch control output terminal.

7. The chip supporting out-of-order finished product testing according to claim 4, characterized in that: The data latch array (6) comprises a plurality of data latch units which are independent of each other and arranged in an array, wherein the data latch unit comprises a fuse Fuse, one end of the fuse Fuse is connected to the voltage VDD, and the other end of the fuse Fuse is connected to the drain end of the NMOS tube NM3, one end of the current source Iread and the input end of the inverter INV4; The source terminal of the NMOS tube NM3 and the ground terminal of the current source Iread are both connected to GND, the gate terminal of the NMOS tube NM3 is connected to the output terminal of the AND gate U1, and the input terminal of the AND gate U1 is connected to the latch control signal Y2 and the register chip select signal of the shift register (5); the data latch state output terminal of the data latch unit is formed through the output terminal of the inverter INV4.

8. A chip testing method supporting out-of-order finished product testing, comprising a chip main circuit module (2), characterized in that: It also comprises at least one readable and writable circuit module (3), wherein the readable and writable circuit module (3) is adaptively connected to the chip main circuit module (2); When the chip main circuit module (2) is subjected to the required finished product test, finished product test data for one or more finished product tests are written into and locked in the readable and writable circuit module (3), and the corresponding finished product test data latched in the readable and writable circuit module (3) can be read through the output terminal OUT of the chip main circuit module (2), so that the required test processing can be performed using the read finished product test data and the current finished product test data during the finished product test of the chip main circuit module (2).

9. The chip testing method supporting out-of-order finished product testing according to claim 8, characterized in that: It also includes a data reading state switch S1, one end of the data reading state switch S1 is connected to the output end OUT of the chip main circuit module (2), the other end of the data reading state switch S1 is grounded, and the control end of the data reading state switch S1 and the enable end of the chip main circuit module (2) are connected to the read / write circuit output end of the read / write circuit module (3); When the data reading state switch S1 is in the on state by the data reading output signal outputted from the read / write circuit output end of the read / write circuit module (3), the chip main circuit module (2) is simultaneously in the off-enabled state by utilizing the data reading output signal.

10. The chip testing method supporting out-of-order finished product testing according to claim 8 or 9, characterized in that: The readable and writable circuit module (3) comprises a logic input detection unit (4), a shift register (5), a data latch array (6) and a logic operation unit (7); The input end of the logic input detection unit (4) is connected to any input port of the chip main circuit module (2), the shift control output end of the logic input detection unit (4) is connected to the clock end of the shift register (5), the latch control output end of the logic input detection unit (4) is connected to the data latch control end in the data latch array (6), the data shift output end of the shift register (5) is adaptively connected to the data latch chip select signal end of the data latch array (6) and the logic operation chip select signal end of the logic operation unit (7), the data latch output end of the data latch array (6) is adaptively connected to the logic operation input end of the logic operation unit (7), and the output end of the logic operation unit (7) is connected to the control end of the data read state switch S1 and the enable end of the chip main circuit module (2); The logic input detection unit (4) outputs a valid shift control signal Y1 through a shift control output terminal or a valid latch control signal Y2 through a latch control output terminal according to the loaded input signal IN, and drives the shift register (5) to shift the register chip select signal output from the data shift output terminal through the valid shift control signal Y1, and the required finished product test sub-data can be latched in the corresponding data latch unit of the data latch array (6) by using the valid latch control signal Y2 and the corresponding register chip select signal; When reading the finished product test data latched in the data latch array (6), the logic operation unit (7) operates the corresponding finished product test sub-data in the data latch array (6) according to the register chip selection signal output from the data shift output end of the shift register (5) and reads them out in series.

Images