Semiconductor device alignment method and alignment system

Abstract

An embodiment of the present invention provides an alignment method of a semiconductor device and an alignment system thereof, the alignment method comprising: providing a first semiconductor device having an element to be aligned on a first surface, and a second semiconductor device; the first semiconductor device is disposed on a surface of a substrate with the first surface facing the substrate; a plurality of marks are formed on the surface of the substrate, the plurality of marks forming a coordinate system; obtaining a first coordinate set of the element to be aligned in the coordinate system; determining a second coordinate set based on the first coordinate set and the size of the second semiconductor device; and placing the second semiconductor device at a position corresponding to the second coordinate set, so that the element to be aligned is aligned with the second semiconductor device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an alignment method and an alignment system of a semiconductor device. Background Art

[0002] In recent years, the trend of high-speed and miniaturized development of semiconductor devices (such as optical devices) has made the packaging of semiconductor devices more and more dense. Based on this, in the process of manufacturing semiconductor devices, the requirements for the packaging process of semiconductor devices are also getting higher and higher. In practical applications, semiconductor device packaging is usually achieved by wire bonding front packaging or flip chip mounting; however, in the flip chip mounting process, in the process of coupling the semiconductor device with other devices using conventional coupling methods, blind adjustment is usually used to achieve coupling alignment between the semiconductor device and other devices, and its coupling alignment is difficult and the coupling efficiency is low.

[0003] Therefore, it is urgent to provide a new alignment method to reduce coupling loss and improve the reliability of semiconductor devices. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides an alignment method and an alignment system for a semiconductor device to solve at least one of the above problems.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] In a first aspect, an embodiment of the present invention provides an alignment method for a semiconductor device, comprising:

[0007] A first semiconductor device having a to-be-aligned element on a first surface and a second semiconductor device are provided; the first semiconductor device is disposed on a surface of a substrate with the first surface facing the substrate;

[0008] forming a plurality of marks on the surface of the substrate, the plurality of marks forming a coordinate system;

[0009] Acquire a first coordinate set of the element to be aligned in the coordinate system;

[0010] determining a second coordinate set based on the first coordinate set and a size of the second semiconductor device;

[0011] The second semiconductor device is placed at a position corresponding to the second coordinate set, so that the component to be aligned is aligned with the second semiconductor device.

[0012] In the above scheme, a plurality of marks are formed on the substrate, including:

[0013] A plurality of marks are formed on the surface of the substrate through a three-dimensional (3D) printing process.

[0014] In the above solution, obtaining a first coordinate set of the component to be aligned in the coordinate system includes:

[0015] Acquiring a position of the component to be aligned in the first semiconductor device;

[0016] Acquire a third coordinate set of the first semiconductor device in the coordinate system;

[0017] The first coordinate set is determined according to the position of the element to be aligned in the first semiconductor device and the third coordinate set.

[0018] In the above scheme, the method further includes:

[0019] Before placing the second semiconductor device at a position corresponding to the second coordinate set, a side and surface parallelism calibration is performed on the first semiconductor device and the second semiconductor device.

[0020] In the above scheme, the first semiconductor device includes an optical chip, the element to be aligned includes an optical fiber interface, and the second semiconductor device includes an optical device to be coupled; the surface of the substrate includes a first area and a second area arranged in parallel, and the thickness of the substrate in the first area is greater than the thickness of the substrate in the second area; the first semiconductor device is arranged on the first area, and the second semiconductor device is arranged on the second area.

[0021] In the above scheme, the shapes of the first semiconductor device and the second semiconductor device both include a cube, the first semiconductor device has a first side surface and a second side surface that are perpendicular to each other, the first side surface and the second side surface are both perpendicular to the first surface, and the extension direction of the element to be aligned is parallel to the first side surface; the second semiconductor device has a second surface and a third side surface and a fourth side surface that are perpendicular to each other, the second semiconductor device is arranged on the surface of the substrate in a manner that the second surface faces the substrate, and the third side surface and the fourth side surface are both perpendicular to the second surface;

[0022] The method further comprises:

[0023] before placing the second semiconductor device at a location corresponding to the second set of coordinates, placing the second semiconductor device over a second region of the substrate;

[0024] Based on the first semiconductor device, the relative position relationship between the first semiconductor device and the second semiconductor device is adjusted so that the first side surface is parallel to the third side surface, the second side surface is parallel to the fourth side surface, and the first surface is parallel to the second surface.

[0025] In the above solution, placing the second semiconductor device at a position corresponding to the second coordinate set includes:

[0026] placing the second semiconductor device at an intermediate position; a projection of the second semiconductor device on the second area when the second semiconductor device is placed at the intermediate position overlaps with a projection of the second semiconductor device on the second area when the second semiconductor device is placed at a position corresponding to the second coordinate set;

[0027] moving the second semiconductor device toward the second region until the second semiconductor device contacts the second region;

[0028] Move the second semiconductor device in a direction away from the second region so that the distance between the third surface of the second semiconductor device and the second region is a first distance; the third surface and the second surface are opposite surfaces of each other; the first distance is the difference between the second distance and the thickness of the second semiconductor device; the second distance is the distance between the second region and the first surface.

[0029] In the above scheme, the method further includes:

[0030] Disposing a plurality of bumps in a first region of the substrate;

[0031] The first surface of the first semiconductor device is fixed on the plurality of bumps by a flip-chip bonding process.

[0032] On the other hand, an embodiment of the present invention further provides an alignment system for a semiconductor device, comprising: a carrier, a 3D printing device, a processor, and a translation stage; wherein:

[0033] The carrier is used to place a substrate; a first semiconductor device is arranged on the surface of the substrate with the first surface facing the substrate, and a component to be aligned is arranged on the first surface of the first semiconductor device;

[0034] The 3D printing device is used to form a plurality of marks on the surface of the substrate; the plurality of marks form a coordinate system;

[0035] The processor is used to obtain a first coordinate set of the component to be aligned in the coordinate system; and determine a second coordinate set based on the first coordinate set and the size of the second semiconductor device;

[0036] The translation stage is coupled to the processor, and is used for placing the second semiconductor device at a position corresponding to the second coordinate set under the control of the processor, so as to align the component to be aligned with the second semiconductor device.

[0037] In the above solution, the alignment system further comprises a measuring device; the measuring device is used to obtain images of the substrate, the first semiconductor device and the plurality of marks, and send the images to the processor;

[0038] The processor is specifically configured to determine, according to the image, a first coordinate set of the element to be aligned in the coordinate system.

[0039] An embodiment of the present invention provides an alignment method of a semiconductor device and an alignment system thereof, wherein the alignment method of the semiconductor device includes: providing a first semiconductor device having an element to be aligned on a first surface, and a second semiconductor device; the first semiconductor device is disposed on a surface of a substrate with the first surface facing the substrate; a plurality of marks are formed on the surface of the substrate, and the plurality of marks form a coordinate system; a first coordinate set of the element to be aligned in the coordinate system is acquired; a second coordinate set is determined based on the first coordinate set and the size of the second semiconductor device; and the second semiconductor device is placed at a position corresponding to the second coordinate set, so that the element to be aligned is aligned with the second semiconductor device. In an embodiment of the present invention, a plurality of marks are provided on a substrate, and a coordinate system is formed according to the plurality of marks. After determining a first coordinate set of a to-be-aligned element in the first semiconductor device in the coordinate system, a second coordinate set of the second semiconductor device in the coordinate system is obtained by calculation in combination with the size of the second semiconductor device. Then, the second semiconductor device is placed at a position indicated by the second coordinate set to achieve precise alignment of the to-be-aligned element in the first semiconductor device and the second semiconductor device. In other words, in an embodiment of the present invention, a coordinate system is established to quantify the size and position of the to-be-aligned element and the second semiconductor device. In the process of aligning the to-be-aligned element with the second semiconductor device, the alignment accuracy is improved, thereby reducing the coupling loss between the to-be-aligned element and the second semiconductor device, and improving the reliability of coupling or alignment of multiple semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a flow chart of a semiconductor device alignment method provided by an embodiment of the present invention;

[0041] Figure 2a to Figure 2h A schematic diagram of an alignment process of a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 3a An alignment system for a semiconductor device according to an embodiment of the present invention;

[0043] Figure 3b A structural schematic diagram of placing a component to be aligned behind an alignment system of a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in combination with the embodiments of the present invention and the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0047] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] In order to fully understand the present invention, detailed steps and detailed structures will be proposed in the following description to illustrate the technical solution of the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0050] In recent years, the high-speed and miniaturized development trend of semiconductor devices (such as optical devices) has made the packaging of semiconductor devices increasingly dense. Based on this, in the process of manufacturing semiconductor devices, the requirements for the packaging process of semiconductor devices are becoming increasingly higher.

[0051] For example, since the traditional wire bonding packaging method easily causes discontinuity in the impedance of semiconductor devices, and the traditional packaging method can only achieve 2.5-dimensional (2.5D) packaging, it will limit the bandwidth and integration of semiconductor devices. Based on this, the related art adopts the flip chip packaging method to improve the integration of semiconductor devices; and the flip chip process is a three-dimensional (3D) packaging form, and the bump connection method it adopts is easier to simulate than the traditional wire bonding method, that is, it is easier to improve the accuracy of adjusting parameters, thereby improving the impedance matching of semiconductor devices, reducing losses, and increasing bandwidth.

[0052] In the related technology, silicon-based chips are widely used due to their high integration and good radio frequency characteristics. In addition to the requirements for their electrical interconnection characteristics, silicon-based chips also have strict requirements on the quality of their optical interconnection. However, since the optical fiber interface of the silicon-based chip, referred to as the optical port, is located on the patterned waveguide surface, after the flip-chip is performed, the patterned waveguide surface faces down and the substrate faces up, which makes it impossible to see the obscured waveguide surface using a conventional coupling platform, and it is also impossible to obtain the position of the optical port on the waveguide surface. In this case, the alignment and coupling of the optical port with other optical devices can only be achieved through blind adjustment. In this way, the coupling quality and coupling efficiency of the silicon-based chip with other optical devices cannot be guaranteed.

[0053] Based on this, an embodiment of the present invention provides an alignment method for a semiconductor device. Figure 1 A schematic diagram of a semiconductor device alignment method provided by an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0054] Step 101: providing a first semiconductor device having a component to be aligned on a first surface and a second semiconductor device; the first semiconductor device is disposed on a surface of a substrate with the first surface facing the substrate;

[0055] Step 102: forming a plurality of marks on the surface of the substrate, wherein the plurality of marks form a coordinate system;

[0056] Step 103: Acquire a first coordinate set of the component to be aligned in the coordinate system;

[0057] Step 104: Determine a second coordinate set based on the first coordinate set and the size of the second semiconductor device;

[0058] Step 105: placing the second semiconductor device at a position corresponding to the second coordinate set, so that the component to be aligned is aligned with the second semiconductor device.

[0059] Figure 2a to Figure 2h A schematic diagram of an alignment process of a semiconductor device provided by an embodiment of the present invention. It should be understood that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in order according to actual needs. Figure 1 , Figure 2a to Figure 2h , the alignment method of the semiconductor device provided by the embodiment of the present invention is described in detail.

[0060] In step 101 , a first semiconductor device 20 , a second semiconductor device 30 , and a substrate 40 are provided.

[0061] In practical applications, a to-be-aligned element 201 is disposed in the first semiconductor device, and the to-be-aligned element 201 is located on a first surface 202 of the first semiconductor device.

[0062] In some embodiments, the first semiconductor device includes but is not limited to an optical chip, and the component to be aligned includes but is not limited to a fiber optic interface.

[0063] Here, if Figure 2a As shown, the optical fiber interface is located on the first surface.

[0064] It should be noted that Figure 2a A top view of a first surface 202 of a first semiconductor device (optical chip) is shown.

[0065] Exemplarily, the first semiconductor device is a silicon-based chip.

[0066] The first surface is a side of the silicon-based chip with a waveguide pattern, namely, a waveguide surface; it can be understood that, in the silicon-based chip, the side with the waveguide pattern and the exposed substrate surface are opposite to each other.

[0067] In some embodiments, the shape of the first semiconductor device includes but is not limited to a cube, the first semiconductor device has a first side surface and a second side surface that are perpendicular to each other, the first side surface and the second side surface are both perpendicular to the first surface, and the extension direction of the element to be aligned is parallel to the first side surface.

[0068] In practical applications, such as Figure 2b As shown, the first semiconductor device includes a first side surface 203 and a second side surface 204, the first side surface 203 and the second side surface 204 are parallel, and the first side surface 203 and the second side surface 204 are both perpendicular to the first surface 202. Here, the element to be aligned 201 can be a long linear structure; its linear extension direction is parallel to the first side surface 203 or the second side surface 204.

[0069] Here, the side surfaces of the first semiconductor device 20 include the aforementioned first side surface 203 and the second side surface 204; and also include a fifth side surface and a sixth side surface ( Figure 2b Here, the fifth side surface is parallel to the sixth side surface. The first semiconductor device 20 further includes a substrate surface which is opposite to the first surface 202 .

[0070] In an embodiment of the present invention, the method further includes: measuring the dimensions of the first semiconductor device 20 and the element to be aligned 201 by a measuring device to obtain the specific dimensions of the first semiconductor device and the relative position relationship between the first surface 202 of the first semiconductor device and the element to be aligned 201.

[0071] In some embodiments, the second semiconductor device 30 includes an optical device to be coupled. In practical applications, the optical device to be coupled may include but is not limited to an optical waveguide.

[0072] In some embodiments, the shape of the second semiconductor device includes but is not limited to a cube. The second semiconductor device has a second surface and a third side surface and a fourth side surface that are perpendicular to each other. The second semiconductor device is arranged on the substrate surface with the second surface facing the substrate, and the third side surface and the fourth side surface are perpendicular to the second surface.

[0073] In practical applications, such as Figure 2c As shown, the second semiconductor device 30 includes a second surface 301, a third surface 302, a third side surface 303 and a fourth side surface 304; wherein the second surface 301 and the third surface 302 are parallel to each other and opposite to each other; illustratively, the second surface 301 can be a substrate surface; the third surface 302 can be a surface with a waveguide pattern. Here, the third side surface 303 and the fourth side surface 304 are parallel to each other, and the third side surface 303 or the fourth side surface 304 is perpendicular to the second surface 301.

[0074] It should be noted that the cube may include a rectangular parallelepiped, a cube, etc. In the embodiment of the present invention, the first semiconductor device and the second semiconductor device are both rectangular parallelepipeds as an example for illustration; however, it should be noted that the embodiment in which the first semiconductor device and the second semiconductor device are both rectangular parallelepipeds is only used to illustrate the present invention and is not used to limit the scope of the present invention.

[0075] Here, the side surfaces of the second semiconductor device 30 include the aforementioned third side surface 303 and fourth side surface 304; and also include a seventh side surface and an eighth side surface ( Figure 2c Here, the seventh side surface is parallel to the eighth side surface.

[0076] In some specific embodiments, Figure 2d As shown, a substrate 40 is provided; the substrate 40 may include a silicon substrate, but is not limited thereto.

[0077] In practical applications, the substrate surface includes a first area 401 and a second area 402 arranged in parallel, and the thickness of the substrate 40 corresponding to the first area 401 is greater than the thickness of the substrate 40 corresponding to the second area 402 .

[0078] refer to Figure 2d , Figure 2e, the thickness H1 of the substrate 40 corresponding to the first region 401 is greater than the thickness H2 of the substrate 40 corresponding to the second region 402. In other words, there is a height difference △H between the first region 401 and the second region 402 in the first direction; wherein △H=H1-H2; Here, the first direction is parallel to the thickness direction of the substrate. For example, the first direction is as follows Figure 2d The Z-axis direction is shown in FIG.

[0079] However, it should be noted that in actual applications, the thickness of the substrate corresponding to the first area can be the same as the thickness of the substrate corresponding to the second area, that is, the first area and the second area can be on the same plane; or the thickness of the substrate corresponding to the first area can be less than the thickness of the substrate corresponding to the second area. The actual thickness can be set according to actual needs; here, the thickness of the substrate corresponding to the first area is taken as an example to illustrate the concept of the present invention, and it is not used to limit the scope of the present invention.

[0080] In some embodiments, the area of ​​the first region 401 is greater than the area of ​​the first surface 202 of the first semiconductor device; and the area of ​​the second region 402 is greater than the area of ​​the second surface 301 of the second semiconductor device.

[0081] In some embodiments, Figure 2d , Figure 2e As shown, the method also includes:

[0082] A plurality of bumps 403 are provided in the first region 401 of the substrate 40;

[0083] The first surface 202 of the first semiconductor device is fixed on the plurality of bumps by a flip-chip bonding process.

[0084] Specifically, a plurality of bumps 403 are disposed on the first region 401 of the substrate, and the first surface 202 of the first semiconductor device is connected to the plurality of bumps 403 to fix the first semiconductor device on the first region 401 of the substrate.

[0085] It should be noted that, here, the first surface 202 of the first semiconductor device is disposed on the first region 401 of the substrate in a manner of facing the substrate 40 .

[0086] In practical applications, the heights of the plurality of bumps 403 are approximately the same, and the height may range from 20um to 30um. In other words, the distance between the first surface 202 of the first semiconductor device and the first region 401 of the substrate is 20um to 30um.

[0087] It should be noted that Figure 2d is a three-dimensional schematic diagram of a substrate 40 and a first semiconductor device 20; Figure 2e It is a schematic side view of the substrate 40 and the first semiconductor device 20 .

[0088] It should be noted that the flip-chip packaging method is relatively mature in practical applications and will not be elaborated here.

[0089] In the embodiment of the present invention, in order to improve the alignment effect of the element to be aligned and the transmission effect of the signal in the subsequent application, the first semiconductor device is arranged at the edge of the first area. Specifically, one end of the element to be aligned is located at the edge of the first area of ​​the substrate; that is, one end of the element to be aligned is substantially flush with the side surface of the first area of ​​the substrate near the second area. Figure 2d .

[0090] In step 102, if Figure 2d As shown, a plurality of marks 50 are formed on the substrate 40 , and a coordinate system (X, Y, Z) is established based on the plurality of marks 50 .

[0091] In some embodiments, forming a plurality of marks 50 on the substrate comprises:

[0092] A plurality of marks are formed on the surface of the substrate through a three-dimensional 3D printing process.

[0093] In practical applications, a 3D printing process is used to form a mark on the surface of a substrate. Compared with the common printing technology in the related art, 3D printing has higher precision and the error between the position of the mark formed and the preset position is small. Therefore, the coordinate system established based on the mark formed by the 3D printing process has higher precision.

[0094] Specifically, the plurality of marks 50 are disposed on a first region 401 of the substrate.

[0095] It should be noted that, here, the first semiconductor device 20 and the multiple marks 50 are both arranged on the first area 401 of the substrate, but the first semiconductor device 20 and the multiple marks 50 do not affect each other; the specific positions of the two can be set according to actual needs.

[0096] In practical applications, the multiple markers 50 may be dispersed or arranged in an array. The multiple markers 50 may include at least three markers; at least one plane may be formed based on the at least three markers; and a coordinate system may be established based on the plane.

[0097] Here, the coordinate system can be understood as a two-dimensional plane coordinate system (X, Y), or a three-dimensional coordinate system (X, Y, 0) in which the value of the first direction (such as the Z axis) is 0. In the embodiment of the present invention, a three-dimensional coordinate system (X, Y, 0) in which the value of the Z axis is 0 is taken as an example for description.

[0098] It should be noted that, in the process of forming the above-mentioned coordinate system, any one of the multiple marks can be set as the origin, and the specific situation can be selected according to the position of the mark point or actual needs.

[0099] Exemplary, reference Figure 2d , three marks 50 are formed on the first area of ​​the substrate, such as mark one 501, mark two 502, and mark three 503; here, mark one 501 is taken as the origin O of the coordinate system, the direction of the line between mark one 501 and mark two 502 is the second direction; the direction of the line between mark one 501 and mark three 503 is the third direction; here, the plane formed by the second direction and the third direction is parallel to or overlaps with the plane where the first area of ​​the substrate is located.

[0100] In actual applications, the second direction may be the X-axis direction or the Y-axis direction; the third direction may be the Y-axis direction or the X-axis direction; but the second direction is different from the third direction; therefore, when the second direction is the X-axis direction, the third direction is the Y-axis direction; when the second direction is the Y-axis direction, the third direction is the X-axis direction; for ease of understanding, in an embodiment of the present invention, the second direction is the X-axis direction and the third direction is the Y-axis direction as an example for explanation; here, the first direction is the Z-axis direction, and the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0101] It should be noted that the mark formed in the embodiment of the present invention may be a groove or a convex point of various shapes, and the shape or size of the mark may also be set according to actual needs.

[0102] In step 103, a first coordinate set of the component to be aligned in the coordinate system is obtained.

[0103] In practical applications, the first coordinate set includes at least one coordinate value. In other words, the first coordinate set may include one coordinate value of the element to be aligned, or may include multiple coordinate values ​​of the element to be aligned.

[0104] Here, the one coordinate value includes but is not limited to the coordinate value at the geometric center position of the element to be aligned; the multiple coordinate values ​​include but are not limited to the coordinate values ​​of any point at different positions of the element to be aligned.

[0105] In some embodiments, obtaining a first coordinate set of the element to be aligned in the coordinate system includes:

[0106] Acquiring a position of the component to be aligned in the first semiconductor device;

[0107] Acquire a third coordinate set of the first semiconductor device in the coordinate system;

[0108] The first coordinate set is determined according to the position of the element to be aligned in the first semiconductor device and the third coordinate set.

[0109] In practical applications, multiple dimensions of the first semiconductor device 20 and the element to be aligned 201 can be obtained by a measuring device, wherein the multiple dimensions include but are not limited to the length, width, height, etc. of the first semiconductor device 20, and the distance from the element to be aligned 201 to the first side 203 and the second side 204 of the first semiconductor device.

[0110] Next, the specific position of the component to be aligned 201 on the first surface 202 of the first semiconductor device is obtained through calculation and analysis; in other words, the relative position relationship between the component to be aligned 201 and the first semiconductor device 20 can be obtained through calculation and analysis.

[0111] Next, after the size of the first semiconductor device 20 is obtained, a third coordinate set of the first semiconductor device 20 can be obtained according to the specific value of the size in combination with the coordinate system (X, Y, Z).

[0112] Here, the third coordinate set may include multiple coordinate values ​​of the first semiconductor device in the coordinate system; in other words, the coordinate values ​​obtained at different positions of the first semiconductor device in the coordinate system and at any point of the first semiconductor device all belong to the third coordinate set.

[0113] For example, Figure 2f As shown, in the coordinate system (X, Y, Z), according to the length, width, and height of the first semiconductor device, the coordinate values ​​of multiple vertices of the first semiconductor device can be determined, such as the first vertex A (X1, Y1, Z1), the second vertex B (X1, Y2, Z1), the third vertex C (X2, Y1, Z1), the fourth vertex D (X2, Y2, Z1), the fifth vertex E (X1, Y1, Z2), the sixth vertex F (X1, Y2, Z2), the seventh vertex G (X2, Y1, Z2), and the eighth vertex H (X2, Y2, Z2). Here, Figure 2f for Figure 2e An enlarged schematic diagram of a first semiconductor device;

[0114] Here, the absolute value of the difference between X1 and X2 can be understood as the length of the first semiconductor device in the X-axis direction; the absolute value of the difference between Y1 and Y2 can be understood as the width of the first semiconductor device in the Y-axis direction; the absolute value of the difference between Z1 and Z2 can be understood as the height of the first semiconductor device in the Z-axis direction.

[0115] It should be noted that, here, since the first semiconductor device has a certain height in the Z-axis direction, the Z value in the coordinate system (X, Y, Z) is not 0. For ease of description, the Z value here can be understood as being located in the positive direction of the Z-axis.

[0116] It can be understood that the coordinate values ​​of the above-mentioned 8 vertices are obtained at a certain position of the first semiconductor device in the coordinate system; in practical applications, the coordinate value of any point of the first semiconductor device at this position can be determined according to the size of the first semiconductor device; in practical applications, the position of the first semiconductor device in the coordinate system can also be selected according to needs.

[0117] It should be noted that, here, the coordinate values ​​of the four vertices of the first surface of the first semiconductor device are A (X1, Y1, Z1), B (X1, Y2, Z1), C (X2, Y1, Z1), and D (X2, Y2, Z1), respectively.

[0118] Next, according to the relative positional relationship between the element to be aligned and the first surface of the first semiconductor device, one or more coordinate values ​​of the element to be aligned in the coordinate system, ie, the first coordinate set, are determined through calculation and analysis.

[0119] For example, Figure 2f As shown, it is known that the length of the element to be aligned in the X-axis direction is L3; the distance from its geometric center point P to the first side surface 203 of the first semiconductor device is L1, and the distance to the second side surface 204 is L2. Here, the sum of L1 and L2 is equal to the width of the first semiconductor device in the Y-axis direction.

[0120] Through calculation and analysis, the coordinate value of the geometric center position P of the element to be aligned is obtained as P(X2-L3 / 2, L1+Y1, Z1); the coordinate value of the first end of the element to be aligned is R(X2-L3, Y1+L1, Z1) ( Figure 2f not shown); coordinate value Q(X2, Y1+L1, Z1) of the second end.

[0121] Here, the first end and the second end of the to-be-aligned element are two opposite ends of the to-be-aligned element in the X-axis direction, respectively, and the distance between the first end and the second end is L3.

[0122] It can be understood that in the above embodiments of the present invention, the first coordinate set of the component to be aligned in the coordinate system can be obtained according to the specific coordinate values ​​of the first semiconductor device in the coordinate system and the relative position relationship of the component to be aligned in the first semiconductor device.

[0123] In addition, it should be noted that, in actual applications, after a coordinate system is established by using multiple marks on the substrate and the first semiconductor device is fixed on the substrate, the coordinate value of the first semiconductor device or the element to be aligned in the coordinate system is a constant.

[0124] In step 104 , a second coordinate set of the second semiconductor device in the coordinate system may be determined through calculation and analysis.

[0125] In practical applications, the size of the second semiconductor device can also be obtained by the measuring device, including but not limited to the length, width, height, etc. of the second semiconductor device. Combined with the first coordinate set of the element to be aligned in the coordinate system, the second coordinate set of the second semiconductor device in the coordinate system is determined through calculation and analysis.

[0126] It is understandable that, according to actual needs, the element to be aligned can be aligned with any plane or any point in the second semiconductor device. Here, the alignment of the second end of the element to be aligned with the midpoint of the intersection line of the third surface and the seventh side of the second semiconductor device is used as an example for description.

[0127] Exemplarily, the distance between the component to be aligned and the second semiconductor device is X4. It should be noted that when the fifth side surface or the sixth side surface of the component to be aligned contacts the seventh side surface of the second semiconductor device, the value of X4 is 0.

[0128] For example, here, the value of X4 is not 0, such as Figure 2g , Figure 2h As shown, through the coordinate value of the second end Q on the first surface (X2, L1+Y1, Z1), the midpoint of the intersection line between the third surface and the seventh side of the second semiconductor device, such as the coordinate value of point S, can be obtained, that is, S (X2+X4, L1+Y1, Z1).

[0129] It should be noted that the height of the element to be aligned in the Z-axis direction is the same as the height of the third surface of the second semiconductor device in the Z-axis direction; therefore, the height of point S in the Z-axis direction is Z1. When point S is located at other positions of the second semiconductor device, the height of point S in the Z-axis direction can be determined by calculation.

[0130] Here, reference Figure 2g, the length L4 of the second semiconductor device in the X-axis direction, the width L5 in the Y-axis direction and the height H3 in the Z-axis direction can be obtained by the measuring device. When the distance between the second semiconductor device and the element to be aligned is X4, the coordinate values ​​of the third surface of the second semiconductor device are the first vertex I (X2+X4, L1+Y1-L5 / 2, Z1), the second vertex J (X2+X4, L1+Y1+L5 / 2, Z1), the third vertex K (X2+X4+L4, L1+Y1-L5 / 2, Z1), and the fourth vertex L (X2+X4+L4, L1+Y1+L5 / 2, Z1).

[0131] It should be noted that, here, when the first semiconductor device and the second semiconductor device are in contact, that is, the distance between the two in the X-axis direction is 0, when calculating the coordinates of the second semiconductor device, the corresponding coordinate value of the second semiconductor device needs to be smaller than the corresponding distance value.

[0132] Exemplarily, when the first semiconductor device contacts the second semiconductor device, the second end point Q of the element to be aligned of the first semiconductor device and the midpoint of the intersection line of the third surface and the seventh side of the second semiconductor device are the same point, that is, the coordinate value of point S of the second semiconductor device at this time is (X2, L1+Y1, Z1).

[0133] At this time, the first vertex I (X2, L1+Y1-L5 / 2, Z1), the second vertex J (X2, L1+Y1+L5 / 2, Z1), the third vertex K (X2+L4, L1+Y1-L5 / 2, Z1), and the fourth vertex L (X2+L4, L1+Y1+L5 / 2, Z1) of the third surface of the second semiconductor.

[0134] It should be noted that the coordinate value of any point of the second semiconductor device belongs to the second coordinate set.

[0135] Next, in step 105 , the second semiconductor device is placed at a position corresponding to the second coordinate set to achieve alignment between the component to be aligned and the second semiconductor device.

[0136] In practical applications, the second semiconductor device can be moved to a position corresponding to the second coordinate set by a translation stage.

[0137] Exemplarily, a waveguide structure is taken as an example; the waveguide structure includes a first semiconductor device and a second semiconductor device, where the first surface of the first semiconductor device is the side of the first semiconductor device with a waveguide pattern; the third surface of the second semiconductor device is the side of the second semiconductor device with a waveguide pattern. It can be understood that in the waveguide structure, the signal output by the element to be aligned has the strongest ability to propagate along the same waveguide surface; at this time, the loss of the waveguide structure is minimal. In other words, the alignment of the element to be aligned and the second semiconductor device based on the embodiment of the present invention can reduce the loss of the waveguide structure during signal transmission.

[0138] In practical applications, the alignment state between the component to be aligned and the second semiconductor device can be set according to actual needs.

[0139] It should be noted that, in other embodiments, after the second coordinate set is determined, the position state of the second semiconductor device may be in a tilted state, that is, there are angles between multiple planes of the second semiconductor device and the first surface of the first semiconductor device.

[0140] Based on this, in some embodiments, the method further includes:

[0141] Before placing the second semiconductor device at a position corresponding to the second coordinate set, a side and surface parallelism calibration is performed on the first semiconductor device and the second semiconductor device.

[0142] In practical applications, a horizontal calibration instrument can be used to determine whether the first semiconductor device and the second semiconductor device are parallel in the XOY plane, the XOZ plane, and the YOZ plane, respectively.

[0143] Here, it is necessary to calibrate whether the first surface of the first semiconductor device is parallel to the second surface of the second semiconductor device; it is also necessary to calibrate whether the first side surface of the first semiconductor device is parallel to the third side surface of the second semiconductor device; and it is also necessary to calibrate whether the fifth side surface of the first semiconductor device is parallel to the seventh side surface of the second semiconductor device.

[0144] In practical applications, when the parallelism of the side and surface of the first semiconductor device and the second semiconductor device needs to be corrected, the relative position of the second semiconductor device on the measuring device can be adjusted by the translation stage to make the first surface of the first semiconductor device parallel to the third surface of the second semiconductor device; the first side of the first semiconductor device parallel to the third side of the second semiconductor device; and the fifth side of the first semiconductor device parallel to the seventh side of the second semiconductor device. Specifically,

[0145] In some embodiments, the method further comprises:

[0146] before placing the second semiconductor device at a location corresponding to the second set of coordinates, placing the second semiconductor device on a second region of the substrate;

[0147] Based on the first semiconductor device, the relative position relationship between the first semiconductor device and the second semiconductor device is adjusted so that the first side surface is parallel to the third side surface, the second side surface is parallel to the fourth side surface, and the first surface is parallel to the second surface.

[0148] In some embodiments, placing the second semiconductor device at a position corresponding to the second coordinate set includes:

[0149] placing the second semiconductor device at an intermediate position; a projection of the second semiconductor device on the second area when the second semiconductor device is placed at the intermediate position overlaps with a projection of the second semiconductor device on the second area when the second semiconductor device is placed at a position corresponding to the second coordinate set;

[0150] moving the second semiconductor device toward the second region until the second semiconductor device contacts the second region;

[0151] Move the second semiconductor device in a direction away from the second region so that the distance between the third surface of the second semiconductor device and the second region is a first distance; the third surface and the second surface are opposite surfaces of each other; the first distance is the difference between the second distance and the thickness of the second semiconductor device; the second distance is the distance between the second region and the first surface.

[0152] Here, the process of placing the second semiconductor device at the middle position can be understood as determining the position of the second semiconductor device in the X-axis direction and the Y-axis direction in the coordinate system. In other words, after the second semiconductor device is placed at the middle position, the X-axis coordinate value and the Y-axis coordinate value of any point of the second semiconductor device are both determined values.

[0153] Next, the second semiconductor device can be moved by means of a translation stage so that it moves along the Z-axis direction to a position in contact with the second area of ​​the substrate, and then moves a first distance in a direction away from the second area of ​​the substrate to reach a corresponding position in the second coordinate set, thereby achieving alignment between the element to be aligned and the second semiconductor device.

[0154] In practical applications, the second semiconductor device is disposed on the second region of the substrate with the second surface facing the substrate.

[0155] Here, if Figure 2h As shown, the first distance is the difference between the distance H4 between the second region of the substrate and the first surface of the first semiconductor device and the thickness H5 of the second semiconductor device, that is, ΔH, = H4-H5.

[0156] Here, the value of △H' is the distance that the second semiconductor device moves upward based on the second area of ​​the substrate. In other words, when the second semiconductor device contacts the second area of ​​the substrate, it is recorded as the initial value of the movement of the second semiconductor device, and moves upward along the Z-axis direction by a distance of △H', so that the alignment element and the second semiconductor device are aligned.

[0157] In an embodiment of the present invention, a plurality of marks are provided on a substrate, and a coordinate system is formed according to the plurality of marks. After determining a first coordinate set of a to-be-aligned element in the first semiconductor device in the coordinate system, a second coordinate set of the second semiconductor device in the coordinate system is obtained by calculation in combination with the size of the second semiconductor device. Then, the second semiconductor device is placed at a position indicated by the second coordinate set to achieve precise alignment of the to-be-aligned element in the first semiconductor device and the second semiconductor device. In other words, in an embodiment of the present invention, a coordinate system is established to quantify the size and position of the to-be-aligned element and the second semiconductor device. In the process of aligning the to-be-aligned element with the second semiconductor device, the alignment accuracy is improved, thereby reducing the coupling loss between the to-be-aligned element and the second semiconductor device, and improving the reliability of coupling or alignment between multiple semiconductor devices.

[0158] The embodiment of the present invention also provides an alignment system for a semiconductor device, such as Figure 3a , Figure 3b As shown, it includes: a carrier 601, a 3D printing device 602 ( Figure 3a , Figure 3b ), processor 603 ( Figure 3a , Figure 3b ) and a translation stage 604; wherein:

[0159] The carrier 601 is used to place a substrate; a first semiconductor device is arranged on the surface of the substrate with the first surface facing the substrate, and a component to be aligned is arranged on the first surface of the first semiconductor device;

[0160] The 3D printing device 602 is used to form a plurality of marks on the surface of the substrate; the plurality of marks form a coordinate system;

[0161] The processor 603 is configured to obtain a first coordinate set of the component to be aligned in the coordinate system; and determine a second coordinate set based on the first coordinate set and a size of the second semiconductor device;

[0162] The translation stage 604 is coupled to the processor 603 , and is used to place the second semiconductor device at a position corresponding to the second coordinate set under the control of the processor, so as to align the component to be aligned with the second semiconductor device.

[0163] In practical applications, the carrier platform 601 is also used to move in multiple directions under the control of the processor 603 to adjust the relative position of the first semiconductor device and the substrate.

[0164] In some embodiments, the alignment system further includes a measuring device 605; the measuring device is used to obtain images of the substrate, the first semiconductor device and the plurality of marks, and send the images to the processor;

[0165] The processor is specifically configured to determine, according to the image, a first coordinate set of the element to be aligned in the coordinate system.

[0166] In practical applications, the measuring device 605 further includes a measuring device lens barrel 6051 , and the measuring device lens barrel 6051 is used to adjust the magnification or reduction ratio of the measurement image when the measuring device 605 measures the object to be measured.

[0167] In some embodiments, the alignment system also includes a horizontal calibrator 606; the horizontal calibrator 606 is used to adjust the second surface, the third surface, the third side and the fourth side of the second semiconductor device during the alignment of the first semiconductor device and the second semiconductor device, so that the surface of the first semiconductor device is parallel to the surface of the second semiconductor device; the side of the first semiconductor device is parallel to the corresponding side of the second semiconductor device.

[0168] In practical applications, the horizontal calibrator 606 also includes a horizontal calibration lens barrel 6061, which is used to adjust the magnification or reduction ratio of the first semiconductor device or the second semiconductor device during the calibration process of the first semiconductor device and the second semiconductor device by the horizontal calibrator 606, so as to improve the calibration accuracy of the first semiconductor device and the second semiconductor device.

[0169] In some embodiments, the alignment system further includes an optical device fixture 607 ; the optical device fixture 607 is connected to one end of the translation stage 604 and is used to fix the second semiconductor device.

[0170] In practical applications, the optical device fixture 607 is also used to drive the movement of the second semiconductor device according to the movement of the translation stage 604 .

[0171] It should be noted that Figure 3a An alignment system for a semiconductor device according to an embodiment of the present invention; Figure 3b The present invention is a structural schematic diagram of placing a first semiconductor device and a second semiconductor device fixed on a substrate in an alignment system for semiconductor devices.

[0172] The following is a detailed description of the process of achieving semiconductor device alignment using an alignment system for semiconductor devices in conjunction with specific application scenarios.

[0173] The specific method includes the following steps:

[0174] Step 1: Place the front side of the silicon-based chip (the side with the waveguide pattern) on the support platform 601 below the measuring device 605, perform image measurement, and accurately measure the size of the silicon-based chip and the relative position relationship between the optical fiber interface and the silicon-based chip.

[0175] Step 2: Flip-chip bonding the silicon-based chip onto the substrate through bumps, and forming multiple high-precision marking point arrays on the substrate by using a 3D printing process;

[0176] In practical applications, since the waveguide light port mode field of the silicon-based chip is very small, only a few microns, a 3D printing process is required for precise logo printing.

[0177] It is understandable that 3D printing has high precision and the error of the formed marking points is small; the accuracy of the coordinate system established based on the marking points is high. And the marking points formed in the form of a marking array can determine the position of any point according to the array properties.

[0178] Step 3: Place the substrate with the marking point array and the silicon-based chip on the carrier 601 below the measuring device 605. The measuring device 605 can identify the position of the marking point on the substrate and form a coordinate system according to the position of the marking point.

[0179] At the same time, the size of the silicon-based chip after flip-chip packaging is measured by measuring device 605, and the relative position relationship between the silicon-based chip and the optical fiber interface measured by measuring device 605 in step one is combined to perform data analysis and comparison to calculate the specific position of the optical fiber interface in the coordinate system.

[0180] Furthermore, the height difference between the back side of the silicon-based chip and the substrate after flip-chip packaging is measured by the measuring device 605; at this time, the precise three-dimensional coordinates of the optical fiber interface can be obtained.

[0181] Here, the front side of the silicon-based chip and the back side of the silicon-based chip are opposite sides to each other.

[0182] Step 4: Place the optical device to be coupled on an optical device fixture, wherein the optical device fixture is fixed on a translation stage 604, and the translation stage 604 is provided with a pressure sensor.

[0183] Using a level calibrator 606, determine whether the silicon-based chip is parallel to each surface or side of the optical device to be coupled;

[0184] If the silicon-based chip and the optical device to be coupled are not parallel in the XOZ plane (horizontal direction), the surface of the optical device to be coupled can be adjusted by the translation stage 604 to make the surface of the silicon-based chip parallel to the surface of the optical device to be coupled.

[0185] Alternatively, the side surface of the optical device to be coupled is adjusted by the translation stage 604 so that the side surface of the silicon-based chip is parallel to the side surface of the optical device to be coupled.

[0186] It should be noted that the parallelism calibration between the silicon-based chip and each surface or side of the optical device to be coupled can be performed in multiple times.

[0187] Step 5: After the silicon-based chip and the optical device to be coupled are calibrated in the three planes of XOZ, XOY, and YOZ respectively, the optical device to be coupled is moved to the middle position by the translation stage 604 to determine the XOY plane coordinates of the coupling fixture;

[0188] At this time, the coordinate value of any point of the optical device to be coupled in the X-axis direction and the coordinate value in the Y-axis direction are constants; (here, the optical device to be coupled and the silicon-based chip are separated by a distance L4 in the X-axis direction, and L4 is not 0, so as to avoid the optical device to be coupled from colliding with the silicon-based chip when moving along the Z-axis direction).

[0189] In practical applications, the distance L4 between the optical device to be coupled and the silicon-based chip in the X-axis direction is 10um-20um.

[0190] Then, the coupling fixture is slowly moved downward along the Z axis to make the optical device to be coupled lightly touch the first area of ​​the substrate. When a pressure value appears on the pressure sensor on the coupling fixture, the initial value of the Z axis of the coupling fixture is recorded.

[0191] It should be noted that after recording the initial value of the coupling fixture, it should be moved upward along the Z axis immediately to avoid damaging the optical device to be coupled.

[0192] Step 6: The measuring device 605 is used to measure and calculate to determine the first distance that the optical device to be coupled moves along the Z-axis direction, so as to achieve alignment between the silicon-based chip and the optical device to be coupled.

[0193] In practical applications, the signal output effect of the silicon-based chip can be detected by an external detection instrument, and the coupling fixture can be fine-tuned to further reduce the coupling loss to further complete optical coupling or alignment.

[0194] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present invention, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention. The serial numbers of the above-mentioned embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments.

[0195] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for aligning a semiconductor device, characterized in that: include: A first semiconductor device having a to-be-aligned element on a first surface and a second semiconductor device are provided; the first semiconductor device is disposed on a surface of a substrate with the first surface facing the substrate; forming a plurality of marks on the surface of the substrate, and forming a three-dimensional coordinate system based on the plurality of marks; Acquire a first coordinate set of the component to be aligned in the three-dimensional coordinate system; determining a second coordinate set based on the first coordinate set and a size of the second semiconductor device; placing the second semiconductor device at an intermediate position; a projection of the second semiconductor device on the substrate surface when the second semiconductor device is placed at the intermediate position overlaps with a projection of the second semiconductor device on the substrate surface when the second semiconductor device is placed at a position corresponding to the second coordinate set; Moving the second semiconductor device toward the substrate surface until the second semiconductor device contacts the substrate surface; The second semiconductor device is moved in a direction away from the substrate surface to align the component to be aligned with the second semiconductor device.

2. The alignment method according to claim 1, characterized in that: A plurality of marks are formed on the substrate, comprising: A plurality of marks are formed on the surface of the substrate through a three-dimensional 3D printing process.

3. The alignment method according to claim 1, characterized in that: Acquiring a first coordinate set of the component to be aligned in the three-dimensional coordinate system includes: Acquiring a position of the component to be aligned in the first semiconductor device; Acquire a third coordinate set of the first semiconductor device in the three-dimensional coordinate system; The first coordinate set is determined according to the position of the element to be aligned in the first semiconductor device and the third coordinate set.

4. The alignment method according to claim 1, characterized in that: The method further comprises: Before placing the second semiconductor device at a position corresponding to the second coordinate set, a side and surface parallelism calibration is performed on the first semiconductor device and the second semiconductor device.

5. The alignment method according to claim 1, characterized in that: The first semiconductor device includes an optical chip, the element to be aligned includes an optical fiber interface, and the second semiconductor device includes an optical device to be coupled; the substrate surface includes a first area and a second area arranged in parallel, and the thickness of the substrate in the first area is greater than the thickness of the substrate in the second area; the first semiconductor device is arranged on the first area, and the second semiconductor device is arranged on the second area.

6. The alignment method according to claim 5, characterized in that: The shapes of the first semiconductor device and the second semiconductor device both include a cube, the first semiconductor device has a first side surface and a second side surface perpendicular to each other, the first side surface and the second side surface are perpendicular to the first surface, and the extension direction of the element to be aligned is parallel to the first side surface; the second semiconductor device has a second surface and a third side surface and a fourth side surface perpendicular to each other, the second semiconductor device is arranged on the surface of the substrate in a manner that the second surface faces the substrate, and the third side surface and the fourth side surface are perpendicular to the second surface; The method further comprises: before placing the second semiconductor device at a location corresponding to the second set of coordinates, placing the second semiconductor device over a second region of the substrate; Based on the first semiconductor device, the relative position relationship between the first semiconductor device and the second semiconductor device is adjusted so that the first side surface is parallel to the third side surface, the second side surface is parallel to the fourth side surface, and the first surface is parallel to the second surface.

7. The alignment method according to claim 6, characterized in that: The step of moving the second semiconductor device in a direction away from the substrate surface comprises: Move the second semiconductor device in a direction away from the second region so that the distance between the third surface of the second semiconductor device and the second region is a first distance; the third surface and the second surface are opposite surfaces of each other; the first distance is the difference between the second distance and the thickness of the second semiconductor device; the second distance is the distance between the second region and the first surface.

8. The alignment method according to claim 5, characterized in that: The method further comprises: Disposing a plurality of bumps in a first region of the substrate; The first surface of the first semiconductor device is fixed on the plurality of bumps by a flip-chip bonding process.

9. An alignment system for a semiconductor device, characterized in that: include: A carrier, a 3D printing device, a processor and a translation stage; wherein: The carrier is used to place a substrate; a first semiconductor device is arranged on the surface of the substrate with the first surface facing the substrate, and a component to be aligned is arranged on the first surface of the first semiconductor device; The 3D printing device is used to form a plurality of marks on the surface of the substrate; the plurality of marks are used to form a three-dimensional coordinate system; The processor is used to obtain a first coordinate set of the component to be aligned in the three-dimensional coordinate system; and determine a second coordinate set based on the first coordinate set and the size of the second semiconductor device; The translation stage is coupled to the processor, and is used to, under the control of the processor, place the second semiconductor device at an intermediate position; a projection of the second semiconductor device on the substrate surface when the second semiconductor device is placed at the intermediate position overlaps with a projection of the second semiconductor device on the substrate surface when the second semiconductor device is placed at a position corresponding to the second coordinate set; move the second semiconductor device in a direction close to the substrate surface until it contacts the substrate surface; and move the second semiconductor device in a direction away from the substrate surface so that the element to be aligned is aligned with the second semiconductor device.

10. The alignment system according to claim 9, characterized in that The alignment system further includes a measuring device; the measuring device is used to obtain images of the substrate, the first semiconductor device and the plurality of marks, and send the images to the processor; The processor is specifically configured to determine, based on the image, a first coordinate set of the component to be aligned in the three-dimensional coordinate system.

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