Fan-out package structure and its manufacturing method

Abstract

Embodiments of the present invention provide a fan-out package structure and a preparation method thereof, relating to the technical field of semiconductor packaging. A main chip is disposed in a first plastic package body. Meanwhile, a first groove is formed on a first surface of the first plastic package body, a first mounted chip is mounted in the first groove, and a first conductive pillar is disposed in the first plastic package body to achieve electrical connection of the main chip. Compared with the conventional technology, in the present invention, the main chip and the first mounted chip are stacked and embedded in the first plastic package body, and the first mounted chip is stacked above the main chip in space, so that the package size can be greatly reduced compared with the flat fan-out structure, the package area is reduced, which is beneficial to the miniaturization of products. At the same time, the main chip is connected to the first wiring combination layer through the first conductive pillar, which can greatly reduce the transmission rate and make the stacking performance of its fan-out products more excellent.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular, to a fan-out package structure and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer-level package (FOWLP) structures are widely used in the semiconductor industry. Generally, individual chips are cut from a wafer and then packaged on a carrier wafer. The main advantages are high-density integration, small package product size, excellent product performance, fast signal transmission frequency, etc. The fan-out technology mainly realizes multi-pin output and the smaller the output pin pitch. When meeting multi-chip packaging, it often requires a larger packaging area, cannot complete the stacking structure, and is not conducive to the miniaturization of products. Summary of the Invention

[0003] The objectives of the present invention include, for example, providing a fan-out package structure and a preparation method thereof, which can complete the stacking structure of the fan-out package, reduce the packaging area, and be conducive to the miniaturization of products.

[0004] Embodiments of the present invention may be implemented as follows:

[0005] In a first aspect, the present invention provides a fan-out package structure, including:

[0006] A first encapsulant having opposite first and second surfaces;

[0007] A main chip disposed in the first encapsulant;

[0008] A first mounted chip disposed in the first encapsulant and exposed on the first surface;

[0009] A first wiring combination layer disposed on the first surface;

[0010] A first solder ball disposed on the first wiring combination layer;

[0011] Wherein, a first conductive pillar is further disposed in the first encapsulant, the first conductive pillar penetrates through to the main chip and is exposed on the first surface, the first wiring combination layer is electrically connected to the main chip through the first conductive pillar, a first groove is formed on the first surface, the first mounted chip is mounted in the first groove, the main chip and the first mounted chip are spaced apart, and the first wiring combination layer is electrically connected to the first mounted chip.

[0012] In an alternative embodiment, the fan-out package structure further includes a second encapsulant. The main chip is exposed on the second surface. The second encapsulant is disposed on the second surface and covers the main chip.

[0013] In an alternative embodiment, a first conductive pad is disposed on a side of the main chip close to the first surface, and the first conductive pillar is connected to the first conductive pad.

[0014] In an alternative embodiment, a conductive layer is disposed in the first groove. The conductive layer extends to the first surface and is electrically connected to the first wiring combination layer. A second mounted chip is further disposed in the first groove. The second mounted chip is attached to the conductive layer and is electrically connected to the conductive layer. The first mounted chip is attached to the second mounted chip on the opposite side, and a third conductive pad is disposed on a side away from the second mounted chip.

[0015] In an alternative embodiment, an adhesive layer is disposed between the first mounted chip and the second mounted chip.

[0016] In an alternative embodiment, the conductive layer extends toward two sides of the first groove and is connected to the first conductive pillar.

[0017] In an alternative embodiment, a second groove is disposed on a surface of the second encapsulant away from the first encapsulant. A third mounted chip is disposed in the second groove, and a second wiring combination layer is further disposed on a surface of the second encapsulant away from the first encapsulant. The second wiring combination layer is electrically connected to the third mounted chip.

[0018] In an alternative embodiment, a second conductive pillar is further disposed in the first encapsulant. Two ends of the second conductive pillar respectively penetrate through to the first wiring combination layer and the second wiring combination layer. The first wiring combination layer is electrically connected to the second wiring combination layer through the second conductive pillar.

[0019] In an alternative embodiment, the first wiring combination layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the first surface, and a first metal layer is disposed in the first dielectric layer. The first metal layer is electrically connected to the first mounted chip and the first conductive pillar. The second dielectric layer is disposed on the first dielectric layer, and a second metal layer is disposed in the second dielectric layer. The second metal layer is electrically connected to the first metal layer. The solder ball is disposed on the second metal layer.

[0020] In a second aspect, the present invention provides a method for manufacturing a fan-out package structure for manufacturing the fan-out package structure according to any one of the foregoing embodiments. The method includes:

[0021] Mount the main chip on the carrier;

[0022] Mold on the carrier to form a first molding body covering the main chip, the first molding body having opposite first and second surfaces;

[0023] Remove the carrier so that the main chip is exposed on the second surface;

[0024] Form a first groove by grooving on the first surface;

[0025] Mount a first mounted chip in the first groove;

[0026] Form a wiring combination layer on the first surface;

[0027] Bump on the wiring combination layer to form solder balls;

[0028] Wherein, a first conductive post is further arranged in the first molding body, the first conductive post penetrates through to the main chip and is exposed on the first surface, the first wiring combination layer is electrically connected to the main chip through the first conductive post, the main chip and the first mounted chip are arranged at intervals, and the first wiring combination layer is electrically connected to the first mounted chip.

[0029] In an alternative embodiment, after the step of removing the carrier, the method further includes:

[0030] Mold on the second surface to form a second molding body covering the main chip.

[0031] The beneficial effects of the embodiments of the present invention include, for example:

[0032] The fan-out package structure and its manufacturing method provided by the present invention arrange the main chip in the first molding body, and at the same time open a first groove on the first surface of the first molding body, mount the first mounted chip in the first groove, and arrange a first conductive post in the first molding body, the first conductive post penetrates through to the main chip and is exposed on the first surface, so that the main chip can be electrically exposed, and finally a first wiring layer is arranged on the first surface of the first molding body and bumping is completed, thereby completing the fan-out package of the main chip and the first mounted chip. Compared with the conventional technology, in the present invention, the main chip and the first mounted chip are stacked and embedded in the first molding body, and the first mounted chip is stacked above the main chip in space, so that the package size can be greatly reduced compared with the flat fan-out structure, the package area is reduced, which is beneficial to the miniaturization of the product. At the same time, the main chip is connected to the first wiring combination layer through the first conductive post, which can greatly reduce the transmission rate and make the stacking performance of its fan-out product more excellent. Description of the Drawings

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0034] Figure 1 Schematic diagram of the fan-out package structure provided by the first embodiment of the present invention;

[0035] Figures 2 to 10 Process flow chart of the preparation method of the fan-out package structure provided by the first embodiment of the present invention;

[0036] Figure 11 Schematic diagram of the fan-out package structure provided by the second embodiment of the present invention;

[0037] Figure 12 Schematic diagram of the fan-out package structure provided by the third embodiment of the present invention.

[0038] Icons: 100 - fan-out package structure; 110 - first plastic package; 111 - first groove; 113 - first conductive post; 115 - second conductive post; 120 - main chip; 121 - first conductive pad; 130 - first mounted chip; 131 - second conductive pad; 140 - first wiring combination layer; 141 - first dielectric layer; 143 - second dielectric layer; 145 - first metal layer; 147 - second metal layer; 150 - first solder ball; 160 - second plastic package; 161 - second groove; 170 - second mounted chip; 171 - conductive layer; 173 - adhesive layer; 180 - third mounted chip; 190 - second wiring combination layer; 191 - second solder ball; 200 - carrier; 210 - adhesive film layer. Specific embodiments

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0040] Accordingly, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0041] It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0042] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0043] If terms such as "first", "second", etc. are used only for distinguishing descriptions, they cannot be understood as indicating or implying relative importance.

[0044] As disclosed in the background art, for the case of multi-chips in the existing fan-out package structure, it usually adopts a flat package structure, which often requires a larger package area and cannot complete a stacked structure, thus being unfavorable for the miniaturization of products.

[0045] Moreover, in the conventional package structure, silicon wafers are usually used as the chip carrier substrate, and the chips are accommodated by means of etching and grooving. However, on the one hand, the etching process is complex, and on the other hand, during the etching process, oxides are easily generated, causing unstable grounding resistance of the edge pads. In addition, the materials between the silicon wafer substrate and the plastic package are inconsistent, and the coefficient of thermal expansion (CTE) does not match, resulting in easy warping of the plastic package.

[0046] To solve the above problems, the present invention provides a fan-out package structure and a preparation method thereof. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0047] First Embodiment

[0048] Refer to Figure 1 , this embodiment provides a fan-out package structure 100, which can complete the stacked structure of the fan-out package, reduce the package area, and is beneficial to the miniaturization of products. Moreover, it does not require an etching process, the process is simple, and it can effectively alleviate the problem of plastic package warping, effectively improving the product performance.

[0049] This embodiment provides a fan-out package structure 100, which includes a first plastic package body 110, a main chip 120, a first mounted chip 130, a first wiring combination layer 140, and a first solder ball 150. The first plastic package body 110 has opposite first and second surfaces. The main chip 120 is disposed within the first plastic package body 110 and is exposed on the second surface. The first mounted chip 130 is disposed within the first plastic package body 110 and is exposed on the first surface. The first wiring combination layer 140 is disposed on the first surface, and the first solder ball 150 is disposed on the first wiring combination layer 140. Wherein, a first conductive post 113 is further disposed within the first plastic package body 110. The first conductive post 113 penetrates through to the main chip 120 and is exposed on the first surface. The first wiring combination layer 140 is electrically connected to the main chip 120 through the first conductive post 113. A first groove 111 is formed on the first surface, and the first mounted chip 130 is mounted within the first groove 111. The main chip 120 and the first mounted chip 130 are spaced apart, and the first wiring combination layer 140 is electrically connected to the first mounted chip 130.

[0050] In this embodiment, during actual preparation, the first plastic package body 110 covering the main chip 120 can be first formed, then the first groove 111 is formed on the first surface of the first plastic package body 110 by means of laser grooving, then the first mounted chip 130 is mounted, and finally the wiring and ball mounting operations are completed. It should be noted that the depth of the first groove 111 in this embodiment is adapted to the thickness of the first mounted chip 130, so that when the first mounted chip 130 is mounted in the first groove 111, the surface of the first mounted chip 130 is flush with the first surface, which is convenient for directly forming the first wiring combination layer 140 on the first surface subsequently.

[0051] Furthermore, the fan-out package structure 100 provided in this embodiment further includes a second plastic package body 160. The main chip 120 is exposed on the second surface, and the second plastic package body 160 is disposed on the second surface and covers the main chip 120. Specifically, the main chip 120 can be first mounted on the carrier 200, the first plastic package body 110 is formed by plastic encapsulation, the carrier 200 is removed, and the second plastic package body 160 is formed by plastic encapsulation again on the second surface of the first plastic package body 110. The second plastic package body 160 can effectively encapsulate and protect the exposed part of the chip, and improve the strength of the overall package structure.

[0052] It should be noted that the second plastic package body 160 may not be provided on the second surface of the first plastic package body 110 here, so that the back surface of the main chip 120 is exposed, and the self-shell structure of the main chip 120 is used to achieve protection.

[0053] In this embodiment, the first encapsulant 110 and the second encapsulant 160 are made of the same encapsulation material, such as epoxy resin, etc. Since the first encapsulant 110 and the second encapsulant 160 use the same encapsulation material, the problem of encapsulation warping caused by the mismatch of the thermal expansion coefficients of the materials can be effectively avoided.

[0054] In this embodiment, a first conductive pad 121 is provided on one side of the main body chip 120 close to the first surface, and the first conductive pillar 113 is connected to the first conductive pad 121. Specifically, the main body chip 120 is mounted with the pad facing up. After the first encapsulant 110 is completed or after the first mounted chip 130 is mounted, a via hole penetrating through to the first conductive pad 121 on the main body chip 120 is formed on the first surface by a laser grooving process, and then the via hole is filled with a conductive adhesive to complete the preparation of the first conductive pillar 113. Of course, here, after the via hole is formed, an electroplated copper pillar operation can be completed in the via hole with the first conductive pad 121 as the base to form a metal pillar, which is exposed on the first surface.

[0055] In this embodiment, the first groove 111 is formed by a laser grooving process. The first mounted chip 130 is also mounted with the pad facing up. Before the first mounted chip 130 is mounted, an adhesive can be coated in the first groove 111 or on the back of the first mounted chip 130, and the first mounted chip 130 is adhered in the first groove 111 by using the adhesive to achieve fixation. Among them, a second conductive pad 131 is provided on the first mounted chip 130. When the first mounted chip 130 is mounted, the second conductive pad 131 is set facing up, and the back of the first mounted chip 130 is attached to the first groove 111.

[0056] In this embodiment, the first wiring composite layer 140 includes a first dielectric layer 141 and a second dielectric layer 143. The first dielectric layer 141 is disposed on the first surface, and a first metal layer 145 is disposed in the first dielectric layer 141. The first metal layer 145 is electrically connected to the first mounted chip 130 and the first conductive pillar 113. The second dielectric layer 143 is disposed on the first dielectric layer 141, and a second metal layer 147 is disposed in the second dielectric layer 143. The second metal layer 147 is electrically connected to the first metal layer 145. The solder ball is disposed on the second metal layer 147. Specifically, after the preparation of the first conductive pillar 113 is completed, a dielectric material is spin-coated on the first surface of the first encapsulant 110 to form the first dielectric layer 141. The first dielectric layer 141 covers the first groove 111, and can also fill the gap between the first mounted chip 130 and the side wall of the first groove 111 to ensure the fixing effect of the first mounted chip 130. After the first dielectric layer 141 is formed, a patterned opening can be formed through an exposure and development / laser grooving process, and a copper layer is electroplated in the opening groove to form the first metal layer 145, wherein the opening groove penetrates through the pad of the first mounted chip 130 and the first conductive pillar 113, so that the first metal layer 145 can be directly in electrical contact with the first conductive pillar 113 and the pad of the first mounted chip 130. After the first metal layer 145 is formed, a dielectric material is spin-coated again to form the second dielectric layer 143. Again, a patterned opening is formed on the second dielectric layer 143 by using an exposure and development / laser grooving process, and a copper layer is electroplated in the opening groove to form the second metal layer 147, completing the wiring operation. Finally, the ball mounting operation is completed on the second metal layer 147.

[0057] It should be noted that in this embodiment, the first metal layer 145 is electrically connected to the pad of the first mounted chip 130 and the first conductive pillar 113 at the same time, and signal transmission is realized through the first conductive pillar 113, which can greatly reduce the transmission rate and make the stacking performance of its fan-out type products more excellent.

[0058] In this embodiment, the first dielectric layer 141 and the second dielectric layer 143 can adopt the same dielectric material, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. At the same time, both the first metal layer 145 and the second metal layer 147 are copper layers, having good electrical conduction functions.

[0059] It should be noted that in order to better complete the production of the solder ball, an electroplating process can be used again on the second metal layer 147 to form a conductive bump structure, which can be used as a UBM layer to improve the welding performance of the solder ball. The material of the UBM layer can be at least one of titanium and tungsten.

[0060] After the preparation of the first wiring composite layer 140 is completed, solder balls can be formed on the second metal layer 147 / conductive protrusions by means of stencil printing or ball placement. The solder ball material can be SnAg, SnAgCu, etc. Finally, a cutting process is performed to form the final product.

[0061] With reference to Figures 2 to 10 , this embodiment also provides a method for manufacturing a fan-out package structure for manufacturing the fan-out package structure 100 as described above. The method includes the following steps:

[0062] S1: Mount the main chip 120 on the carrier 200.

[0063] Refer to Figure 2 , specifically, provide a carrier 200, and after mounting the adhesive film layer 210 on the carrier 200, mount the main chip 120 again, where the pads of the main chip 120 are placed upward. The carrier 200 can be made of materials such as glass, silicon oxide, and metal. The material of the adhesive film layer 210 can be a UV adhesive layer, which can be separated by irradiating UV light, facilitating the subsequent peeling of the carrier 200. The adhesive film layer 210 can also be one of an adhesive, epoxy resin, and polyimide (PI). That is to say, the adhesive film layer 210 can be cured by UV (ultraviolet) or heat, and is used as a separation layer between the subsequent formed chip package structure to facilitate the removal of the carrier 200.

[0064] S2: Encapsulate on the carrier 200 to form a first encapsulant 110 covering the main chip 120.

[0065] Refer to Figure 3 , specifically, after the mounting of the main chip 120 is completed, use the encapsulation process to form the first encapsulant 110, where the first encapsulant 110 has opposite first and second surfaces, and the second surface is attached to the carrier 200.

[0066] S3: Remove the carrier 200.

[0067] Refer to Figure 4 , specifically, adopt the method of irradiating UV light to make the adhesive film layer 210 fall off, thereby peeling off the carrier 200 and exposing the main chip 120 on the second surface.

[0068] S4: Encapsulate on the second surface to form a second encapsulant 160.

[0069] Refer to Figure 5, specifically, after removing the vehicle 200, rotate the first encapsulant 110 and perform an encapsulation process on the second surface of the first encapsulant 110 to form the second encapsulant 160, which is used to protect the bottom structure, that is, to protect the main chip 120. The materials used for the first encapsulant 110 and the second encapsulant 160 are the same, which can effectively avoid the encapsulation warping problem caused by the mismatch of the thermal expansion coefficients of the materials.

[0070] S5: Form a first groove 111 by grooving on the first surface.

[0071] See Figure 6 , specifically, use a laser grooving process to groove on the first surface of the first encapsulant 110 to form the first groove 111, and the grooving depth can be determined according to the thickness of the first mounted chip 130 to be mounted.

[0072] S6: Mount the first mounted chip 130 in the first groove 111.

[0073] See Figure 7 , specifically, an adhesive can be coated in the first groove 111 or on the back of the first mounted chip 130, and the first mounted chip 130 is bonded and fixed in the first groove 111 by using the adhesive to complete the fan-out chip stacking. The size of the first groove 111 can be designed according to the size of the first mounted chip 130.

[0074] S7: Form a first conductive pillar 113 that penetrates through to the main chip 120.

[0075] See Figure 8 , specifically, after completing the mounting of the first mounted chip 130, use the laser grooving process again to groove on the first surface of the first encapsulant 110 to form a via that penetrates through to the main chip 120. The via corresponds to the first conductive pad 121 and exposes the first conductive pad 121. Then, fill the via with conductive glue, and after curing, the first conductive pillar 113 is formed. The first conductive pillar 113 is exposed on the first surface.

[0076] Of course, the first conductive pillar 113 can also be made by other processes here. For example, after forming the via, a metal pillar is formed in the via by electroplating a copper layer, thereby forming the first conductive pillar 113.

[0077] S8: Form a wiring combination layer on the first surface.

[0078] See Figure 9, specifically, after the preparation of the first conductive pillar 113, a dielectric material is spin-coated on the first surface of the first encapsulant 110 to form a first dielectric layer 141. The first dielectric layer 141 covers the first groove 111 and can also fill the gap between the first mounted chip 130 and the sidewall of the first groove 111 to ensure the fixing effect of the first mounted chip 130. After the formation of the first dielectric layer 141, a patterned opening can be formed by photolithography / laser grooving process, and a copper layer is electroplated in the opening groove to form a first metal layer 145, where the opening groove penetrates through the pads of the first mounted chip 130 and the first conductive pillar 113, so that the first metal layer 145 can be in direct electrical contact with the first conductive pillar 113 and the pads of the first mounted chip 130. After the formation of the first metal layer 145, a dielectric material is spin-coated again to form a second dielectric layer 143. A patterned opening is formed on the second dielectric layer 143 by photolithography / laser grooving process again, and a copper layer is electroplated in the opening groove to form a second metal layer 147, completing the wiring operation.

[0079] S9: Bumping is performed on the wiring combination layer to form solder balls.

[0080] See Figure 10 , specifically, after the preparation of the second metal layer 147, the bumping operation is completed on the second metal layer 147. Solder balls can be formed on the second metal layer 147 / conductive protrusions by stencil printing or bumping method, where the solder ball material can be SnAg, SnAgCu, etc. Finally, a dicing process is performed to form the final product.

[0081] In summary, this embodiment provides a fan-out package structure 100 and a method for manufacturing the same. The main chip 120 is disposed within the first encapsulant 110. Meanwhile, a first groove 111 is formed on the first surface of the first encapsulant 110, and the first mounted chip 130 is mounted within the first groove 111. A first conductive pillar 113 is disposed within the first encapsulant 110, and the first conductive pillar 113 penetrates through to the main chip 120 and is exposed on the first surface, enabling the main chip 120 to be electrically exposed. Finally, a first wiring layer is disposed on the first surface of the first encapsulant 110, and ball implantation is completed, thereby completing the fan-out package of the main chip 120 and the first mounted chip 130. Compared with the conventional technology, in this embodiment, the main chip 120 and the first mounted chip 130 are stacked and embedded within the first encapsulant 110, and the first mounted chip 130 is stacked above the main chip 120 in space. Therefore, compared with the flat fan-out structure, the package size can be significantly reduced, the package area can be shrunk, which is beneficial to the miniaturization of the product. At the same time, the main chip 120 is connected to the first wiring combination layer 140 through the first conductive pillar 113, which can significantly reduce the transmission rate, making the stacking performance of its fan-out product more excellent. Moreover, the first encapsulant 110 and the second encapsulant 160 are made of the same material, which can effectively alleviate the encapsulant warping phenomenon and ensure the encapsulation quality.

[0082] Second Embodiment

[0083] Refer to Figure 11 , this embodiment provides a fan-out package structure 100. Its basic structure, principle, and the resulting technical effects are the same as those of the first embodiment. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment.

[0084] In this embodiment, the fan-out package structure 100 includes a first encapsulant 110, a main chip 120, a first mounted chip 130, a first wiring combination layer 140, and a first solder ball 150. The first encapsulant 110 has opposite first and second surfaces. The main chip 120 is disposed within the first encapsulant 110 and is exposed on the second surface. The first mounted chip 130 is disposed within the first encapsulant 110 and is exposed on the first surface. The first wiring combination layer 140 is disposed on the first surface, and the first solder ball 150 is disposed on the first wiring combination layer 140. Among them, a first conductive pillar 113 is further disposed within the first encapsulant 110. The first conductive pillar 113 penetrates through to the main chip 120 and is exposed on the first surface. The first wiring combination layer 140 is electrically connected to the main chip 120 through the first conductive pillar 113. The first surface is provided with a first groove 111, and the first mounted chip 130 is mounted within the first groove 111. The main chip 120 and the first mounted chip 130 are spaced apart, and the first wiring combination layer 140 is electrically connected to the first mounted chip 130.

[0085] In this embodiment, a conductive layer 171 is disposed in the first groove 111. The conductive layer 171 extends to the first surface and is electrically connected to the first wiring combination layer 140. A second mounted chip 170 is also disposed in the first groove 111. The second mounted chip 170 is attached to the conductive layer 171 and is electrically connected to the conductive layer 171. The first mounted chip 130 is attached to the second mounted chip 170 in a back-to-back manner, and a third conductive pad is disposed on a side away from the second mounted chip 170. Specifically, the second mounted chip 170 adopts a flip-chip structure, and its bottom pads are directly in electrical contact with the conductive layer 171. The first mounted chip 130 and the second mounted chip 170 are attached to each other in a back-to-back manner and are jointly disposed in the first groove 111, which can further increase the stacking quantity.

[0086] It should be noted that the depth of the first groove 111 here needs to be adapted to the sum of the thicknesses of the first mounted chip 130 and the second mounted chip 170, and the conductive layer 171 climbs from the bottom side of the first groove 111 to the outside, enabling the electrical connection of the second mounted chip 170. Preferably, in this embodiment, the first mounted chip 130 and the second mounted chip 170 have the same size specifications, which is convenient for the two to be attached and also convenient for preparing the first groove 111.

[0087] In this embodiment, an adhesive layer 173 is disposed between the first mounted chip 130 and the second mounted chip 170. Specifically, after the first groove 111 is formed, the conductive layer 171 is continuously formed in the first groove 111, then the second mounted chip 170 is attached to the conductive layer 171, and then an adhesive is coated on the back of the second mounted chip 170 or the first mounted chip 130, so that the first mounted chip 130 can be fixedly adhered to the second mounted chip 170 through the adhesive layer 173.

[0088] In this embodiment, the conductive layer 171 extends toward both sides of the first groove 111 and is connected to the first conductive posts 113. Specifically, after the first groove 111 is formed, the conductive layer 171 can be formed by sputtering or electroplating processes. The conductive layer 171 can cover the first conductive posts 113, thereby realizing the electrical connection with the first conductive posts 113.

[0089] It should be noted that when the subsequent first wiring combination layer 140 is formed, the first metal layer 145 can be electrically in contact with the pads of the first mounted chip 130 and the conductive layer 171 at the same time, so that the main chip 120, the first mounted chip 130, and the second mounted chip 170 can be electrically connected as a whole.

[0090] In this embodiment, when forming the first wiring combination layer 140, since the first conductive posts 113 are prepared in advance and the first conductive posts 113 are exposed in the encapsulant 110, the first conductive posts 113 can play a role in wiring identification and positioning during wiring, facilitating precise wiring. At the same time, when forming the conductive layer 171 and mounting the second mounted chip 170, the first conductive posts 113 can also play a role in positioning and identification, so as to accurately delimit the setting range of the conductive layer 171 and accurately mount the second mounted chip 170 in the first groove 111, ensuring the mounting accuracy of the second mounted chip 170.

[0091] The fan-out package structure 100 provided in this embodiment, by setting the conductive layer 171 and stacking the first mounted chip 130 and the second mounted chip 170 together in the first groove 111, further improves the stacking quantity compared with the first embodiment, making its integration degree higher, and the fan-out structure has more functions and better performance. And in the case of the same number of chips, the package size of the product is smaller, which is more conducive to the miniaturization of the product.

[0092] Third Embodiment

[0093] See Figure 12 , this embodiment provides a fan-out package structure 100, whose basic structure, principle, and the resulting technical effects are the same as those of the first embodiment. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment.

[0094] This embodiment provides a fan-out package structure 100, including a first encapsulant 110, a main chip 120, a first mounted chip 130, a first wiring combination layer 140, a first solder ball 150, and a second encapsulant 160. The first encapsulant 110 has opposite first and second surfaces. The main chip 120 is disposed in the first encapsulant 110 and is exposed on the second surface. The first mounted chip 130 is disposed in the first encapsulant 110 and is exposed on the first surface. The first wiring combination layer 140 is disposed on the first surface. The first solder ball 150 is disposed on the first wiring combination layer 140. Among them, a first conductive post 113 is further disposed in the first encapsulant 110. The first conductive post 113 penetrates through to the main chip 120 and is exposed on the first surface. The first wiring combination layer 140 is electrically connected to the main chip 120 through the first conductive post 113. A first groove 111 is formed on the first surface. The first mounted chip 130 is mounted in the first groove 111. The main chip 120 and the first mounted chip 130 are spaced apart. The first wiring combination layer 140 is electrically connected to the first mounted chip 130. The main chip 120 is exposed on the second surface. The second encapsulant 160 is disposed on the second surface and covers the main chip 120.

[0095] In this embodiment, a second groove 161 is provided on a surface of the second encapsulation body 160 away from the first encapsulation body 110. A third mounted chip 180 is disposed in the second groove 161, and a second wiring combination layer 190 is further provided on the surface of the second encapsulation body 160 away from the first encapsulation body 110. The second wiring combination layer 190 is electrically connected to the third mounted chip 180. Specifically, second solder balls 191 are further provided on the second wiring combination layer 190. The structure of the second wiring combination layer 190 is the same as that of the first wiring combination layer 140, and will not be described in detail here.

[0096] In this embodiment, a second conductive column 115 is further provided in the first encapsulation body 110. Two ends of the second conductive column 115 respectively penetrate through to the first wiring combination layer 140 and the second wiring combination layer 190. The first wiring combination layer 140 is electrically connected to the second wiring combination layer 190 through the second conductive column 115. Specifically, the second conductive column 115 penetrates through the first encapsulation body 110 and the second encapsulation body 160, thereby electrically connecting the first wiring layer and the second wiring layer into one body. The material and preparation method of the second conductive column 115 are the same as those of the first conductive column 113, and will not be described in detail here.

[0097] It should be noted that the depth of the second groove 161 is adapted to the thickness of the third mounted chip 180. In order to prevent the second groove 161 from penetrating to the surface of the main chip 120, the thickness of the second encapsulation body 160 can be made larger and greater than the thickness of the third mounted chip 180.

[0098] The fan-out package structure 100 provided in this embodiment realizes a double-sided groove structure by opening a second groove 161 on the second encapsulation body 160 and attaching the third mounted chip 180. Compared with the first embodiment, the stacking quantity is further improved, making its integration degree higher, and the fan-out structure has more functions and better performance. And in the case of the same number of chips, the package size of the product is smaller, which is more conducive to the miniaturization of the product.

[0099] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A fan-out package structure, characterized in that, it includes: A first encapsulant, the first encapsulant having opposite first and second surfaces; A main chip disposed within the first encapsulant; A first mounted chip disposed within the first encapsulant and exposed on the first surface; A first wiring combination layer disposed on the first surface; A first solder ball disposed on the first wiring combination layer; Wherein, a first conductive pillar is further disposed within the first encapsulant, the first conductive pillar penetrating through to the main chip and exposed on the first surface, the first wiring combination layer being electrically connected to the main chip through the first conductive pillar, the first surface being formed with a first groove by a laser grooving process, the first mounted chip being mounted within the first groove, the main chip and the first mounted chip being spaced apart, and the first wiring combination layer being electrically connected to the first mounted chip; The fan-out package structure further includes a second encapsulant made of the same encapsulation material as the first encapsulant, the main chip being exposed on the second surface, the second encapsulant being disposed on the second surface and covering the main chip.

2. The fan-out package structure according to claim 1, characterized in that, A first conductive pad is disposed on a side of the main chip close to the first surface, and the first conductive pillar is connected to the first conductive pad.

3. The fan-out package structure according to claim 1, characterized in that, A conductive layer is disposed within the first groove, the conductive layer extending to the first surface and being electrically connected to the first wiring combination layer, a second mounted chip is further disposed within the first groove, the second mounted chip being mounted on the conductive layer and electrically connected to the conductive layer, the first mounted chip being mounted back-to-back on the second mounted chip and having a third conductive pad disposed on a side away from the second mounted chip.

4. The fan-out package structure according to claim 3, characterized in that, An adhesive layer is disposed between the first mounted chip and the second mounted chip.

5. The fan-out package structure according to claim 4, characterized in that, The conductive layer extends towards two sides of the first groove and is connected to the first conductive pillar.

6. The fan-out package structure according to claim 1 or 3, characterized in that, A second groove is disposed on a surface of the second encapsulant away from the first encapsulant, a third mounted chip is disposed within the second groove, and a second wiring combination layer is further disposed on a surface of the second encapsulant away from the first encapsulant, the second wiring combination layer being electrically connected to the third mounted chip.

7. The fan-out package structure according to claim 6, characterized in that, A second conductive pillar is further disposed within the first encapsulant, two ends of the second conductive pillar respectively penetrating through to the first wiring combination layer and the second wiring combination layer, the first wiring combination layer being electrically connected to the second wiring combination layer through the second conductive pillar.

8. The fan-out package structure according to claim 1, characterized in that, The first wiring composite layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the first surface, and a first metal layer is disposed in the first dielectric layer. The first metal layer is electrically connected to the first mounted chip and the first conductive pillar. The second dielectric layer is disposed on the first dielectric layer, and a second metal layer is disposed in the second dielectric layer. The second metal layer is electrically connected to the first metal layer. The solder ball is disposed on the second metal layer.

9. A method for manufacturing a fan-out package structure for manufacturing the fan-out package structure according to any one of claims 1-8, characterized in that, the method includes: mounting a main chip on a carrier; encapsulating on the carrier to form a first encapsulant covering the main chip, the first encapsulant having opposite first and second surfaces; removing the carrier so that the main chip is exposed on the second surface; encapsulating on the second surface to form a second encapsulant covering the main chip; laser grooving on the first surface to form a first groove; mounting a first mounted chip in the first groove; forming a wiring composite layer on the first surface; planting balls on the wiring composite layer to form solder balls; wherein, the first encapsulant and the second encapsulant adopt the same encapsulation material, a first conductive pillar is further disposed in the first encapsulant, the first conductive pillar penetrates through to the main chip and is exposed on the first surface, the first wiring composite layer is electrically connected to the main chip through the first conductive pillar, the main chip and the first mounted chip are spaced apart, and the first wiring composite layer is electrically connected to the first mounted chip.

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