A configuration control circuit for P_FLASH FPGA

Abstract

The present invention discloses a configuration control circuit applied to a P_FLASH type FPGA, belonging to the field of programmable logic devices, including a word line circuit, a bit line circuit, a data reading circuit and a data comparison and verification circuit; each word line gate end in the word line circuit is horizontally connected to the gate end of each corresponding row of P_FLASH configuration units in the P_FLASH storage array; each bit line drain end in the bit line circuit is connected to the drain end of each corresponding column of P_FLASH configuration units, and each bit line source end is connected to the source end of each corresponding column of FLASH configuration units; the data reading circuit includes a specified number of data reading channels, each data reading channel corresponds to a bit line channel of a corresponding bit, and can read configuration data from the drain end of the P_FLASH configuration unit; the data comparison and verification circuit performs XOR comparison and verification on programming data and configuration data read from the P_FLASH configuration unit. The present invention can realize functions such as erasing, programming, and verification of P_FLASH storage array units, and operate each configuration stage of the P_FLASH type FPGA under various configuration instruction sets and operating voltages.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable logic devices, and in particular to a configuration control circuit applied to a P_FLASH type FPGA. Background Art

[0002] FPGA (Field Programmable Gate Array) is distinguished by its internal programmable configuration units; the current mainstream FPGA circuits mainly include three types: SRAM type, anti-fuse type and FLASH type FPGA.

[0003] The internal configurable unit of FLASH-type FPGA is the FLASH switch. FPGA based on FLASH architecture can realize multiple operations such as erasing, programming and verification, and the configuration information is non-volatile after the circuit is powered off. When the system is powered on, no external configuration memory is required to load configuration data. It has the characteristics of fast power-on startup speed and high confidentiality and security. It is widely used in many fields such as aerospace, military industry, industrial control, etc.

[0004] To configure the FLASH storage unit in the FPGA according to the P-type FLASH unit operation mechanism, it is necessary to design a corresponding configuration control circuit. Summary of the invention

[0005] The object of the present invention is to provide a configuration control circuit applied to a P_FLASH type FPGA to implement configuration operations on a FLASH storage configuration unit in the FPGA.

[0006] In order to solve the above technical problems, the present invention provides a configuration control circuit applied to a P_FLASH type FPGA, which is used to erase, program, read and verify data and over-erase a P_FLASH storage array composed of P_FLASH configuration units, characterized in that the configuration control circuit includes a word line circuit, a bit line circuit, a data reading circuit and a data comparison and verification circuit; wherein,

[0007] The gate end of each word line in the word line circuit is horizontally connected to the gate end of each corresponding row of P_FLASH configuration units in the P_FLASH storage array;

[0008] Each bit line drain end in the bit line circuit is connected to the drain end of each corresponding column of P_FLASH configuration units, and each bit line source end is connected to the source end of each corresponding column of FLASH configuration units;

[0009] The data reading circuit includes a specified number of data reading channels, each data reading channel corresponds to a bit line channel of a corresponding bit, and can read the configuration data from the drain end of the P_FLASH configuration unit;

[0010] The data comparison and verification circuit performs an XOR comparison and verification on the programming data and the configuration data read from the P_FLASH configuration unit.

[0011] Optionally, the word line circuit includes 89 horizontal word line channels, each word line channel has 32 word lines, and the word line circuit corresponding to each word line has the same structure;

[0012] The word line circuit includes NMOS tubes N0~N9 and PMOS tubes P0~P10; the drain end of NMOS tube N0, the drain end of NMOS tube N2 and the drain end of NMOS tube N8 are all connected to the word line gate end WL; the source end of NMOS tube N5, the source end of NMOS tube N7 and the source end of NMOS tube N9 are all connected to the LV1 signal; the source end of NMOS tube N0 is connected to the drain end of NMOS tube N1; the source end of NMOS tube N1 is connected to the ground GND; the source end of NMOS tube N2 is connected to the drain end of NMOS tube N3; the source end of NMOS tube N3 is connected to the drain end of NMOS tube N4; the source end of NMOS tube N4 is connected to the drain end of NMOS tube N5; the source end of NMOS tube N8 is connected to the drain end of NMOS tube N6 and the drain end of NMOS tube N9; the source end of NMOS tube N6 is connected to the drain end of NMOS tube N7;

[0013] The source ends of PMOS tube P0, PMOS tube P2, PMOS tube P6, and PMOS tube P9 are all connected to the VS_WL signal; the drain end of PMOS tube P1 and the drain end of PMOS tube P5 are all connected to the word line gate end WL; the drain end of PMOS tube P0 is connected to the source end of PMOS tube P1; the drain end of PMOS tube P2 is connected to the source end of PMOS tube P3; the drain end of PMOS tube P3 is connected to the source end of PMOS tube P4; the drain end of PMOS tube P4 is connected to the source end of PMOS tube P5; the drain end of PMOS tube P6 is connected to the source end of PMOS tube P7; the drain end of PMOS tube P7 is connected to the source end of PMOS tube P8; the drain end of PMOS tube P9 is connected to the source end of PMOS tube P10; the drain end of PMOS tube P8 and the drain end of PMOS tube P10 are connected to the source end of PMOS tube P5;

[0014] The gate terminal of NMOS tube N0 is connected to A1 signal, the gate terminal of NMOS tube N1 is connected to A2 signal, the gate terminal of NMOS tube N2 is connected to A2N signal, the gate terminal of NMOS tube N3 is connected to A1 signal, the gate terminal of NMOS tube N4 is connected to OEN signal, the gate terminal of NMOS tube N5 is connected to A3 signal, the gate terminal of NMOS tube N6 is connected to A3N signal, the gate terminal of NMOS tube N7 is connected to A2N signal, the gate terminal of NMOS tube N8 is connected to A1N signal, and the gate terminal of NMOS tube N9 is connected to OEP signal; the gate terminal of PMOS tube P0 is connected to A1N signal, the gate terminal of NMOS tube N9 is connected to OEP signal, and the gate terminal of NMOS tube P0 is connected to A1N signal. The gate end of PMOS tube P1 is connected to the A1 signal, the gate end of PMOS tube P2 is connected to the OEP signal, the gate end of PMOS tube P3 is connected to the A3N signal, the gate end of PMOS tube P4 is connected to the A1N signal, the gate end of PMOS tube P5 is connected to the A2 signal, the gate end of PMOS tube P6 is connected to the A1N signal, the gate end of PMOS tube P7 is connected to the A3N signal, the gate end of PMOS tube P8 is connected to the OEN signal, the gate end of PMOS tube P9 is connected to the A1N signal, and the gate end of PMOS tube P10 is connected to the A3 signal.

[0015] Optionally, the bit line circuit includes 10 vertical bit line channels, each bit line channel has 83 bit lines, and the bit line circuit corresponding to each bit line has the same structure;

[0016] The bit line circuit includes NMOS tubes N10-N19 and PMOS tubes P11-P14; the source end of NMOS tube N10 and the source end of NMOS tube N13 are both connected to the ground GND; the drain end of NMOS tube N10 and the drain end of NMOS tube N12 are connected to the source end of NMOS tube N11; the source end of NMOS tube N12 is connected to the LV2 signal; the drain end of NMOS tube N11 and the drain end of NMOS tube N13 are connected to the bit line drain end BL; the source end of PMOS tube P11 is connected to the VS_BL signal, and the drain end is connected to the bit line drain end BL;

[0017] The gate terminal of the NMOS tube N10 is connected to the A4 signal; the gate terminal of the NMOS tube N11 is connected to the PRG signal; the gate terminal of the NMOS tube N12 is connected to the A4N signal; the gate terminal of the NMOS tube N13 is connected to the A5 signal; the gate terminal of the PMOS tube P11 is connected to the ERA signal; the gate terminal of the NMOS tube N14 is connected to the A7N signal; the gate terminal of the NMOS tube N15 is connected to the A6 signal; the gate terminal of the NMOS tube N16 is connected to the PRG signal; the gate terminal of the NMOS tube N17 is connected to the A4 signal; the gate terminal of the NMOS tube N18 is connected to the A4N signal; the gate terminal of the NMOS tube N19 is connected to the A8 signal; the gate terminal of the PMOS tube P12 is connected to the A6 signal; the gate terminal of the PMOS tube P13 is connected to the A7 signal; the gate terminal of the PMOS tube P14 is connected to the ERA signal.

[0018] Optionally, the data reading circuit includes 83 data reading channels, and the structure of each data reading circuit is the same;

[0019] The data reading circuit includes NMOS tubes N20-N25, PMOS tubes P15-P17 and three inverter circuits; the source end of the NMOS tube N24 is connected to the ground GND, and the drain end is connected to the source end of the NMOS tube N23; the drain end of the NMOS tube N23 is connected to the source end of the NMOS tube N22; the drain end of the NMOS tube N22 is connected to the source end of the NMOS tube N21; the drain end of the NMOS tube N21 is connected to the source end of the NMOS tube N20; The drain end of the transistor N20 is connected to the drain end of the PMOS transistor P15; the source end of the PMOS transistor P15, the source end of the PMOS transistor P16 and the source end of the PMOS transistor P17 are all connected to the power supply VCCA, the gate end of the PMOS transistor P15 is connected to the gate end of the PMOS transistor P16 and is connected to the drain end of the NMOS transistor N20; the drain end of the PMOS transistor P16 and the drain end of the PMOS transistor P17 are both connected to the drain end of the NMOS transistor N25 and connected to the input end of the first inverter;

[0020] The gate end of the NMOS tube N24 and the gate end of the NMOS tube N22 are both connected to the VS_BL signal; the gate end of the NMOS tube N23 is connected to the READ_EN signal; the gate end of the NMOS tube N21 is connected to the power supply VCCA; the gate end of the NMOS tube N20 and the gate end of the NMOS tube N25 are both connected to the READ_CTRL signal; the source end of the NMOS tube N25 is connected to the bit line source end SL; the gate end of the PMOS tube P17 is connected to the program_en signal.

[0021] Optionally, the data comparison and verification circuit includes NMOS tubes N26 and N27, a PMOS tube P18 and three transmission gate circuits; the source end of the NMOS tube N27 is connected to the qn signal, and the drain end is connected to the drain end of the PMOS tube P18 and the gate end of the NMOS tube N26; the source end of the PMOS tube P18 is connected to the q signal; the source end of the NMOS tube N26 is connected to the ground GND, and the drain end is connected to the Verify_d signal.

[0022] Optionally, the gate terminal of the FLASH configuration unit is connected to the word line gate terminal WL; the drain terminal is connected to the bit line drain terminal BL, and the source terminal is connected to the bit line source terminal SL.

[0023] Optionally, during the erase operation phase, the word line circuit applies a -9.5V voltage to the gate terminal of the P_FLASH configuration unit through the word line gate terminal;

[0024] The bit line circuit applies a 7.8V voltage to the drain terminal of the P_FLASH configuration unit through the bit line drain terminal, and provides a 7.8V voltage to the source terminal of the P_FLASH configuration unit through the bit line source terminal.

[0025] Optionally, in the programming operation phase, the programming operation is performed on the selected P_FLASH configuration unit under the control of the configuration control circuit, and the word line circuit applies an 8.8V voltage to the gate terminal of the selected P_FLASH configuration unit through the word line gate terminal, and applies a -2.5V voltage to the gate terminal of the unselected P_FLASH configuration unit through the word line gate terminal;

[0026] The bit line circuit applies a -7V voltage to the drain terminal of the selected P_FLASH configuration unit, applies a -0.9V voltage to the source terminal of the selected P_FLASH configuration unit, and applies a 0V voltage to both the drain terminal and the source terminal of the unselected P_FLASH configuration unit.

[0027] Optionally, in the data reading and verification stage, the word line circuit applies a 0V voltage to the gate terminal of the selected P_FLASH configuration unit through the word line gate terminal, and applies an 8.8V voltage to the gate terminals of other unselected P_FLASH configuration units; the bit line channels are selected one by one, and the source terminal of each P_FLASH configuration unit is connected to the corresponding data reading circuit through the bit line channel to which the connected bit line source terminal belongs, and the bit line circuit applies a 0V voltage to the drain terminal of the selected P_FLASH configuration unit and a 2.5V voltage to the source terminal; the data reading circuit collects and processes the source terminal signal current of the P_FLASH configuration unit, and then verifies it through the data comparison and verification circuit.

[0028] In the configuration control circuit applied to the P_FLASH type FPGA provided by the present invention, the P_FLASH configuration unit is erased, programmed, data read and verified, and over-erased. The configuration control circuit includes a word line circuit, a bit line circuit, a data reading circuit, and a data comparison and verification circuit; each word line gate end in the word line circuit is horizontally connected to the gate end of each corresponding row of P_FLASH configuration units in the P_FLASH storage array; each bit line drain end in the bit line circuit is connected to the drain end of each corresponding column of P_FLASH configuration units, and each bit line source end is connected to the source end of each corresponding column of FLASH configuration units; the data reading circuit includes a specified number of data reading channels, each data reading channel corresponds to the bit line channel of the corresponding bit, and can read the configuration data from the drain end of the P_FLASH configuration unit; the data comparison and verification circuit performs an XOR comparison and verification on the programming data and the configuration data read from the P_FLASH configuration unit. The configuration control circuit of the present invention can realize the functions of erasing, programming, verifying, etc. of the P_FLASH storage array unit, and can realize the operation of each configuration stage of the P_FLASH type FPGA under the control of corresponding configuration instruction sets and operating voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1is a schematic diagram of the structure of a P_FLASH storage array composed of P_FLASH configuration units;

[0030] Figure 2 It is a structural schematic diagram of a word line circuit in a configuration control circuit provided by the present invention;

[0031] Figure 3 It is a structural schematic diagram of a bit line circuit in a configuration control circuit provided by the present invention;

[0032] Figure 4 It is a structural schematic diagram of a data reading circuit in a configuration control circuit provided by the present invention;

[0033] Figure 5 It is a structural schematic diagram of a data comparison and verification circuit in a configuration control circuit provided by the present invention. DETAILED DESCRIPTION

[0034] The following is a further detailed description of a configuration control circuit for a P_FLASH type FPGA proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] The present invention provides a configuration control circuit applied to a P_FLASH type FPGA, such as Figure 1 The P_FLASH storage array is composed of P_FLASH configuration units. The horizontal signal is the word line, and the vertical signals are BL and SL. The configuration control circuit includes a word line circuit, a bit line circuit, a data reading circuit, and a data comparison and verification circuit. The word line gate terminal WL output of the word line circuit is connected to the gate terminal of the P_FLASH configuration unit, the bit line drain terminal BL output of the bit line circuit is connected to the drain terminal of the P_FLASH configuration unit, and the bit line source terminal SL output of the bit line circuit is connected to the source terminal of the P_FLASH configuration unit, and the current signal input is through the NMOS tube N25 in the data reading circuit.

[0036] The word line circuit includes 89 horizontal word line channels, each word line channel has 32 word lines, each word line signal gate terminal signal WL is horizontally connected to the gate terminal of each corresponding row of P_FLASH configuration units in the FLASH storage array, and the word line circuit corresponding to each word line has the same structure.

[0037] like Figure 2As shown, the word line circuit includes NMOS tubes N0~N9 and PMOS tubes P0~P10; the drain end of NMOS tube N0, the drain end of NMOS tube N2, and the drain end of NMOS tube N8 are all connected to the word line gate end WL; the source end of NMOS tube N5, the source end of NMOS tube N7, and the source end of NMOS tube N9 are all connected to the LV1 signal; the source end of NMOS tube N0 is connected to the drain end of NMOS tube N1; the source end of NMOS tube N1 is connected to the ground GND; the source end of NMOS tube N2 is connected to the drain end of NMOS tube N3; the source end of NMOS tube N3 is connected to the drain end of NMOS tube N4; the source end of NMOS tube N4 is connected to the drain end of NMOS tube N5; the source end of NMOS tube N8 is connected to the drain end of NMOS tube N6 and the drain end of NMOS tube N9; the source end of NMOS tube N6 is connected to the drain end of NMOS tube N7;

[0038] The source ends of PMOS tube P0, PMOS tube P2, PMOS tube P6, and PMOS tube P9 are all connected to the VS_WL signal; the drain end of PMOS tube P1 and the drain end of PMOS tube P5 are all connected to the word line gate end WL; the drain end of PMOS tube P0 is connected to the source end of PMOS tube P1; the drain end of PMOS tube P2 is connected to the source end of PMOS tube P3; the drain end of PMOS tube P3 is connected to the source end of PMOS tube P4; the drain end of PMOS tube P4 is connected to the source end of PMOS tube P5; the drain end of PMOS tube P6 is connected to the source end of PMOS tube P7; the drain end of PMOS tube P7 is connected to the source end of PMOS tube P8; the drain end of PMOS tube P9 is connected to the source end of PMOS tube P10; the drain end of PMOS tube P8 and the drain end of PMOS tube P10 are connected to the source end of PMOS tube P5;

[0039] The gate terminal of NMOS tube N0 is connected to A1 signal, the gate terminal of NMOS tube N1 is connected to A2 signal, the gate terminal of NMOS tube N2 is connected to A2N signal, the gate terminal of NMOS tube N3 is connected to A1 signal, the gate terminal of NMOS tube N4 is connected to OEN signal, the gate terminal of NMOS tube N5 is connected to A3 signal, the gate terminal of NMOS tube N6 is connected to A3N signal, the gate terminal of NMOS tube N7 is connected to A2N signal, the gate terminal of NMOS tube N8 is connected to A1N signal, and the gate terminal of NMOS tube N9 is connected to OEP signal; the gate terminal of PMOS tube P0 is connected to A1N signal, the gate terminal of NMOS tube N9 is connected to OEP signal, and the gate terminal of NMOS tube P0 is connected to A1N signal. The gate end of PMOS tube P1 is connected to the A1 signal, the gate end of PMOS tube P2 is connected to the OEP signal, the gate end of PMOS tube P3 is connected to the A3N signal, the gate end of PMOS tube P4 is connected to the A1N signal, the gate end of PMOS tube P5 is connected to the A2 signal, the gate end of PMOS tube P6 is connected to the A1N signal, the gate end of PMOS tube P7 is connected to the A3N signal, the gate end of PMOS tube P8 is connected to the OEN signal, the gate end of PMOS tube P9 is connected to the A1N signal, and the gate end of PMOS tube P10 is connected to the A3 signal.

[0040] The bit line circuit includes 10 vertical bit line channels, each bit line channel has 83 bit lines, each bit line drain signal BL is connected to the drain of each corresponding column of P_FLASH configuration units, each bit line source signal SL is connected to the source of each corresponding column of P_FLASH configuration units, and the bit line circuit corresponding to each bit line has the same structure.

[0041] like Figure 3 As shown, the bit line circuit includes NMOS tubes N10~N19 and PMOS tubes P11~P14; the source end of the NMOS tube N10 and the source end of the NMOS tube N13 are both connected to the ground GND; the drain end of the NMOS tube N10 and the drain end of the NMOS tube N12 are connected to the source end of the NMOS tube N11; the source end of the NMOS tube N12 is connected to the LV2 signal; the drain end of the NMOS tube N11 and the drain end of the NMOS tube N13 are connected to the bit line drain end BL; the source end of the PMOS tube P11 is connected to the VS_BL signal, and the drain end is connected to the bit line drain end BL;

[0042] The gate terminal of the NMOS tube N10 is connected to the A4 signal; the gate terminal of the NMOS tube N11 is connected to the PRG signal; the gate terminal of the NMOS tube N12 is connected to the A4N signal; the gate terminal of the NMOS tube N13 is connected to the A5 signal; the gate terminal of the PMOS tube P11 is connected to the ERA signal; the gate terminal of the NMOS tube N14 is connected to the A7N signal; the gate terminal of the NMOS tube N15 is connected to the A6 signal; the gate terminal of the NMOS tube N16 is connected to the PRG signal; the gate terminal of the NMOS tube N17 is connected to the A4 signal; the gate terminal of the NMOS tube N18 is connected to the A4N signal; the gate terminal of the NMOS tube N19 is connected to the A8 signal; the gate terminal of the PMOS tube P12 is connected to the A6 signal; the gate terminal of the PMOS tube P13 is connected to the A7 signal; the gate terminal of the PMOS tube P14 is connected to the ERA signal.

[0043] The data reading circuit includes a specific number of data reading channels, the specific number of which is the number of bits of the 83-bit bit stream in the P_FLASH type FPGA, each data reading channel corresponds to a corresponding number of bit line channels, and the data reading circuit can read the configuration data from the drain end of the P_FLASH configuration unit. The structure of each data reading circuit is the same.

[0044] like Figure 4As shown, the data reading circuit includes NMOS tubes N20~N25, PMOS tubes P15~P17 and three inverter circuits; the source end of the NMOS tube N24 is connected to the ground GND, and the drain end is connected to the source end of the NMOS tube N23; the drain end of the NMOS tube N23 is connected to the source end of the NMOS tube N22; the drain end of the NMOS tube N22 is connected to the source end of the NMOS tube N21; the drain end of the NMOS tube N21 is connected to the source end of the NMOS tube N20; The drain end of the S transistor N20 is connected to the drain end of the PMOS transistor P15; the source end of the PMOS transistor P15, the source end of the PMOS transistor P16 and the source end of the PMOS transistor P17 are all connected to the power supply VCCA, the gate end of the PMOS transistor P15 is connected to the gate end of the PMOS transistor P16 and is connected to the drain end of the NMOS transistor N20; the drain end of the PMOS transistor P16 and the drain end of the PMOS transistor P17 are all connected to the drain end of the NMOS transistor N25 and are connected to the input end of the first inverter;

[0045] The gate end of the NMOS tube N24 and the gate end of the NMOS tube N22 are both connected to the VS_BL signal; the gate end of the NMOS tube N23 is connected to the READ_EN signal; the gate end of the NMOS tube N21 is connected to the power supply VCCA; the gate end of the NMOS tube N20 and the gate end of the NMOS tube N25 are both connected to the READ_CTRL signal; the source end of the NMOS tube N25 is connected to the bit line source end SL; the gate end of the PMOS tube P17 is connected to the program_en signal.

[0046] like Figure 5 As shown, the data comparison and verification circuit includes NMOS tubes N26 and N27, a PMOS tube P18 and three transmission gate circuits; the source end of the NMOS tube N27 is connected to the qn signal, and the drain end is connected to the drain end of the PMOS tube P18 and the gate end of the NMOS tube N26; the source end of the PMOS tube P18 is connected to the q signal; the source end of the NMOS tube N26 is connected to the ground GND, and the drain end is connected to the Verify_d signal.

[0047] joint Figure 2~Figure 5 The gate terminal of the FLASH configuration unit is connected to the word line gate terminal WL; the drain terminal is connected to the bit line drain terminal BL, and the source terminal is connected to the bit line source terminal SL.

[0048] The configuration control circuit provided by the present invention can realize the functions of erasing, programming, reading verification and over-erasing of P_FLASH storage array units. Under the control of corresponding configuration instruction sets and operating voltages, it can realize the operation of each configuration stage of P_FLASH type FPGA. The specific operation stages are described as follows.

[0049] according to Figure 2~Figure 5Configure the signal states in the control circuit and describe the different operation stages in detail. First, explain the signal states and corresponding MOS tube states in the following circuits. For example, A1=0 means that the A1 signal is at a low level, and A3=1 means that the A3 signal is at a high level. The following descriptions all use this description method. For CMOS integrated circuits, when the gate terminal signal of the PMOS tube is "0", it means that the PMOS tube is turned on, and when the gate terminal signal is "1", it means that the PMOS tube is turned off. Similarly, for the NMOS tube, when the gate terminal signal is "0", it means that the NMOS tube is turned off, and when the gate terminal signal is "1", it means that the NMOS tube is turned on.

[0050] 1. During the erase operation:

[0051] The P_FLASH type FPGA adopts the full chip selected erase mode, that is, all P_FLASH configuration cell arrays in the FPGA are fully erased through the configuration control circuit. All word line signal gate terminals WL of the word line channel apply a -9.5V voltage to the gate terminal of the P_FLASH storage unit, all bit line drain terminals BL in all bit line channels of the bit line circuit apply a 7.8V voltage to the drain terminal of the P_FLASH storage unit, and all bit line source terminals SL apply a 7.8V voltage to the source terminal of the P_FLASH storage unit.

[0052] In the word line circuit, LV1=-9.5V, A1N=OEP=1, NMOS tubes N8 and N9 are turned on, the path formed by the two NMOS tubes is turned on, and other paths are closed, and the word line output is LV1=-9.5V; in the bit line circuit, ERA=0, PMOS tubes P11 and P14 are turned on, and the bit line BL and bit line SL port outputs VS_BL=7.8V voltage.

[0053] 2. Programming operation process:

[0054] The selected P_FLASH configuration unit is programmed under the control of the configuration circuit. Through the corresponding instruction operation, a certain word line channel is first selected, and then a certain word line in the word line channel is selected. The word line circuit applies an 8.8V voltage to the gate terminal of the selected P_FLASH configuration unit through the gate terminal signal WL, and applies a -2.5V voltage to the gate terminal of the unselected word line signal; for the bit line signal, similarly, a specific bit line channel is first selected, and then the programming Bits data stream is injected into the selected bit line channel. The bit line circuit applies a -7V voltage to the bit line drain terminal signal of the selected P_FLASH configuration unit, a -0.9V voltage to the bit line source terminal, and a 0V voltage to the drain terminal and the bit line source terminal of the unselected P_FLASH configuration unit.

[0055] During the programming operation phase of the P_FLASH configuration unit, there are two states: selected and unselected. The signal states are as follows:

[0056] 1. For the selected P_FLASH configuration unit:

[0057] (1) In the word line circuit, the signal state is VS_WL=8.8V, LV1=-2.5V, A1=A2=OEP=A3N=0, PMOS tubes P2, P3, P4, and P5 are turned on, the path formed by the four PMOS tubes is turned on, and the word line gate terminal signal output is VS_WL=8.8V;

[0058] (2) In the bit line circuit, the signal state is LV2 = -7 V, LV3 = -0.9 V, PRG = A4N = 1, NMOS tubes N11, N12, N16, and N18 are turned on, the path formed by NMOS tubes N11 and N12 is turned on, and the bit line BL outputs LV2 = -7 V; the path formed by NMOS tubes N16 and N18 is turned on, and the bit line SL signal is LV3 = -0.9 V.

[0059] 2. For unselected P_FLASH configuration units, including unselected word lines and unselected bit lines, there are three specific situations:

[0060] (1) For the word line channel that is selected but the word line in the word line channel that is not selected, VS_WL = 8.8 V, LV1 = -2.5 V, A1N = OEP = 1, NMOS tubes N8 and N8 are turned on, the path formed by the two NMOS tubes is turned on, and other paths are closed, and the word line output is LV1 = -2.5 V.

[0061] (2) For the unselected word line in the word line channel, LV1=-2.5V, A2N=A3N=1, NMOS tubes N6 and N7 are turned on, the path formed by the two NMOS tubes is turned on, and other paths are closed, and the word line output is LV1=-2.5V.

[0062] (3) The word line of the P_FLASH configuration unit is selected, but the bit line BL and bit line SL are not selected. At this time, A4=PRG=1, NMOS tubes N10, N11, N16 and N17 are turned on, the channel formed by the four NMOS tubes is turned on, and the output of the bit line BL and SL ends are both GND=0V voltage.

[0063] 3. Verification operation process:

[0064] Under the control of the configuration circuit, the P_FLASH configuration unit in the FLASH type FPGA is verified. In the verification operation stage, the word line channel and word line in the circuit are traversed one by one. The bit line channel is selected in turn, and the source end of each P_FLASH configuration unit is connected to the corresponding data reading circuit through the bit line channel to which the source end signal end belongs. The data reading circuit collects and processes the leakage signal of the P_FLASH configuration unit, and then verifies it through the data comparison verification circuit.

[0065] In the verification mode, the word line circuit applies 0V voltage to the gate terminal of the selected P_FLASH configuration unit through the gate terminal signal, applies 0V voltage to the bit line BL, and applies 2.5V voltage to the SL terminal. The word line circuit applies 8.8V voltage to the gate terminal of other unselected P_FLASH configuration units, and applies 0V voltage to the bit line BL and SL terminals.

[0066] 1. For the selected P_FLASH configuration unit:

[0067] In the word line circuit, at this time LV1=0V, A1=A2N=A3=OEN=1, NMOS tubes N2~N5 are turned on, the path formed by the four NMOS tubes is turned on, and other paths are closed, and the word line output is LV1=0V.

[0068] In the bit line circuit, A5=1, A6=A7=0, NMOS tube N13 is turned on, PMOS tubes P12 and P13 are turned on. The bit line BL outputs GND=0V voltage, that is, the drain signal of the P_FLASH configuration unit is 0V, and the bit line SL outputs VCCA=2.5V voltage.

[0069] In the reading circuit, the current information read by SL is read in through the current source circuit, and the result signal Read_out is output. The data comparison and verification circuit performs XOR comparison and verification on the input signal Read_out and the programming code stream data q input at this time. After the comparison and verification, the comparison and verification result Verify_d is output to the FLASH related control circuit through the opening and closing of the NMOS tube N26, so as to determine whether the related P_FLASH configuration unit is erased and programmed correctly.

[0070] 2. For unselected P_FLASH configuration units:

[0071] In the word line circuit, at this time VS_WL=8.8V, A1N=OEN=A3N=0, PMOS tubes P6~P8 are turned on, the path formed by the three PMOS tubes is turned on, and other paths are closed, and the word line output is VS_WL=8.8V.

[0072] In the bit line circuit, A5=A6=A7N=1, NMOS tubes N13~N15 are turned on, and the bit lines BL and SL output GND=0V.

[0073] In summary, the configuration control circuit applied to P_FLASH type FPGA proposed in the present invention is a reliable and flexible design method after design and simulation verification, which provides a guarantee basis for the later design of larger-scale P_FLASH type FPGA circuits.

[0074] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A configuration control circuit applied to a P_FLASH type FPGA, used for erasing, programming, data reading verification and over-erasing a P_FLASH storage array composed of P_FLASH configuration units, characterized in that: The configuration control circuit includes a word line circuit, a bit line circuit, a data reading circuit and a data comparison and verification circuit; wherein, The gate end of each word line in the word line circuit is horizontally connected to the gate end of each corresponding row of P_FLASH configuration units in the P_FLASH storage array; Each bit line drain end in the bit line circuit is connected to the drain end of each corresponding column of P_FLASH configuration units, and each bit line source end is connected to the source end of each corresponding column of FLASH configuration units; The data reading circuit includes a specified number of data reading channels, each data reading channel corresponds to a bit line channel of a corresponding bit, and can read the configuration data from the drain end of the P_FLASH configuration unit; The data comparison and verification circuit performs an XOR comparison and verification on the programming data and the configuration data read from the P_FLASH configuration unit; The word line circuit includes 89 horizontal word line channels, each word line channel has 32 word lines, and the word line circuit corresponding to each word line has the same structure; The word line circuit includes NMOS tubes N0~N9 and PMOS tubes P0~P10; the drain end of NMOS tube N0, the drain end of NMOS tube N2 and the drain end of NMOS tube N8 are all connected to the word line gate end WL; the source end of NMOS tube N5, the source end of NMOS tube N7 and the source end of NMOS tube N9 are all connected to the LV1 signal; the source end of NMOS tube N0 is connected to the drain end of NMOS tube N1; the source end of NMOS tube N1 is connected to the ground GND; the source end of NMOS tube N2 is connected to the drain end of NMOS tube N3; the source end of NMOS tube N3 is connected to the drain end of NMOS tube N4; the source end of NMOS tube N4 is connected to the drain end of NMOS tube N5; the source end of NMOS tube N8 is connected to the drain end of NMOS tube N6 and the drain end of NMOS tube N9; the source end of NMOS tube N6 is connected to the drain end of NMOS tube N7; The source ends of PMOS tube P0, PMOS tube P2, PMOS tube P6, and PMOS tube P9 are all connected to the VS_WL signal; the drain end of PMOS tube P1 and the drain end of PMOS tube P5 are all connected to the word line gate end WL; the drain end of PMOS tube P0 is connected to the source end of PMOS tube P1; the drain end of PMOS tube P2 is connected to the source end of PMOS tube P3; the drain end of PMOS tube P3 is connected to the source end of PMOS tube P4; the drain end of PMOS tube P4 is connected to the source end of PMOS tube P5; the drain end of PMOS tube P6 is connected to the source end of PMOS tube P7; the drain end of PMOS tube P7 is connected to the source end of PMOS tube P8; the drain end of PMOS tube P9 is connected to the source end of PMOS tube P10; the drain end of PMOS tube P8 and the drain end of PMOS tube P10 are connected to the source end of PMOS tube P5; The gate terminal of NMOS tube N0 is connected to A1 signal, the gate terminal of NMOS tube N1 is connected to A2 signal, the gate terminal of NMOS tube N2 is connected to A2N signal, the gate terminal of NMOS tube N3 is connected to A1 signal, the gate terminal of NMOS tube N4 is connected to OEN signal, the gate terminal of NMOS tube N5 is connected to A3 signal, the gate terminal of NMOS tube N6 is connected to A3N signal, the gate terminal of NMOS tube N7 is connected to A2N signal, the gate terminal of NMOS tube N8 is connected to A1N signal, and the gate terminal of NMOS tube N9 is connected to OEP signal; the gate terminal of PMOS tube P0 is connected to A1N signal, the gate terminal of NMOS tube N9 is connected to OEP signal, and the gate terminal of NMOS tube P0 is connected to A1N signal. The gate terminal of the PMOS tube P1 is connected to the A1 signal, the gate terminal of the PMOS tube P2 is connected to the OEP signal, the gate terminal of the PMOS tube P3 is connected to the A3N signal, the gate terminal of the PMOS tube P4 is connected to the A1N signal, the gate terminal of the PMOS tube P5 is connected to the A2 signal, the gate terminal of the PMOS tube P6 is connected to the A1N signal, the gate terminal of the PMOS tube P7 is connected to the A3N signal, the gate terminal of the PMOS tube P8 is connected to the OEN signal, the gate terminal of the PMOS tube P9 is connected to the A1N signal, and the gate terminal of the PMOS tube P10 is connected to the A3 signal; The bit line circuit includes 10 vertical bit line channels, each bit line channel has 83 bit lines, and the bit line circuit corresponding to each bit line has the same structure; The bit line circuit includes NMOS tubes N10-N19 and PMOS tubes P11-P14; the source end of NMOS tube N10 and the source end of NMOS tube N13 are both connected to the ground GND; the drain end of NMOS tube N10 and the drain end of NMOS tube N12 are connected to the source end of NMOS tube N11; the source end of NMOS tube N12 is connected to the LV2 signal; the drain end of NMOS tube N11 and the drain end of NMOS tube N13 are connected to the bit line drain end BL; the source end of PMOS tube P11 is connected to the VS_BL signal, and the drain end is connected to the bit line drain end BL; The gate terminal of the NMOS tube N10 is connected to the A4 signal; the gate terminal of the NMOS tube N11 is connected to the PRG signal; the gate terminal of the NMOS tube N12 is connected to the A4N signal; the gate terminal of the NMOS tube N13 is connected to the A5 signal; the gate terminal of the PMOS tube P11 is connected to the ERA signal; the gate terminal of the NMOS tube N14 is connected to the A7N signal; the gate terminal of the NMOS tube N15 is connected to the A6 signal; the gate terminal of the NMOS tube N16 is connected to the PRG signal; the gate terminal of the NMOS tube N17 is connected to the A4 signal; the gate terminal of the NMOS tube N18 is connected to the A4N signal; the gate terminal of the NMOS tube N19 is connected to the A8 signal; the gate terminal of the PMOS tube P12 is connected to the A6 signal; the gate terminal of the PMOS tube P13 is connected to the A7 signal; the gate terminal of the PMOS tube P14 is connected to the ERA signal.

2. The configuration control circuit applied to a P_FLASH type FPGA as claimed in claim 1, characterized in that: The data reading circuit includes 83 data reading channels, and the structure of each data reading circuit is the same; The data reading circuit includes NMOS tubes N20-N25, PMOS tubes P15-P17 and three inverter circuits; the source end of the NMOS tube N24 is connected to the ground GND, and the drain end is connected to the source end of the NMOS tube N23; the drain end of the NMOS tube N23 is connected to the source end of the NMOS tube N22; the drain end of the NMOS tube N22 is connected to the source end of the NMOS tube N21; the drain end of the NMOS tube N21 is connected to the source end of the NMOS tube N20; The drain end of the transistor N20 is connected to the drain end of the PMOS transistor P15; the source end of the PMOS transistor P15, the source end of the PMOS transistor P16 and the source end of the PMOS transistor P17 are all connected to the power supply VCCA, the gate end of the PMOS transistor P15 is connected to the gate end of the PMOS transistor P16 and is connected to the drain end of the NMOS transistor N20; the drain end of the PMOS transistor P16 and the drain end of the PMOS transistor P17 are both connected to the drain end of the NMOS transistor N25 and connected to the input end of the first inverter; The gate end of the NMOS tube N24 and the gate end of the NMOS tube N22 are both connected to the VS_BL signal; the gate end of the NMOS tube N23 is connected to the READ_EN signal; the gate end of the NMOS tube N21 is connected to the power supply VCCA; the gate end of the NMOS tube N20 and the gate end of the NMOS tube N25 are both connected to the READ_CTRL signal; the source end of the NMOS tube N25 is connected to the bit line source end SL; the gate end of the PMOS tube P17 is connected to the program_en signal.

3. The configuration control circuit applied to a P_FLASH type FPGA as claimed in claim 2, characterized in that: The data comparison and verification circuit includes NMOS tubes N26 and N27, a PMOS tube P18 and three transmission gate circuits; the source end of the NMOS tube N27 is connected to the qn signal, and the drain end is connected to the drain end of the PMOS tube P18 and the gate end of the NMOS tube N26; the source end of the PMOS tube P18 is connected to the q signal; the source end of the NMOS tube N26 is connected to the ground GND, and the drain end is connected to the Verify_d signal.

4. The configuration control circuit applied to a P_FLASH type FPGA as claimed in claim 3, characterized in that: The gate terminal of the FLASH configuration unit is connected to the word line gate terminal WL; the drain terminal is connected to the bit line drain terminal BL; and the source terminal is connected to the bit line source terminal SL.

5. The configuration control circuit applied to a P_FLASH type FPGA as claimed in claim 4, characterized in that: During the erase operation phase, the word line circuit applies a -9.5V voltage to the gate terminal of the P_FLASH configuration unit through the word line gate terminal; The bit line circuit applies a 7.8V voltage to the drain terminal of the P_FLASH configuration unit through the bit line drain terminal, and provides a 7.8V voltage to the source terminal of the P_FLASH configuration unit through the bit line source terminal.

6. The configuration control circuit applied to a P_FLASH type FPGA as claimed in claim 5, characterized in that: In the programming operation phase, the selected P_FLASH configuration unit is programmed under the control of the configuration control circuit, and the word line circuit applies an 8.8V voltage to the gate terminal of the selected P_FLASH configuration unit through the word line gate terminal, and applies a -2.5V voltage to the gate terminal of the unselected P_FLASH configuration unit through the word line gate terminal; The bit line circuit applies a -7V voltage to the drain terminal of the selected P_FLASH configuration unit, applies a -0.9V voltage to the source terminal of the selected P_FLASH configuration unit, and applies a 0V voltage to both the drain terminal and the source terminal of the unselected P_FLASH configuration unit.

7. The configuration control circuit applied to a P_FLASH type FPGA as claimed in claim 6, characterized in that: In the data reading and verification stage, the word line circuit applies a 0V voltage to the gate terminal of the selected P_FLASH configuration unit through the word line gate terminal, and applies an 8.8V voltage to the gate terminals of other unselected P_FLASH configuration units; the bit line channels are selected one by one, and the source terminal of each P_FLASH configuration unit is connected to the corresponding data reading circuit through the bit line channel to which the connected bit line source terminal belongs, and the bit line circuit applies a 0V voltage to the drain terminal of the selected P_FLASH configuration unit and a 2.5V voltage to the source terminal; the data reading circuit collects and processes the source terminal signal current of the P_FLASH configuration unit, and then verifies it through the data comparison and verification circuit.

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