Terminal structure, method of fabrication, and power device

Abstract

The application provides a terminal structure, a manufacturing method and a power device, which comprise: a first epitaxial layer; a buried layer located on one side of the first epitaxial layer; a first doped region penetrating through the buried layer, the first doped region being opposite to the doping type of the buried layer; a second epitaxial layer located on the side of the buried layer away from the first epitaxial layer, the second epitaxial layer having a main junction expansion region and a field limiting ring; an oxide layer located on the side of the second epitaxial layer away from the buried layer; wherein the second epitaxial layer and the first epitaxial layer are opposite to the doping type of the buried layer; in a first direction, the field limiting ring is located between the main junction expansion region and the first doped region, and the first direction is perpendicular to the direction of the first epitaxial layer pointing to the second epitaxial layer. The terminal structure, the manufacturing method and the power device provided by the technical scheme improve the withstand voltage capacity of the terminal structure and further improve the reliability and stability of the power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, more particularly, to a terminal structure, a manufacturing method and a power device. BACKGROUND

[0002] Silicon carbide (SiC) as a wide band gap semiconductor material developed rapidly in recent decades, compared with other semiconductor materials, silicon carbide material has the advantages of wide band gap, high thermal conductivity, high carrier saturation mobility, high power density and so on. Since the 1990s, silicon carbide power devices have been widely used in switching power supply, high frequency heating, automotive electronics and power amplifier.

[0003] At present, in the design and preparation process of silicon carbide power devices, especially high-voltage power devices, the terminal structure of the power device has the problems of sensitivity to the concentration of JTE and interface charge, low breakdown voltage and poor withstand voltage, which affects the reliability and stability of the power device. Therefore, designing a more reliable and efficient power device terminal structure has become one of the problems to be solved by the technical personnel in the field. SUMMARY

[0004] Therefore, the present application provides a terminal structure, a manufacturing method and a power device, which improves the withstand voltage of the terminal structure and further improves the reliability and stability of the power device.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0006] The first aspect of the present application provides a terminal structure, which comprises:

[0007] A first epitaxial layer;

[0008] A buried layer located on one side of the first epitaxial layer;

[0009] A first doped region penetrating the buried layer, the doped type of the first doped region being opposite to that of the buried layer;

[0010] A second epitaxial layer located on the side of the buried layer away from the first epitaxial layer, the second epitaxial layer having a main junction expansion region and a field limiting ring therein;

[0011] An oxide layer located on the side of the second epitaxial layer away from the buried layer;

[0012] Wherein, the doped type of the second epitaxial layer and the first epitaxial layer is opposite to that of the buried layer; in the first direction, the field limiting ring is located between the main junction expansion region and the first doped region, and the first direction is perpendicular to the direction of the first epitaxial layer pointing to the second epitaxial layer.

[0013] Optionally, the side surface of the oxide layer away from the buried layer has a first recess, the first recess extending into the second epitaxial layer, and the first recess is used as an ion implantation window for the first doped region.

[0014] Optionally, the terminal structure comprises a first protective layer at the bottom of the first recess, and the first protective layer is spaced apart from the first doped region.

[0015] Optionally, the terminal structure comprises a second doped region and a third doped region penetrating through the buried layer, and the second doped region and the third doped region are both located between the field limiting ring and the first doped region; wherein the second doped region is opposite to the doping type of the buried layer, the third doped region is the same as the doping type of the buried layer, and the doping concentration of the third doped region is greater than the doping concentration of the buried layer.

[0016] Optionally, the side surface of the oxide layer away from the buried layer has a second recess, the second recess extending into the second epitaxial layer, and the second recess is used as an ion implantation window for the second doped region and the third doped region.

[0017] Optionally, a second protective layer is located at the bottom of the second recess, wherein the second doped region is spaced apart from the second protective layer, and the third doped region is in contact with the second protective layer.

[0018] Optionally, there are a plurality of third doped regions arranged at intervals in the first direction.

[0019] Optionally, the intervals between adjacent second recesses are equal, and the widths of the second recesses gradually decrease in the direction from the main junction expansion region to the field limiting ring; or,

[0020] the widths of the second recesses are equal, and the intervals between adjacent second recesses gradually increase in the direction from the main junction expansion region to the field limiting ring.

[0021] Optionally, there are a plurality of field limiting rings arranged at intervals in the first direction.

[0022] Optionally, the intervals between adjacent field limiting rings are equal, and the widths of the field limiting rings gradually decrease in the direction from the main junction expansion region to the field limiting ring; or,

[0023] the widths of the field limiting rings are equal, and the intervals between adjacent field limiting rings gradually increase in the direction from the main junction expansion region to the field limiting ring.

[0024] The second aspect of the present application provides a power device, which comprises:

[0025] The terminal structure as described in any of the preceding paragraphs of the first aspect;

[0026] A device cell region located on the side of the main junction expansion region away from the field limiting ring.

[0027] The third aspect of the present application provides a manufacturing method, which comprises:

[0028] An epitaxial wafer is provided, which comprises: a first epitaxial layer; a buried layer located on one side of the first epitaxial layer; a second epitaxial layer located on a side of the buried layer away from the first epitaxial layer; wherein the second epitaxial layer and the first epitaxial layer are opposite to the doping type of the buried layer;

[0029] An oxide layer is formed on a side surface of the second epitaxial layer away from the buried layer;

[0030] A main junction expansion region and a field limiting ring are formed in the second epitaxial layer;

[0031] A first doped region penetrating the buried layer is formed, and the first doped region is opposite to the doping type of the buried layer; wherein, in a first direction, the field limiting ring is located between the main junction expansion region and the first doped region, and the first direction is perpendicular to the direction of the first epitaxial layer pointing to the second epitaxial layer.

[0032] Optionally, the method for forming the first doped region comprises:

[0033] A first recess is formed on a side surface of the oxide layer away from the buried layer;

[0034] Based on the first recess, ion implantation is performed to form the first doped region.

[0035] Optionally, the method further comprises:

[0036] A second recess is formed at the same time as the first recess;

[0037] At the same time as forming the first doped region, based on the second recess, ion implantation is performed to form a second doped region penetrating the buried layer;

[0038] After forming the second doped region, based on the second recess, ion implantation is performed to form a third doped region penetrating the buried layer;

[0039] Wherein, the second doped region and the third doped region are both located between the field limiting ring and the first doped region.

[0040] As can be seen from the above description, the terminal structure, the manufacturing method and the power device provided by the technical scheme of the present application distribute the high electric field alleviation of the main junction expansion region to the middle region of the entire terminal, i.e. the field limiting ring region, or the field limiting ring region and the third doped region, through the buried layer, so that multiple regions jointly share the energy of avalanche breakdown, thereby improving the avalanche resistance of the terminal structure, improving the withstand voltage capability of the terminal structure, and further improving the reliability and stability of the power device. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on the provided drawings also fall within the scope of protection of the present application.

[0042] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the present specification, to be understood and read by those skilled in the art, and do not define the limiting conditions for the implementation of the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0043] Figure 1 A cross-sectional schematic view of a conventional junction terminal extension structure provided by an embodiment of the present application;

[0044] Figure 2 A cross-sectional schematic view of a conventional field limiting ring terminal structure provided by an embodiment of the present application;

[0045] Figure 3 A cross-sectional schematic view of a terminal structure provided by an embodiment of the present application;

[0046] Figure 4 A cross-sectional schematic view of another terminal structure provided by an embodiment of the present application;

[0047] Figure 5 A top view of a power device provided by an embodiment of the present application;

[0048] Figures 6-11 A cross-sectional flowchart of a manufacturing method provided by an embodiment of the present application;

[0049] Figures 12-16 A cross-sectional flowchart of another manufacturing method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments in the present application will be described in detail below with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort fall within the scope of protection of the present application.

[0051] Currently, in the design and fabrication of power devices such as silicon carbide (SiC), especially high-voltage power devices, good termination structures are required to reduce the junction edge electric field and improve the actual breakdown voltage capability of the devices. These structures include field plates (FP), field limiting rings (FLR), and junction extensions (JTE). The field limiting rings (FLR) and junction extensions (JTE) are the most widely used structures in existing SiC power device architectures.

[0052] like Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of a conventional junction termination extension structure provided in an embodiment of this application. The junction termination extension structure includes:

[0053] Substrate 104, epitaxial layer 18 located on one side of substrate 104, oxide layer 7 located on the side of epitaxial layer 18 away from substrate 104, main junction extension region 2 located in epitaxial layer 18, and junction termination extension region 19 located in epitaxial layer 18 and on the side of main junction extension region 2, and oxide layer 7 located on the surface of epitaxial layer 18 away from substrate 104.

[0054] In this terminal structure, the junction terminal extension region 19 has a figure of merit concentration. The breakdown voltage of the device terminal is sensitive to the figure of merit concentration of the junction terminal extension region 19, so the design window is small. Furthermore, this terminal structure is very sensitive to surface charge and is easily affected by interface instability and oxide layer 7 charge, which can affect the surface electric field distribution of the device and thus affect the breakdown voltage and reliability of the device. At the same time, the manufacturing process of this terminal structure is relatively complex and is not conducive to large-scale production.

[0055] In addition, such as Figure 2 As shown, Figure 2 A cross-sectional schematic diagram of a conventional field limiting ring structure provided in an embodiment of this application. The field limiting ring structure includes:

[0056] Substrate 104, epitaxial layer 18 located on one side of substrate 104, oxide layer 7 located on the side of epitaxial layer 18 away from substrate 104, main junction extension region 2 located in epitaxial layer 18, and field confinement ring 3 located in epitaxial layer 18 and on the side of main junction extension region 2, and oxide layer 7 located on the surface of epitaxial layer 18 away from substrate 104.

[0057] In this terminal structure, due to the high surface electric field of devices such as silicon carbide, it is necessary to reduce the peak surface electric field during device design to improve the breakdown voltage, requiring the design of a large number of field limiting rings 3. In the design, many factors such as the number of rings, ring width, and ring spacing will affect the surface electric field distribution. Furthermore, the terminal structure of multiple field limiting rings 3 occupies a large chip area, which is not conducive to improving current. Moreover, this terminal structure is also very sensitive to surface charge, and the surface electric field distribution of the device is easily affected by interface instability and oxide layer charge, which in turn affects the breakdown voltage and reliability of the device.

[0058] The technical scheme of the present application provides a terminal structure, a manufacturing method and a power device, and improves the withstand voltage capability of the terminal structure, and further improves the reliability and stability of the power device.

[0059] In order to make the above objectives, characteristics and advantages of the present application more apparent, comprehensible and easier to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0060] Reference Figure 3 , Figure 3 A cross-sectional schematic diagram of a terminal structure provided by an embodiment of the present application is shown in FIG. 1. The terminal structure comprises:

[0061] A first epitaxial layer 101, a buried layer 102 located on one side of the first epitaxial layer 101, a first doped region 4 penetrating through the buried layer 102, the first doped region 4 being opposite to the doped type of the buried layer 102, a second epitaxial layer 103 located on the side of the buried layer 102 away from the first epitaxial layer 101, the second epitaxial layer 103 having a main junction expansion region 2 and a field limiting ring 3 therein, and an oxide layer 7 located on the side of the second epitaxial layer 103 away from the buried layer 102.

[0062] In the terminal structure, the second epitaxial layer 103 and the first epitaxial layer 101 are opposite to the doped type of the buried layer 102; in a first direction, the field limiting ring 3 is located between the main junction expansion region 2 and the first doped region 4, and the first direction is perpendicular to the direction of the first epitaxial layer 101 pointing to the second epitaxial layer 103.

[0063] In addition, the main junction expansion region 2 and the field limiting ring 3 have the same doped type, and are opposite to the doped type of the second epitaxial layer 103, that is, the doped type of the main junction expansion region 2 and the field limiting ring 3 is the same as the doped type of the buried layer 102, and in addition, the main junction expansion region 2 and the field limiting ring 3 are both heavily doped, and in general, the doped concentration of the main junction expansion region 2 and the field limiting ring 3 is greater than the doped concentration of the buried layer 102. For example, when the first epitaxial layer 101 and the second epitaxial layer 103 are N-type doped, the buried layer 102 is P-type doped, the first doped region 4 is N-type doped, and the N-type doped concentration of the first doped region 4 is greater than the P-type doped concentration of the buried layer 102, and the main junction expansion region 2 and the field limiting ring 3 are both P-type heavily doped. The main junction expansion region plays a role of smoothly transitioning the electric field from the device cell region in the power device to the terminal structure.

[0064] It should be noted that in the present application, the same doped type means that the doped types of two or more objects are both N-type doped or both P-type doped, and the doped concentrations are the same or different; correspondingly, the different doped types mean that the doped types of two or more objects are at least one N-type doped and at least one P-type doped, and the corresponding doped concentrations can be the same or different.

[0065] In the present application, the first epitaxial layer 101, the buried layer 102 and the second epitaxial layer 103 are one or more of Si, SiC and Ga2O3.

[0066] It should be noted that in the present application, the doping concentration is not limited by default to the ordinary doping concentration, which is between the light doping concentration and the heavy doping concentration. For example, the N-type doping is between the N-type light doping and the N-type heavy doping. The following description of the doping concentration is also used, which will not be repeated here.

[0067] In the terminal structure, due to the presence of the buried layer 102, a leakage channel along the buried layer 102 is formed, which affects the reliability of the device. Therefore, the first doped region 4 is used to cut off the electric field in the terminal structure to prevent leakage and affect other components. At the same time, the first doped region 4 can terminate the inversion layer formed on the surface of the device due to various reasons, reduce the influence of surface contamination on the breakdown voltage, and further improve the reliability of the device. In addition, the terminal structure distributes the high field relaxation of the main junction extension region 2 to the field limiting ring 3 through the buried layer 102, that is, the field limiting ring 3 acts as a voltage divider, thereby improving the withstand voltage capability of the terminal structure and improving the reliability and stability of the device.

[0068] Optionally, the side surface of the oxide layer 7 away from the buried layer 102 has a first recess 11, and the first recess 11 extends into the second epitaxial layer 103. The first recess 11 is used as an ion implantation window for the first doped region 4. It should be noted that the depth of the first recess 11 can be set based on requirements, and the bottom thereof can extend into the second epitaxial layer 103, or be located in the oxide layer 7, or be located at the interface position of the oxide layer 7 and the second epitaxial layer 103, all of which are within the protection scope of the present application. Correspondingly, in the actual process, the first recess 11 can be formed by modifying the existing process design, without the need to increase the process steps. In addition, when forming the first doped region 4, a patterned photoresist can be used as an ion implantation window, without the need to form the first recess 11.

[0069] Preferably, the terminal structure includes a first protective layer 13 located at the bottom of the first groove 11, with a spacing between the first protective layer 13 and the first doped region 4. Additionally, ion implantation can be performed based on the first groove 11 to form 13 below its bottom. The doping type of the first protective layer 13 is opposite to that of the first doped region 4, but the same as that of the field confinement ring 3 and the main junction extension region 2, and its doping concentration is lower than that of the field confinement ring 3 and the main junction extension region 2. For example, when both the field confinement ring 3 and the main junction extension region 2 are heavily P-type doped, the first protective layer 13 is either P-type doped or lightly P-type doped; generally, the first protective layer 13 is lightly P-type doped. The first protective layer 13 reduces the influence of charge in the oxide layer 7 on the terminal structure, while also reducing the possibility of surface breakdown, thus improving the reliability and stability of the device.

[0070] In addition, such as Figure 4 As shown, Figure 4 This is a cross-sectional schematic diagram of another terminal structure provided in an embodiment of this application. Figure 3 Based on the terminal structure shown, the terminal structure also includes:

[0071] The second doped region 5 and the third doped region 6 penetrate the buried layer 102, both located between the field confinement ring 3 and the first doped region 4. The second doped region 5 has the opposite doping type to the buried layer 102, while the third doped region 6 has the same doping type, and its doping concentration is greater than that of the buried layer 102. Furthermore, generally, the doping concentration of the second doped region 5 is greater than that of the buried layer 102. For example, when the buried layer 102 is P-type doped, the second doped region 5 is heavily N-type doped, and the third doped region 6 is heavily P-type doped.

[0072] The terminal structure uses the buried layer 102 to distribute the high electric field of the main junction extension region 2 in a gentle manner throughout the middle region of the terminal, namely the field limiting ring 3 and the third doped region 6. This allows multiple regions to share the energy of avalanche breakdown, thereby improving the avalanche tolerance of the terminal structure, increasing the breakdown voltage of the device, improving the withstand voltage capability of the terminal structure, and further improving the reliability and stability of the power device.

[0073] Optionally, the side surface of the oxide layer 7 away from the buried layer 102 has a second groove 12 extending into the second epitaxial layer 103, and the second groove 12 is used as an ion implantation window for the second doped region 5 and the third doped region 6. Similar to the first groove 11, the depth of the second groove 12 can be set based on requirements, and the bottom of the second groove 12 can extend into the second epitaxial layer 103, or be located in the oxide layer 7, or be located at the interface between the oxide layer 7 and the second epitaxial layer 103, all of which are within the protection scope of the present application. Similarly, in actual processes, the second groove 12 can be formed by modifying the existing process design, without the need to add process steps. Generally, the second groove 12 can be formed at the same time as the first groove 11. In addition, when forming the second doped region 5 or the third doped region 6, a patterned photoresist can be used as an ion implantation window, without the need to form the second groove 12.

[0074] In addition, the width of the second groove 12 is smaller than the width of the first groove 11, which is beneficial to reducing the area of the terminal structure. The width of the first groove 11 is relatively large, which is used to ensure better cutoff field effect. Generally, the width of the first groove 11 is greater than 5 μm.

[0075] It should be noted that in actual processes, the main junction expansion region 2 cannot reach the ideal state, and there is a curved area at the etching edge, which affects the breakdown voltage of the device. The first groove 11 and the second groove 12 can reduce the ion concentration in the second epitaxial layer 103, weaken the electric field intensity of the curved area of the main junction expansion region 2, and thus improve the breakdown voltage. In addition, the first groove 11 and the second groove 12 can also effectively improve the area utilization rate of the terminal structure, reduce the area of the voltage division region, and thus reduce the chip area of the terminal structure. In the same area of the silicon wafer, more devices can be produced, and the chip cost is reduced. However, in actual processes, due to process or design requirements, the first groove 11 and the second groove 12 can be selected not to be formed.

[0076] In addition, the shape of the first groove 11 or the second groove 12 can be rectangular, trapezoidal, or U-shaped.

[0077] Preferably, the second protective layer 14 is located at the bottom of the second groove 12, wherein the second doped region 5 is spaced apart from the second protective layer 14, and the third doped region 6 is in contact with the second protective layer 14. Similar to the first protective layer 13, the doping type of the second protective layer 14 is opposite to that of the second doped region 5, is the same as that of the third doped region 6, and has a doping concentration lower than that of the third doped region 6. For example, when the second doped region 5 is N-type doped, the third doped region 6 is P-type doped, and the second protective layer 14 is P-type lightly doped. The second protective layer 14 is located between the second groove 12 and the third doped region 6 and is in contact with the third doped region 6, thereby reducing the influence of the charges in the oxide layer 7 on the third doped region 6, reducing the effect of surface breakdown, improving the voltage division effect of the third doped region 6, improving the breakdown voltage of the device, and improving the reliability and stability of the device.

[0078] Optionally, the terminal structure has a plurality of third doped regions 6 arranged at intervals in the first direction. The plurality of third doped regions 6 can better divide the voltage, reduce the energy of each third doped region 6 to share the avalanche breakdown of the device, further improve the breakdown voltage of the device, and improve the voltage resistance of the device.

[0079] Optionally, in the first mode, the intervals between adjacent second grooves 12 are equal, and the widths of the second grooves 12 gradually decrease in the direction from the main junction expansion region 2 to the field limiting ring 3; or,

[0080] In the second mode, the widths of the second grooves 12 are equal, and the intervals between adjacent second grooves 12 gradually increase in the direction from the main junction expansion region 2 to the field limiting ring 3.

[0081] It should be noted that in the present application, one second groove 12 and the corresponding second doped region 5 and third doped region 6 form a trench ring. That is, in the first mode, the intervals between adjacent trench rings are equal, and the widths of the trench rings gradually decrease in the direction from the main junction expansion region 2 to the field limiting ring 3; in the second mode, the widths of the trench rings are equal, and the intervals between adjacent trench rings gradually increase in the direction from the main junction expansion region 2 to the field limiting ring 3.

[0082] Both the above two modes can optimize the electric field distribution in the terminal structure, reduce the sensitivity of the terminal structure to the charge dose, and improve the reliability and stability of the power device. It should be noted that in actual processes, appropriate modes can be selected according to actual needs. In addition, the widths of the trench rings and the intervals therebetween can be flexibly set according to different specifications of the device, and the present application does not limit this.

[0083] Optionally, the terminal structure in the present application has a plurality of field limiting rings 3 arranged at intervals in the first direction. The plurality of field limiting rings 3 can better divide the voltage, reduce the energy of the device avalanche breakdown borne by each field limiting ring 3, further improve the breakdown voltage of the device, and improve the voltage resistance of the device.

[0084] Optionally, in the first form, the adjacent field limiting rings 3 have equal intervals, and the width of the field limiting ring 3 gradually decreases in the direction of the main junction expansion region 2 pointing to the field limiting ring 3; or,

[0085] In the second form, the width of the field limiting ring 3 is equal, and the interval between the adjacent field limiting rings 3 gradually increases in the direction of the main junction expansion region 2 pointing to the field limiting ring 3.

[0086] Both the above two forms can optimize the electric field distribution in the terminal structure, reduce the sensitivity of the terminal structure to the charge dose, and improve the reliability and stability of the power device. It should be noted that in the actual process, appropriate forms can be selected according to actual needs. In addition, the width of the field limiting ring 3 and the interval between them can be flexibly set according to different specifications of the device, and the present application does not limit them.

[0087] It should be noted that in the present application, due to the limitation of drawing, the width change of the field limiting ring 3 or the trench ring is not shown in the drawing, and the change of the interval between the field limiting rings 3 or the trench rings is also not shown, but this does not mean that the present application does not include the above changes.

[0088] Based on the above terminal structure, the present application also provides a power device, and the power device described below can be mutually corresponding to the terminal structure described above. Reference Figure 5 , Figure 5 is a top view structure diagram of a power device provided by the present application. The power device comprises:

[0089] any of the above terminal structures, and the device cell region 9 located on the side of the main junction expansion region 2 away from the field limiting ring 3.

[0090] As shown in Figure 5 , the center of the entire power device is the device cell region 9, the area surrounding the device cell region 9 is the main junction expansion region 2, the area surrounding the main junction expansion region 2 is the field limiting ring region 20, the field limiting ring region 20 comprises the above-mentioned field limiting ring 3, the area surrounding the field limiting ring region 20 is the trench ring region 21, the trench ring region 21 comprises the above-mentioned second groove 12, second doped region 5 and third doped region 6, and the area surrounding the trench ring region 21 is the electric field cutoff region 22, which comprises the above-mentioned first groove 11 and first doped region 4. In addition, there is a scribe line 10 between adjacent power devices, which is used to divide the silicon wafer to form a single power device.

[0091] It should be noted that the aforementioned power devices include, but are not limited to, PIN, SBD, MOSFET, IGBT, or GTO. Furthermore, the wafer materials used to fabricate these power devices include, but are not limited to, silicon, silicon carbide, gallium arsenide, aluminum nitride, gallium nitride, gallium oxide, or diamond.

[0092] The power device provided in this application has a high breakdown voltage, thus exhibiting good withstand voltage capability, as well as good reliability and stability.

[0093] Based on the above embodiments, this application also provides a manufacturing method, which can be referred to in conjunction with the terminal structure and power device described above. Reference Figures 6-11 , Figures 6-11 A cross-sectional flowchart illustrating a manufacturing method provided in an embodiment of this application. The manufacturing method includes:

[0094] Step S101: As Figure 6 As shown, an epitaxial wafer 1 is provided, comprising: a first epitaxial layer 101; a buried layer 102 located on one side of the first epitaxial layer 101; and a second epitaxial layer 103 located on the side of the buried layer 102 opposite to the first epitaxial layer 101; wherein the doping type of the second epitaxial layer 103 and the first epitaxial layer 101 is opposite to that of the buried layer 102. For example, when the buried layer 102 is P-type doped, the first epitaxial layer 101 and the second epitaxial layer 103 are both N-type doped.

[0095] In addition, the epitaxial wafer 1 also includes a substrate 104 located on the first epitaxial layer 101 away from the buried layer 102, which is used to support and improve the thin film properties. Optionally, the doping type of the substrate 104 is the same as that of the first epitaxial layer 101. It should be noted that the epitaxial layer can be obtained directly through custom procurement or can be fabricated based on a deposition process.

[0096] Step S102: An oxide layer 7 is formed on the surface of the second epitaxial layer 103 facing away from the buried layer 102. This oxide layer 7 serves to protect and isolate moisture. Especially during ion implantation, the oxide layer 7 withstands ion bombardment, protecting the film from damage and reducing or even eliminating film damage associated with ion implantation.

[0097] It should be noted that the photoresist can also be used as a protective layer to replace the oxide layer 7 to reduce the damage to the film layer caused by ion implantation. However, when the terminal structure of the SiC power device (i.e., the second epitaxial layer 103 is SiC) is manufactured, the Al ions are implanted to form the main junction extension region 2 and the field limiting ring 3. Since the relative atomic mass of Al is large, the photoresist cannot block ion bombardment. Therefore, when the Al ions are implanted, the film layer structure 8 needs to be used as a mask layer for ion implantation. The film layer structure 8 can be a single thick oxide dielectric layer or a multilayer structure. Generally, the thickness of the oxide dielectric layer is 100 nm to 10 μm.

[0098] As shown in Figure 7 The film layer structure 8 includes three layers, namely the first oxide layer 81 located on the surface of the second epitaxial layer 103 away from the buried layer 102, the polysilicon layer 82 located on the surface of the first oxide layer 81 away from the second epitaxial layer 103, and the second oxide layer 83 located on the surface of the polysilicon layer 82 away from the first oxide layer 81. Among them, the thickness of the first oxide layer is 50-500 nm, the thickness of the polysilicon layer is 100-2000 nm, and the thickness of the second oxide layer is 50-500 nm. Generally, the thickness of the first oxide layer is less than the thickness of the second oxide layer.

[0099] Step S103: Forming the main junction extension region 2 and the field limiting ring 3 in the second epitaxial layer 103. The method for forming the main junction extension region 2 and the field limiting ring 3 is as follows:

[0100] Step S103.1: Etching the oxide layer 7 to form an ion implantation window based on a photolithography process. Based on the patterned Mask 17, the oxide layer 7 is subjected to a photolithography process, a development process, and the like to obtain an oxide layer 7 with an ion implantation window. Among them, the ion implantation window corresponding to the main junction extension region 2 and the ion implantation window corresponding to the field limiting ring 3 can be formed together.

[0101] Step S103.2: Ion implantation based on the ion implantation window to form the main junction extension region 2 and the field limiting ring 3.

[0102] It should be noted that when the implanted ions are Al ions, the ion implantation is performed based on the above-mentioned film layer structure 8, as shown in Figure 8As shown, after photoetching development, the second oxide layer 83 is etched using a gas with a good selectivity to the oxide layer and the polysilicon layer 82, such as CF4, CHF3, etc.; then the polysilicon layer 82 is etched using a gas with a good selectivity to the polysilicon layer 82, such as HBr, etc. Since a certain over-etching will occur during the etching, the first oxide layer 81 is relatively thin at this time, and then the relatively thin first oxide layer 81 is used as a mask layer for ion implantation to form the main junction extension region 2 and the field limiting ring 3, so that the ion implantation distribution is better, and the channel effect is effectively avoided. In addition, after the ion implantation is completed, the film structure 8 is removed by using a wet etching process.

[0103] It should be noted that the first oxide layer 81 with a relatively thin thickness is not shown in the drawings in this application, but actually exists in the terminal structure.

[0104] Step S104: referring to Figures 9-10 , a first doped region 4 penetrating the buried layer 102 is formed, and the first doped region 4 is opposite in doping type to the buried layer 102; wherein, in a first direction, the field limiting ring 3 is located between the main junction extension region 2 and the first doped region 4, and the first direction is perpendicular to the direction of the first epitaxial layer 101 pointing to the second epitaxial layer 103.

[0105] Based on the above, the method for forming the first doped region 4 includes:

[0106] Step S104.1: as shown in Figure 9 , a first recess 11 is formed on the side surface of the oxide layer 7 away from the buried layer 102. The first recess 11 is formed based on a photoetching process. The first recess 11 extends into the second epitaxial layer 103, and is used as an ion implantation window for the first doped region 4.

[0107] Step S104.2: as shown in Figure 10 , based on the first recess 11, ion implantation is performed to form the first doped region 4. The first doped region 4 is opposite in doping type to the buried layer 102, and has a doping concentration greater than that of the buried layer 102, thereby playing a role of cutting off the buried layer 102.

[0108] In addition, referring to Figure 10 , the manufacturing method can also perform ion implantation based on the first recess 11 to form a first protective layer 13. The first protective layer 13 is located at the bottom of the first recess 11, and the first protective layer 13 has a spacing with the first doped region 4. The first protective layer 13 is the same in doping type as the buried layer 102, and is used to reduce the influence of interface charges on the device.

[0109] Step S105: as Figure 11As shown, a high-dielectric-constant dielectric material is filled into the first groove 11 to form a flat film. The first groove 11 is filled with a dielectric material deposited using a CVD process. This dielectric material is SiO2 or SiN. x , Al2O3, AlN, HfO2, MgO, Sc2O3, Ga2O3, AlHFO x One or any combination of HFSiON materials.

[0110] Step S106: A cathode 16 is formed on the surface of the substrate 104 opposite to the first epitaxial layer 101, and an anode 15 is formed on the side of the main junction extension region 2 opposite to the buried layer 102, wherein the anode 15 is in contact with the main junction extension region 2, forming as shown in the figure. Figure 3 The terminal structure is shown. Additionally, the anode 15 is typically made of metal.

[0111] refer to Figures 12-16 , Figures 12-16 A cross-sectional flowchart illustrating another manufacturing method provided in an embodiment of this application. This application also provides another manufacturing method, which, based on the above-described manufacturing method, further includes:

[0112] Step S107, which follows step S104 above, is as follows:

[0113] A second doped region 5 and a third doped region 6 are formed that penetrate the buried layer 102. Both the second doped region 5 and the third doped region 6 are located between the field confinement ring 3 and the first doped region 4. The doping type of the second doped region 5 is opposite to that of the buried layer 102, while the doping type of the third doped region 6 is the same as that of the buried layer 102. The doping concentration of the third doped region 6 is greater than that of the buried layer 102.

[0114] In addition, the methods for forming the second doped region 5 and the third doped region 6 include:

[0115] Step S107.1: As Figure 13 As shown, a second groove 12 is formed on the surface of the oxide layer 7 facing away from the buried layer 102. Similarly, the second groove 12 is formed using a photolithography process, extending into the second epitaxial layer 103, and serves as an ion implantation window for the second doped region 5 and the third doped region 6. It should be noted that the depths of the first groove 11 and the second groove 12 can be the same; therefore, the second groove 12 can be formed simultaneously with the formation of the first groove 11.

[0116] Step S107.2: As Figure 14 As shown, ion implantation is performed based on the second groove 12 to form a second doped region 5 that penetrates the buried layer 102. The doping type of the second doped region 5 is opposite to that of the buried layer 102, and the doping concentration is greater than that of the buried layer 102.

[0117] In addition, referring to Figure 14 , ion implantation is performed based on the second groove 12 to form a second protective layer 14 located at the bottom of the second groove 12, and the second protective layer 14 has a spacing with the second doped region 5. The doping type of the second protective layer 14 is the same as that of the buried layer 102, which is used to reduce the influence of the interface charge on the device.

[0118] It should be noted that the doping type of the second doped region 5 is the same as that of the first doped region 4, and both are greater than the doping concentration of the buried layer 102, so that while the first doped region 4 is formed, ion implantation is performed based on the second groove 12 to form the second doped region 5 penetrating through the buried layer 102. Correspondingly, while the first protective layer 13 is formed, the second protective layer 14 is formed.

[0119] Step S107.3: After the second doped region 5 is formed, ion implantation is performed based on the second groove 12 to form a third doped region 6 penetrating through the buried layer 102, wherein the second doped region 5 and the third doped region 6 are both located between the field limiting ring 3 and the first doped region 4.

[0120] As shown in Figure 15 , the second groove 12 on the left side of the dashed line is a first window, and the second groove 12 on the right side of the dashed line is a second window. Ion implantation is performed based on the second window to form the third doped region 6, wherein the third doped region 6 is in contact with the second protective layer 14 described above.

[0121] In addition, in the manufacturing method, after the second doped region 5 and the third doped region 6 are formed, step S105 is also performed, and the second groove 12 is filled at the same time as the first groove 11 is filled (as shown in Figure 16 ); then step S106 is performed to form the terminal structure as shown in Figure 4 .

[0122] In summary, the terminal structure, manufacturing method and power device provided by the technical scheme of the present application have the following advantages: the injection depth of the third doped region 6 is greater than the depth of the field limiting ring 3, which constitutes a vertical step effect in the doping distribution with respect to the device cell region 9, thereby improving the withstand voltage capability of the device and reducing the chip area required by the terminal structure. At the same time, the terminal structure of the present application is not sensitive to the concentration of JTE and the surface charge. In addition, the present application distributes the high electric field relaxation of the main junction extension region 2 to the middle region of the entire terminal, i.e. the field limiting ring 3 region, or the field limiting ring 3 region and the third doped region 6, so that multiple regions share the energy of avalanche breakdown, thereby improving the avalanche resistance of the terminal structure, improving the withstand voltage capability of the terminal structure, and further improving the reliability and stability of the power device.

[0123] Various embodiments are described in the specification in a progressive and / or concurrent manner, each embodiment emphasizing different aspects and embodiments, which provide their respective benefits. The same can apply to the corresponding method embodiments as well. For the devices disclosed by the embodiments, as they have corresponding relationship with the methods disclosed by the embodiments, the description is relatively simple and the relevant part can be referred to the method part.

[0124] It should be noted that, in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0125] It should also be noted that, in this document, relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0126] The above description of disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A terminal structure, characterized by comprising: The terminal structure comprises: a first epitaxial layer; a buried layer located on one side of the first epitaxial layer; a first doped region penetrating through the buried layer, the first doped region being opposite to the doped type of the buried layer; a second epitaxial layer located on the side of the buried layer away from the first epitaxial layer, the second epitaxial layer having a main junction expansion region and a field limiting ring therein; an oxide layer located on the side of the second epitaxial layer away from the buried layer; wherein the second epitaxial layer and the first epitaxial layer are opposite to the doped type of the buried layer; in a first direction, the field limiting ring is located between the main junction expansion region and the first doped region, the first direction being perpendicular to the direction of the first epitaxial layer pointing to the second epitaxial layer; the side surface of the oxide layer away from the buried layer has a first groove, the first groove extending into the second epitaxial layer, the first groove being used as an ion implantation window of the first doped region; a plurality of the field limiting rings are arranged at intervals in the first direction.

2. The terminal structure according to claim 1, characterized in that The terminal structure comprises: a first protective layer located at the bottom of the first groove, the first protective layer having a spacing from the first doped region.

3. The terminal structure according to claim 1, characterized by The terminal structure comprises: a second doped region and a third doped region penetrating through the buried layer, the second doped region and the third doped region being located between the field limiting ring and the first doped region; wherein the second doped region is opposite to the doped type of the buried layer, the third doped region is the same as the doped type of the buried layer, and the doping concentration of the third doped region is greater than the doping concentration of the buried layer.

4. The terminal structure according to claim 3, characterized in that The side surface of the oxide layer away from the buried layer has a second groove, the second groove extending into the second epitaxial layer, the second groove being used as an ion implantation window of the second doped region and the third doped region.

5. The terminal structure according to claim 4, characterized in that a second protective layer located at the bottom of the second groove, wherein the second doped region has a spacing from the second protective layer, and the third doped region is in contact with the second protective layer.

6. The terminal structure according to claim 3, wherein A plurality of the third doped regions are arranged at intervals in the first direction.

7. The terminal structure of claim 4, wherein The intervals of adjacent second grooves are equal, and the widths of the second grooves gradually decrease in the direction of the main junction expansion region pointing to the field limiting ring; or, The widths of the second grooves are equal, and the intervals of adjacent second grooves gradually increase in the direction of the main junction expansion region pointing to the field limiting ring.

8. The terminal structure of claim 1, wherein The intervals of adjacent field limiting rings are equal, and the widths of the field limiting rings gradually decrease in the direction of the main junction expansion region pointing to the field limiting ring; or, The widths of the field limiting rings are equal, and the intervals of adjacent field limiting rings gradually increase in the direction of the main junction expansion region pointing to the field limiting ring.

9. A power device, characterized by The terminal structure comprises: any one of the terminal structures according to claims 1-8; a device cell region located on the side of the main junction expansion region away from the field limiting ring.

10. A method of manufacture, characterized by, The terminal structure comprises: providing an epitaxial wafer, the epitaxial wafer comprising: a first epitaxial layer; a buried layer located on one side of the first epitaxial layer; a second epitaxial layer located on the side of the buried layer away from the first epitaxial layer; wherein the second epitaxial layer and the first epitaxial layer are opposite to the doped type of the buried layer; forming an oxide layer on a side surface of the second epitaxial layer facing away from the buried layer; forming a main junction extension region and a field limiting ring in the second epitaxial layer; forming a first doped region penetrating the buried layer, the first doped region being opposite to a doping type of the buried layer; wherein, in a first direction, the field limiting ring is located between the main junction extension region and the first doped region, the first direction being perpendicular to a direction of the first epitaxial layer pointing to the second epitaxial layer.

11. The method of manufacturing according to claim 10, wherein, The method for forming the first doped region comprises: forming a first recess on a side surface of the oxide layer facing away from the buried layer; based on the first recess, performing ion implantation to form the first doped region.

12. The method of manufacturing according to claim 11, wherein, Further comprising: forming a second recess at the same time as forming the first recess; based on the second recess, performing ion implantation to form a second doped region penetrating the buried layer at the same time as forming the first doped region; after forming the second doped region, based on the second recess, performing ion implantation to form a third doped region penetrating the buried layer; wherein, the second doped region and the third doped region are both located between the field limiting ring and the first doped region.

Images