Sparse matrix parallel solution method, device and electronic equipment

Abstract

The present invention provides a sparse matrix parallel solution method, device and electronic device, which are applied to a parallel computing platform, wherein the parallel computing platform includes a processor, the processor includes a high-speed local memory and a main memory, and the method includes: receiving a first input matrix and a second input matrix, and storing a first non-zero element and a second non-zero element row by row respectively; matching the subscripts of the first non-zero element and the second non-zero element, and calculating the row product of the first input matrix and the second input matrix row by row based on the matching result; establishing a first hash table in the high-speed local memory and a second hash table in the main memory; obtaining product non-zero elements based on the row product, and storing the product non-zero elements in the first hash table and the second hash table; traversing the first hash table and the second hash table, and writing the product non-zero elements into a buffer; and obtaining an output matrix based on the product non-zero elements. Through this method, the parallel solution method minimizes the memory access overhead and maximizes the resource utilization.

Description

Technical Field

[0001] The present invention relates to the field of numerical computing technology, and in particular to a sparse matrix parallel solution method, device and electronic equipment. Background Art

[0002] With the development of computer technology, the demand for large-scale scientific computing is gradually increasing. Many fields of scientific computing, such as structural mechanics calculations and fluid mechanics calculations, require solving large-scale sparse linear equations.

[0003] In the numerical simulation of hypersonic aerodynamics, the numerical conditions of the viscous flow field problem are poor, and an implicit algorithm is required to accurately discretize and solve it within a sufficiently large step size. In the application process, it is necessary to solve the relevant sparse matrices under the viscous flow field. At present, an iterative solution based on algebraic multigrids has been proposed. However, in this solution, the step of calculating the sparse general matrix multiplication is time-consuming, which limits the performance of the solution. Therefore, finding an efficient sparse matrix parallel solution method is an important issue that the industry needs to solve urgently. Summary of the invention

[0004] The present invention provides a sparse matrix parallel solution method, device and electronic equipment, which realizes minimization of memory access overhead and maximization of resource utilization of the sparse matrix parallel solution method by rationally utilizing high-speed local memory space in a processor.

[0005] The present invention provides a sparse matrix parallel solution method, which is applied to a parallel computing platform. The parallel computing platform includes multiple processors, and the processors include a high-speed local memory and a main memory. The sparse matrix parallel solution method includes: receiving a first input matrix and a second input matrix, and storing a first non-zero element of the first input matrix and a second non-zero element of the second input matrix row by row respectively; matching the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculating the row product of the first input matrix and the second input matrix row by row through the processor; establishing a first hash table in the high-speed local memory, and establishing a second hash table in the main memory; obtaining product non-zero elements based on the row products, and storing the product non-zero elements in the first hash table and the second hash table; traversing the first hash table and the second hash table, and writing the product non-zero elements into the buffer of the processor; obtaining the output matrix based on the product non-zero elements stored in the buffer.

[0006] According to a sparse matrix parallel solution method provided by the present invention, based on the matching result, the row products of the first input matrix and the second input matrix are calculated row by row by the processor, including: determining the computing power of the processor; matching the corresponding number of product calculations for the processor based on the computing power; based on the matching result, calculating the row products of the first input matrix and the second input matrix corresponding to the number of product calculations row by row by the processor.

[0007] According to a sparse matrix parallel solution method provided by the present invention, the storing of the product non-zero elements to the first hash table and the second hash table includes: if the number of the product non-zero elements does not exceed a first number, storing the product non-zero elements to the first hash table; if the number of the product non-zero elements exceeds the first number, storing the excess product non-zero elements to the second hash table, wherein the first number is a preset multiple of the storage capacity of the high-speed local memory, and the excess product non-zero elements are the product non-zero elements that exceed the first number among the product non-zero elements.

[0008] According to a sparse matrix parallel solution method provided by the present invention, the non-zero element of the product is stored in the first hash table, including: if a hash conflict is encountered during the insertion of the non-zero element of the product into the first hash table, it is determined whether the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, and based on the determination result, the non-zero element of the product is stored in the first hash table.

[0009] According to a sparse matrix parallel solution method provided by the present invention, based on the judgment result, the non-zero element of the product is stored in the first hash table, including: if the judgment result is that the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, the storage element stored in the first hash table and the non-zero element of the product are added and merged, and stored in the first hash table; if the judgment result is that the column subscript of the storage element stored in the first hash table is not the same as the column subscript of the non-zero element of the product, an open addressing method is used to determine a free hash bucket, and the non-zero element of the product is stored in the free hash bucket of the first hash table.

[0010] According to a sparse matrix parallel solution method provided by the present invention, the storing of the excess product non-zero elements into the second hash table includes: if a hash conflict is encountered during the insertion of the excess product non-zero elements into the second hash table, determining whether the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, and based on the determination result, storing the excess product non-zero elements into the second hash table.

[0011] According to a sparse matrix parallel solution method provided by the present invention, based on the judgment result, the excess product non-zero element is stored in the second hash table, including: if the judgment result is that the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, the storage element stored in the second hash table and the excess product non-zero element are added and merged, and stored in the second hash table; if the judgment result is that the column subscript of the storage element stored in the second hash table is not the same as the column subscript of the excess product non-zero element, an open addressing method is used to determine a free hash bucket, and the excess product non-zero element is stored in the free hash bucket of the second hash table.

[0012] According to a sparse matrix parallel solution method provided by the present invention, the buffer includes a current buffer and a newly generated buffer, and the traversing of the first hash table and the second hash table to write the non-zero elements of the product into the buffer of the processor includes: traversing the first hash table and the second hash table to write the non-zero elements of the product into the current buffer of the processor; in response to the current buffer being full, storing the non-zero elements of the product that are not stored in the current buffer to the newly generated buffer, and recording the current buffer and the newly generated buffer based on pointers.

[0013] According to a sparse matrix parallel solution method provided by the present invention, the output matrix is ​​obtained based on the non-zero elements of the product stored in the buffer, including: creating an output matrix memory space; based on the pointer, copying the non-zero elements of the product stored in the buffer to the output matrix memory space to obtain the output matrix.

[0014] The present invention also provides a sparse matrix parallel solution device, which is applied to a parallel computing platform, and the parallel computing platform includes multiple processors, and the processors include a high-speed local memory and a main memory. The sparse matrix parallel solution device includes: a receiving module, which is used to receive a first input matrix and a second input matrix, and store the first non-zero element of the first input matrix and the second non-zero element of the second input matrix row by row respectively; a calculation module, which is used to match the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculate the row product of the first input matrix and the second input matrix row by row through the processor; a creation module, which is used to establish a first hash table in the high-speed local memory and a second hash table in the main memory; a storage module, which is used to obtain product non-zero elements based on the row product, and store the product non-zero elements in the first hash table and the second hash table; a cache module, which is used to traverse the first hash table and the second hash table, and write the product non-zero elements into the buffer of the processor; a generation module, which is used to obtain the output matrix based on the product non-zero elements stored in the buffer.

[0015] The present invention also provides a sparse matrix parallel solution device, wherein the calculation module calculates the row products of the first input matrix and the second input matrix row by row through the processor based on the matching results in the following manner: determining the computing power of the processor; matching the corresponding number of product calculations for the processor based on the computing power; and calculating the row products of the first input matrix and the second input matrix corresponding to the number of product calculations row by row through the processor based on the matching results.

[0016] The present invention also provides a sparse matrix parallel solution device, wherein the storage module stores the non-zero product elements to the first hash table and the second hash table in the following manner: if the number of the non-zero product elements does not exceed a first number, the non-zero product elements are stored in the first hash table; if the number of the non-zero product elements exceeds the first number, the excess non-zero product elements are stored in the second hash table, wherein the first number is a preset multiple of the storage capacity of the high-speed local memory, and the excess non-zero product elements are the non-zero product elements in the non-zero product elements that exceed the first number.

[0017] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the above-mentioned sparse matrix parallel solution methods are implemented.

[0018] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above-mentioned sparse matrix parallel solution methods.

[0019] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned sparse matrix parallel solution methods are implemented.

[0020] The sparse matrix parallel solution method, device and electronic device provided by the present invention realize the reasonable use of high-speed local memory space by creating a hash table in the high-speed local memory space of the processor. In the process of writing the non-zero element of the product into the buffer of the processor and obtaining the output matrix, data access can be performed quickly and efficiently in the hash table, thereby realizing the minimization of memory access overhead and maximization of resource utilization of the sparse matrix parallel solution method, and improving the computational efficiency of the sparse matrix parallel solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 This is one of the flow charts of the sparse matrix parallel solution method provided by the present invention;

[0023] Figure 2 It is one of the flowcharts of calculating the row product of the first input matrix and the second input matrix row by row by a processor based on the matching result provided by the present invention;

[0024] Figure 3 It is one of the flow charts of processing each product element when performing sparse general matrix concurrent calculation on the input matrix provided by the present invention;

[0025] Figure 4 This is the second flow chart of processing each product element when performing concurrent sparse general matrix calculation on an input matrix provided by the present invention;

[0026] Figure 5 It is one of the flowchart diagrams of traversing the first hash table and the second hash table and writing the non-zero element of the product into the buffer of the processor provided by the present invention;

[0027] Figure 6 It is one of the flow charts of obtaining an output matrix based on the non-zero elements of the product stored in the buffer provided by the present invention;

[0028] Figure 7 It is a schematic diagram of the performance test results of applying the sparse matrix parallel solution method provided by the present invention to run on a new generation of Sunway supercomputer;

[0029] Figure 8 It is a structural schematic diagram of a sparse matrix parallel solving device provided by the present invention;

[0030] Fig. 9 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] With the development of computer technology, the demand for large-scale scientific computing is gradually increasing. Many fields of scientific computing, such as structural mechanics calculations and fluid mechanics calculations, require solving large-scale sparse linear equations.

[0033] In the numerical simulation of hypersonic aerodynamics, the numerical conditions of the viscous flow field problem are poor, and an implicit algorithm is required to accurately discretize and solve it within a sufficiently large step size. In the implicit algorithm, the discretized unknowns form a set of algebraic equations, which can be linearized to obtain a linear equation system Ax = b, and then solved using an iterative method. In such a problem, the low-frequency component in the iterative error is difficult to eliminate, resulting in poor iterative convergence.

[0034] To solve the above problems, the multigrid method is an iterative solution with high parallelism and strong numerical convergence. It maps the linear space formed by the original discrete grid to a coarser discrete grid space, constructs the sampling matrix R1 that maps from the original space to the coarse grid space, and the interpolation matrix P1 that maps from the coarse grid space back to the original space, thereby obtaining the coarse grid equation After recursively coarsening the coarse grid, the low-frequency errors in it increase in frequency in the coarse grid space, so they can be effectively eliminated in the iterations on multiple layers of coarse grids. The coarse grid solution is then mapped back to the original grid, thus achieving rapid convergence.

[0035] In the case of unstructured grids, before the iteration begins, sparse general matrix multiplication needs to be calculated to construct multiple new grids. In each layer of grid, A needs to be calculated.i =R i A i- 1P i , where R i , A i-1 and P i They are sampling matrix, equation coefficient matrix and interpolation matrix, all of which are sparse. It is understandable that in the application process, it is necessary to solve the relevant sparse matrices under the viscous flow field. At present, finding an efficient sparse matrix parallel solution method is an important issue that needs to be solved in the industry.

[0036] It is understandable that the process of solving sparse matrices in parallel can be a process of performing parallel multiplication calculations on sparse matrices. As known from the related art, the development of high-performance technology has made it possible for multiple processors to operate in coordination and efficiently utilize parallel units for calculations and memory access. Compared with the powerful computing power provided by multiple processors, the performance of many programs is limited by the access speed of system memory. For this reason, the processor's own on-chip memory can store a small portion of data and provide a fast access mode. How to effectively utilize the on-chip memory space and reduce the number of main memory accesses poses a challenge to program developers.

[0037] The sparse matrix parallel solution method provided by the present invention can quickly and effectively implement data access by rationally utilizing high-speed local memory space, thereby minimizing memory access overhead and maximizing resource utilization of the sparse matrix parallel solution method, and improving the computational efficiency of the sparse matrix parallel solution.

[0038] It should be noted that the sparse matrix parallel solution method provided by the present invention can be applied to relevant calculation scenarios of viscous flow field problems in the numerical simulation of hypersonic aerodynamics. By solving the relevant sparse matrix under the viscous flow field, the pressure, density and flow rate of the air at each point in the space in each discrete time step can be obtained.

[0039] The present invention will illustrate the process of the sparse matrix parallel solution method in conjunction with the following embodiments.

[0040] Figure 1 This is one of the flow charts of the sparse matrix parallel solution method provided by the present invention.

[0041] In an exemplary embodiment of the present invention, the sparse matrix parallel solution method can be applied to a parallel computing platform, wherein the parallel computing platform can include multiple processors, each processor can include a high-speed local memory and a main memory. It is understandable that the access delay of the high-speed local memory is often within a few clock cycles and has an address space independent of the main memory.

[0042] like Figure 1As shown, the sparse matrix parallel solution method may include steps 110 to 160, and each step will be introduced below.

[0043] In step 110, a first input matrix and a second input matrix are received, and the first non-zero elements of the first input matrix and the second non-zero elements of the second input matrix are stored row by row, respectively.

[0044] In one embodiment, the first input matrix and the second input matrix can be understood as matrices that need to be solved by sparse general matrices, and the first input matrix and the second input matrix can be sparse matrices. After the first input matrix and the second input matrix complete the sparse general matrix solution, an output matrix can be obtained. In one embodiment, the first input matrix and the second input matrix can be the initial state and boundary conditions in solving the viscous flow field problem in the numerical simulation of hypersonic aerodynamics, wherein the initial state can include the pressure, density and flow rate of air at each discrete point in the space at the initial moment. The output matrix can be the pressure, density and flow rate of air at each point in the space in each subsequent discrete time step.

[0045] In one embodiment, the first input matrix and the second input matrix may include input scales respectively. During the application process, the first input matrix, the second input matrix, and the input scale may be received, and multiple processors may be started to perform sparse general matrix multiplication calculations in parallel. In one example, all processor resources in the processor group may be started, wherein each thread may be bound to a processor resource. In one example, all processors may be started for execution, for example, P processors may be started and P threads may be bound. In one example, the first input matrix may be a sparse matrix A of M*K, and the second input matrix may be a sparse matrix B of K*N. The first non-zero element of the first input matrix A and the second non-zero element of the second input matrix B may be stored in the memory of the processor in a row-by-row order.

[0046] In one embodiment, all sparse matrices (e.g., the first input matrix and the second input matrix) can be represented in a compressed sparse row format. In one example, the first input matrix A and the second input matrix B may include: an array V containing all non-zero values A and V B , an integer array I containing all non-zero column indices A and I B , and the position P of the first non-zero element in each row A and P B . In V A 、V B ,I A and I BIn , all non-zero elements are arranged row by row. For example, the value of the non-zero element (the first non-zero element) in the i-th row of the first input matrix A is V A From P A [i] to P A [i+1]-1 value. It can be understood that P A and P B is a non-negative non-decreasing integer, I A and I B is a non-negative integer, and there are no repeated subscripts in the same row of the matrix. A The subscripts in K and I do not exceed B The subscripts in do not exceed N.

[0047] In step 120, the subscripts of the first non-zero element and the second non-zero element are matched, and based on the matching result, the row product of the first input matrix and the second input matrix is ​​calculated row by row by the processor.

[0048] In one embodiment, the first non-zero element and the second non-zero element with matching subscripts may be found, and the product of the first input matrix and the second input matrix, ie, the row product, may be calculated row by row by the processor.

[0049] In step 130, a first hash table is established in a high-speed local memory, and a second hash table is established in a main memory.

[0050] In one embodiment, the high-speed local memory can be a software-controllable memory, whose access delay is often within a few clock cycles and has an address space independent of the main memory. It is understandable that by cleverly utilizing the high-speed local memory for fast and efficient data access, it can bring beneficial effects to high-performance programming, such as parallel solving of sparse matrices.

[0051] In one embodiment, a first hash table can be established in a high-speed local memory, and a second hash table can be established in a main memory. In the application process, the best first hash table or second hash table can be selected to store the non-zero elements of the products included in the row products according to the sparsity of the first input matrix and the second input matrix, thereby maximizing resource utilization.

[0052] In step 140 , product non-zero elements are obtained based on the row product, and the product non-zero elements are stored in the first hash table and the second hash table.

[0053] In step 150, the first hash table and the second hash table are traversed, and non-zero elements of the product are written into the buffer of the processor.

[0054] In one embodiment, the product non-zero element may be a non-zero element included in the output matrix. In the application process, the product non-zero element may be obtained based on the row product, and the product non-zero element may be stored in the first hash table and the second hash table. Further, the first hash table and the second hash table may be traversed to write the product non-zero element into the buffer of the processor.

[0055] In one embodiment, a buffer can be allocated for each processor core in the memory, and a two-layer hash table is established for each processor core. The two-layer hash table includes a first hash table in a high-speed local memory and a second hash table in a main memory. During the application process, the non-zero element of the product can be stored in the first hash table and the second hash table, and the first hash table and the second hash table are traversed to write the non-zero element of the product into the buffer of the processor. Since the first hash table is stored in the high-speed local memory, the memory access overhead of writing the non-zero element of the product into the buffer of the processor can be reduced, thereby maximizing the utilization of computing resources.

[0056] In step 160, an output matrix is ​​obtained based on the non-zero elements of the products stored in the buffer.

[0057] The output matrix may be a matrix obtained by performing a sparse general matrix multiplication calculation on the first input matrix and the second input matrix. In one embodiment, an output matrix memory space may be allocated for the output matrix, and the non-zero elements stored in the buffer of each processor may be copied to the output matrix memory space to obtain the output matrix.

[0058] The sparse matrix parallel solution method provided by the present invention realizes reasonable utilization of high-speed local memory space by creating a hash table in the high-speed local memory space of the processor. In the process of writing the non-zero element of the product into the buffer of the processor and obtaining the output matrix, data access can be performed quickly and efficiently in the hash table, thereby realizing the minimization of memory access overhead and maximization of resource utilization of the sparse matrix parallel solution method, and improving the computational efficiency of the sparse matrix parallel solution.

[0059] The present invention will be described in conjunction with the following embodiments to illustrate a process of calculating the row product of the first input matrix and the second input matrix row by row by a processor based on the matching result.

[0060] Figure 2 This is one of the flowchart diagrams of calculating the row product of the first input matrix and the second input matrix row by row by a processor based on the matching result provided by the present invention.

[0061] In an exemplary embodiment of the present invention, Figure 2 As shown, based on the matching result, calculating the row product of the first input matrix and the second input matrix row by row by the processor may include steps 210 to 230, and each step will be introduced below.

[0062] In step 210, the computing capability of the processor is determined.

[0063] In step 220, the corresponding number of product calculations is matched to the processor based on the computing capability.

[0064] In step 230, based on the matching result, the processor calculates row products of the first input matrix and the second input matrix row by row corresponding to the number of product calculations.

[0065] In one embodiment, the computing power of each processor can be determined. Among them, the computing power can be the ability of the processor to perform the number of product calculations, for example, the number of times the processor performs product calculations per unit time. It can be understood that by performing product calculations on the corresponding non-zero elements in the first input matrix and the second input matrix, the corresponding row product can be obtained. In one example, for row product A, m product calculations need to be performed, and for row product B, n product calculations need to be performed. If m is greater than n, when calculating row product A, a processor with high computing power can be selected for calculation. In the application process, the number of product calculations for each row of the output matrix can be counted, and according to the number of product calculations for each row, each row can be evenly distributed to the processor with corresponding computing power for calculation. Through this embodiment, the load balancing of the processor can be optimized, thereby improving the utilization rate of computing resources.

[0066] In one embodiment, the number of product calculations for the i-th row of the output matrix may be Among them, nnz(B k ) represents the number of non-zero elements in the kth row of the second input matrix B. i The calculation process can be executed in parallel on each row.

[0067] In one embodiment, the number of product calculations for the i-th row is m. i The calculation method can be realized by the following method: A From P A [i] to P A [i+1]-1 subscript k, accumulated P B [k+1]-P B [k] The value obtained. In the application process, P processor cores can be used to perform calculations on the output matrix C. In one example, the pth processor core can calculate an M in the output matrix C. p ×N sub-block, that is, an M in the first input matrix A p The sub-block of M×K is multiplied by the second input matrix B. In one embodiment, M p The calculation process can be: first calculate m i The prefix and That is, the number of product calculations that have been performed until the i-th row of the output matrix. Further, the total number of multiplications of the entire output matrix C can be obtained as s(M). Combined with the computing power of each processor, the processor is matched with a row product with a corresponding number of product calculations for calculation. In one example, the calculated mi value can be stored in an array in the main memory, and the prefix sum of the array is calculated. By searching the prefix sum, we can get t p value, and then we can get M p value.

[0068] In another example, for each processor pi, we can find the one closest to s(t). The elements of Then the tth corresponding output matrix p-1 Go to t p The rows are assigned to processor p for product calculation, that is, M p =t p -t p-1 In summary, the number of product calculations assigned to processor p is s(t p )-s(t p-1 )≈s(M)×p / Ps(M)×(p-1) / P=s(M) / P. It can be understood that the number of product calculations assigned to processor p matches the computing power of processor p. Through this embodiment, the load balancing of the processor can be optimized, thereby improving the utilization rate of computing resources.

[0069] The present invention will be described in conjunction with the following embodiments to explain the process of storing non-zero elements of the product in the first hash table and the second hash table.

[0070] In an exemplary embodiment of the present invention, if the number of product non-zero elements does not exceed the first number, the product non-zero elements are stored in the first hash table. If the number of product non-zero elements exceeds the first number, the excess product non-zero elements are stored in the second hash table. The first number is a preset multiple of the storage capacity of the high-speed local memory, and the excess product non-zero elements are product non-zero elements that exceed the first number in the product non-zero elements. The preset multiple can be adjusted according to actual conditions, and the preset multiple is not specifically limited in the invention.

[0071] In one embodiment, before storing the non-zero element of the product in the first hash table or the second hash table, the first hash table and the second hash table may be initialized, and the capacities of the first hash table and the second hash table may be determined.

[0072] In one embodiment, each processor core allocates two arrays V in a high-speed local memory. L1 and I L1, respectively representing the value and column index in the hash bucket of the first hash table; and allocate two arrays V in the main memory L2 and I L2 , respectively represent the value and column index in the hash bucket of the second hash table. L1 or I L2 When a subscript is outside the range [0, N), it means that the hash bucket is empty. When initializing the hash table, all hash buckets can be set to empty.

[0073] In one embodiment, the above-mentioned embodiment is continued as an example for explanation. It can be estimated that nnz(C i ) i , that is, nnz(C i )≤u i =min(m i , N), it is understandable that C i Represents the number of non-zero elements in the i-th row of the output matrix C. During the application process, C is calculated on each processor core i Before that, you can initialize the first hash table. And according to u i Determine the capacity of the first hash table. In one example, if u i / α (α is a constant less than 1) does not exceed the capacity of the high-speed local memory (which can be called condition A), the capacity of the first hash table is u i / α, at this time, the non-zero element of the product can be stored in the first hash table. In another example, if u i When / α (α is a constant less than 1) exceeds the capacity of the high-speed local memory, the capacity of the first hash table is the capacity of the high-speed local memory. At this time, the excess product non-zero elements can be stored in the second hash table.

[0074] It is understandable that u i can represent the number of non-zero product elements, α can represent a preset multiple, and the product of α and the capacity of the high-speed local memory can represent a first quantity. In the application process, if the number of non-zero product elements does not exceed the first quantity, the non-zero product elements are stored in the first hash table. If the number of non-zero product elements exceeds the first quantity, the excess non-zero product elements are stored in the second hash table.

[0075] In order to further introduce the sparse matrix parallel solution method provided by the present invention, the process of storing the non-zero elements of the product into the first hash table will be described in combination with the following embodiments.

[0076] In an exemplary embodiment of the present invention, if a hash conflict is encountered during the process of inserting a non-zero element of the product into the first hash table, it is determined whether the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, and based on the determination result, the non-zero element of the product is stored in the first hash table.

[0077] In an exemplary embodiment of the present invention, based on the judgment result, storing the non-zero element of the product in the first hash table can be implemented in the following manner: if the judgment result is that the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, then the storage element stored in the first hash table and the non-zero element of the product are added and merged, and stored in the first hash table. If the judgment result is that the column subscript of the storage element stored in the first hash table is not the same as the column subscript of the non-zero element of the product, an open addressing method is used to determine an idle hash bucket, and the non-zero element of the product is stored in an idle hash bucket of the first hash table.

[0078] In one embodiment, the non-zero elements in the first input matrix A can be multiplied with the corresponding non-zero elements in the second input matrix B, and the result can be inserted into the first hash table using the column subscript in the output matrix C as the key. In the process of inserting into the first hash table, if a hash conflict is encountered, it can be checked whether the column subscript of the storage element stored in the first hash table is the same as the column subscript of the product non-zero element. If they are the same, the storage elements stored in the first hash table can be added and merged with the product non-zero element without inserting new elements. Otherwise, use the open addressing method to try to find another hash bucket until an idle hash bucket is found. After finding an idle hash bucket, it can be checked whether the load factor of the first hash table reaches α. If not, the product non-zero element can be inserted into the empty bucket; if it has been reached, the excess product non-zero element can be inserted into the second hash table.

[0079] In order to further introduce the sparse matrix parallel solution method provided by the present invention, the process of processing each product element when performing sparse general matrix concurrent calculation on the input matrix will be described in combination with the following embodiments.

[0080] Figure 3 It is one of the flowchart diagrams of processing each product element when performing sparse general matrix concurrent calculation on the input matrix provided by the present invention.

[0081] In one embodiment, if Figure 3 As shown, when performing sparse general matrix concurrent calculation on the input matrix, processing each product element may include steps 310 to 330, and each step will be introduced below.

[0082] In step 310, the first hash position of the first hash table is checked.

[0083] In step 320, it is determined whether the hash position is empty.

[0084] In step 330, if the hash position is empty, the new element is inserted into the empty position of the first hash table.

[0085] In step 340, if the hash position is not empty, it is determined whether the position is equal to the column subscript of the new element.

[0086] In step 350, if the position is equal to the column subscript of the new element, the new element is inserted into the empty position of the first hash table.

[0087] In step 360, if the position is not equal to the column index of the new element, check the next hash position and continue to execute step 320 until all product elements are stored.

[0088] In one embodiment, a sparse general matrix multiplication is performed on a sparse matrix (e.g., a first input matrix A and a second input matrix B). When processing the i-th row, if condition A (i.e., u i / α does not exceed the capacity of the high-speed local memory), then the first hash table is initialized first, wherein the capacity of the first hash table can be u i / α. Then take the non-zero elements in the i-th row of the first input matrix A, that is, for each p A =P A [i], ..., P A [i+1]-1Perform the following steps: For each p B =P B [I A [p A ]], ..., P B [I A [p A ]+1]-1, a new element is generated, whose value is V A [p A ]*V B [p B ], column subscript is I B [p B ], and execute steps 310 to 360 for the new element. A Represents the first matrix A in P A [i], ..., P A The first non-zero element between [i+1]-1.

[0089] When all p in the row AAfter the processing is completed, the first hash table is traversed, and the values ​​and column subscripts of the non-empty hash buckets therein are collected and written into the buffer. Further, the output matrix can be obtained based on the values ​​and column subscripts of the non-empty hash buckets stored in the buffer. In this embodiment, the optimal hash table capacity can be selected according to the different sparsity of the input matrix, and storage can be performed based on the hash table, which can maximize resource utilization.

[0090] In order to further introduce the sparse matrix parallel solution method provided by the present invention, the process of storing the excess product non-zero elements in the second hash table will be described in combination with the following embodiments.

[0091] In an exemplary embodiment of the present invention, if a hash conflict is encountered during the process of inserting the excess product non-zero element into the second hash table, it is determined whether the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, and based on the determination result, the excess product non-zero element is stored in the second hash table.

[0092] In an exemplary embodiment of the present invention, based on the judgment result, storing the excess product non-zero element in the second hash table can be achieved in the following manner: if the judgment result is that the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, then the storage element stored in the second hash table and the excess product non-zero element are added and merged, and stored in the second hash table; if the judgment result is that the column subscript of the storage element stored in the second hash table is not the same as the column subscript of the excess product non-zero element, then the open addressing method is used to determine the free hash bucket, and the excess product non-zero element is stored in the free hash bucket of the second hash table.

[0093] In one embodiment, before the second hash table is used for the first time, the second hash table may be initialized and its capacity may be determined. If μ of the mi multiplications have been calculated during initialization and ν elements have been generated in the first hash table, then the capacity of the second hash table may be min(m i -μ, N-ν) / α.

[0094] In another embodiment, the method of inserting an element into the second hash table can be consistent with inserting into the first hash table, but there is no need to check the load factor. In one example, if a hash conflict is encountered during the process of inserting the excess product non-zero element into the second hash table, it can be checked whether the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element. If the same, the storage element stored in the second hash table and the excess product non-zero element are added and merged, and stored in the second hash table without inserting a new element. Otherwise, an open addressing method is used to determine the idle hash bucket, and the excess product non-zero element is stored in the idle hash bucket of the second hash table.

[0095] In order to further introduce the sparse matrix parallel solution method provided by the present invention, the process of processing each product element when performing sparse general matrix concurrent calculation on the input matrix will be described in combination with the following embodiments.

[0096] Figure 4 This is the second flow chart of processing each product element when performing sparse general matrix concurrent calculation on the input matrix provided by the present invention.

[0097] In one embodiment, if Figure 4 As shown, when performing sparse general matrix concurrent calculation on the input matrix, processing each product element may include steps 4010 to 4150, and each step will be introduced below.

[0098] In step 4010, the first hash position of the first hash table is checked.

[0099] In step 4020, determine whether the hash position is empty.

[0100] In step 4030, if the hash position is empty, it is determined whether the load factor of the first hash table reaches α, where α is the same as α described above and is a constant less than 1.

[0101] In step 4040, if the load factor of the first hash table reaches α, it is determined whether the second hash table has been initialized.

[0102] In step 4050, if the load factor of the first hash table does not reach α, the μ value is increased by 1, the ν value is increased by 1, and the new element is inserted into the empty position in the first hash table. Wherein, μ is the same as μ described above, indicating the number of product calculations. ν is the same as ν described above, indicating the new element generated in the first hash table.

[0103] In step 4060, if the second hash table is not initialized, the second hash table is initialized and its capacity is set to min(m-μ, N-ν) / α.

[0104] In step 4070, if the second hash table has been initialized, check the first hash position of the second hash table.

[0105] In step 4080, determine whether the hash position is empty.

[0106] In step 4090, if the hash position is not empty, determine whether the column subscripts of the element at that position are equal to the column subscript of the new element.

[0107] In step 4100, if the hash position is empty, the new element is inserted into the empty position in the second hash table.

[0108] In step 4110, if the column subscript of the element at this position is not equal to the column subscript of the new element, check the next hash position.

[0109] In step 4120, if the column subscripts of the element at the position and the new element are equal, the new element is merged with the element in the second hash table.

[0110] In step 4130, if the hash position is not empty, determine whether the column subscript of the position is equal to the column subscript of the new element.

[0111] In step 4140, if the column subscript of the position is not equal to the column subscript of the new element, the next hash position is checked and step 4020 is continued until all product elements are stored.

[0112] In step 4150, if the column subscript of the position is equal to the column subscript of the new element, the μ value is increased by 1, and the new element is merged with the element in the first hash table.

[0113] In one embodiment, a sparse general matrix multiplication is performed on a sparse matrix (e.g., a first input matrix A and a second input matrix B). When processing the i-th row, if condition A (i.e., u i / α does not exceed the capacity of the high-speed local memory), then the first hash table is initialized. The capacity of the first hash table is the capacity of the high-speed local memory. Then, the first non-zero element of the i-th row of the first input matrix A is taken, that is, for each p A =P A [i], ..., P A [i+1]-1Perform the following steps: For each p B =P B [I A [p A ]], ..., P B [I A [p A ]+1]-1, a new element is generated, whose value is V A [p A ]*V B [p B ], column subscript is I B [p B ], and execute steps 4010 to 4150 for the new element. A After the processing is completed, the first hash table and the second hash table are traversed to collect the values ​​and column indices of the non-empty hash buckets and write them into the buffer. A Represents the first matrix A in P A [i], ..., P A The first non-zero element between [i+1]-1.

[0114] It should be noted that the values ​​and column subscripts in the buffer are the values ​​V of the non-zero elements of the output matrix C. Cand column subscript I C In order to obtain the output matrix P C (P C Indicates the output matrix C in P C [i], ..., P C [i+1]-1, in addition to recording the non-zero number of each row after the calculation is completed, it is also necessary to calculate the prefix sum of the non-zero number of each row at the end to obtain P C , and then the output matrix C is obtained. In this embodiment, the optimal hash table capacity can be selected according to the different sparsity of the input matrix, and storage is performed based on the hash table, which can maximize resource utilization.

[0115] The present invention will describe the process of traversing the first hash table and the second hash table and writing the non-zero element of the product into the buffer of the processor in combination with the following embodiments.

[0116] Figure 5 This is one of the flowchart diagrams of traversing the first hash table and the second hash table and writing the non-zero element of the product into the buffer of the processor provided by the present invention.

[0117] In an exemplary embodiment of the present invention, the buffer may include a current buffer and a newly generated buffer. Figure 5 As shown, traversing the first hash table and the second hash table and writing the product non-zero elements into the processor buffer may include steps 510 to 520, and each step will be introduced below.

[0118] In step 510, the first hash table and the second hash table are traversed, and non-zero elements of the product are written into the current buffer of the processor.

[0119] In step 520 , in response to the current buffer being full, the non-zero product elements that are not stored in the current buffer are stored in the newly generated buffer, and the current buffer and the newly generated buffer are recorded based on the pointer.

[0120] In one embodiment, all products of the non-zero elements of the first input matrix A and the corresponding non-zero elements of the second input matrix B are stored in a hash table (including a first hash table and a second hash table). The elements in the hash table are the non-zero elements of the output matrix C, and the first hash table and the second hash table are traversed and these elements are written into the buffer of the corresponding processor core. If the current buffer is full, a new buffer is allocated, and all full buffers are recorded with a series of pointers. In this embodiment, the non-zero elements of the output matrix C are stored in the first hash table and the second hash table, and the first hash table and the second hash table are traversed to write the product non-zero elements into the buffer of the processor. Since the first hash table is stored in a high-speed local memory, the memory access overhead of writing the product non-zero elements into the buffer of the processor can be reduced, thereby maximizing the utilization of computing resources.

[0121] The present invention will be described in conjunction with the following embodiments to explain the process of obtaining an output matrix based on the non-zero elements of the product stored in the buffer.

[0122] Figure 6 This is one of the flow charts of obtaining an output matrix based on the non-zero elements of the product stored in the buffer provided by the present invention.

[0123] In an exemplary embodiment of the present invention, Figure 6 As shown, obtaining the output matrix based on the non-zero elements of the product stored in the buffer may include step 610 and step 620, and each step will be introduced below.

[0124] In step 610, an output matrix memory space is created.

[0125] In step 620, based on the pointer, the non-zero elements of the product stored in the buffer are copied to the output matrix memory space to obtain the output matrix.

[0126] In one embodiment, an output matrix memory space may be created, and based on a pointer, non-zero elements stored in the buffer of each processor may be copied to the output matrix memory space to obtain an output matrix.

[0127] In another embodiment, the number of non-zero elements of the output matrix may be recorded, and memory space may be allocated for the output matrix according to the number of non-zero elements. Subsequently, all data in the buffer is copied to the memory space of the output matrix C to obtain the output matrix C.

[0128] Figure 7 The figure is a schematic diagram of the performance test results of the sparse matrix parallel solution method provided by the present invention running on a new generation of Shenwei supercomputer. Among them, swSparse represents the running result of the sparse matrix parallel solution method provided by the present invention on a core group of a new generation of domestic Shenwei processors, and MKL represents the running result of the mathematical library on an Intel Xeon Gold 6132 processor. Figure 7 As can be seen, this test uses the SuiteSparse data set and calculates the square of some square matrices in the data set. Although swSparse has a certain gap compared with MKL in a few large matrices, it has surpassed MKL in most matrices, and its geometric average performance is 69% faster than MKL.

[0129] According to the above description, the sparse matrix parallel solution method, device and electronic device provided by the present invention realize the reasonable use of high-speed local memory space by creating a hash table in the high-speed local memory space in the processor. In the process of writing the non-zero element of the product into the buffer of the processor and obtaining the output matrix, data access can be performed quickly and efficiently in the hash table, realizing the minimization of memory access overhead and maximization of resource utilization of the sparse matrix parallel solution method, and improving the computational efficiency of the sparse matrix parallel solution.

[0130] Based on the same concept, the present invention also provides a sparse matrix parallel solution device.

[0131] The sparse matrix parallel solution device provided by the present invention is described below. The sparse matrix parallel solution device described below and the sparse matrix parallel solution method described above can be referenced to each other.

[0132] It should be noted that the sparse matrix parallel solving device provided by the present invention can be applied to the scene of related calculations of viscous flow field problems in the numerical simulation of hypersonic aerodynamics. By solving the relevant sparse matrix under the viscous flow field, the pressure, density and flow rate of the air at each point in the space in each discrete time step can be obtained.

[0133] In an exemplary embodiment of the present invention, the sparse matrix parallel solution device can be applied to a parallel computing platform, wherein the parallel computing platform can include multiple processors, each processor can include a high-speed local memory and a main memory. It can be understood that the access delay of the high-speed local memory is often within a few clock cycles and has an address space independent of the main memory.

[0134] Figure 8 It is a structural schematic diagram of the sparse matrix parallel solution device provided by the present invention.

[0135] like Figure 8 As shown, the sparse matrix parallel solution device may include a receiving module 810, a computing module 820, a creating module 830, a storing module 840, a caching module 850 and a generating module 860, and each module will be introduced below.

[0136] The receiving module 810 may be configured to receive a first input matrix and a second input matrix, and store the first non-zero element of the first input matrix and the second non-zero element of the second input matrix row by row, respectively. In one embodiment, the first input matrix and the second input matrix may be the initial state and boundary conditions in solving the viscous flow field problem in the numerical simulation of hypersonic aerodynamics, wherein the initial state may include the pressure, density and flow rate of the air at each discrete point in the space at the initial moment. The output matrix may be the pressure, density and flow rate of the air at each point in the space in each subsequent discrete time step. The calculation module 820 may be configured to match the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculate the row product of the first input matrix and the second input matrix row by row through the processor.

[0137] The creation module 830 may be configured to create a first hash table in a high-speed local memory, and a second hash table in a main memory.

[0138] The storage module 840 may be configured to obtain product non-zero elements based on the row products, and store the product non-zero elements in the first hash table and the second hash table.

[0139] The cache module 850 may be configured to traverse the first hash table and the second hash table, and write non-zero elements of the products into a buffer of the processor.

[0140] The generating module 860 may be configured to obtain an output matrix based on the non-zero elements of the products stored in the buffer.

[0141] In an exemplary embodiment of the present invention, the calculation module 820 can calculate the row products of the first input matrix and the second input matrix row by row through the processor based on the matching result in the following manner: determine the computing power of the processor; match the corresponding number of product calculations for the processor based on the computing power; and calculate the row products of the first input matrix and the second input matrix corresponding to the number of product calculations row by row through the processor based on the matching result.

[0142] In an exemplary embodiment of the present invention, the storage module 840 may store product non-zero elements in the first hash table and the second hash table in the following manner: if the number of product non-zero elements does not exceed the first number, the product non-zero elements are stored in the first hash table; if the number of product non-zero elements exceeds the first number, the excess product non-zero elements are stored in the second hash table, wherein the first number is a preset multiple of the storage capacity of the high-speed local memory, and the excess product non-zero elements are the product non-zero elements that exceed the first number among the product non-zero elements.

[0143] In an exemplary embodiment of the present invention, the storage module 840 can store the non-zero element of the product to the first hash table in the following manner: if a hash conflict is encountered during the insertion of the non-zero element of the product into the first hash table, it is determined whether the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, and based on the determination result, the non-zero element of the product is stored in the first hash table.

[0144] In an exemplary embodiment of the present invention, the storage module 840 may store the non-zero element of the product in the first hash table based on the judgment result in the following manner: if the judgment result is that the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, then the storage element stored in the first hash table and the non-zero element of the product are added and merged and stored in the first hash table; if the judgment result is that the column subscript of the storage element stored in the first hash table is not the same as the column subscript of the non-zero element of the product, then the open addressing method is used to determine the free hash bucket, and the non-zero element of the product is stored in the free hash bucket of the first hash table.

[0145] In an exemplary embodiment of the present invention, the storage module 840 may store the non-zero element of the product in the first hash table based on the judgment result in the following manner: if the judgment result is that the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, then the storage element stored in the first hash table and the non-zero element of the product are added and merged and stored in the first hash table; if the judgment result is that the column subscript of the storage element stored in the first hash table is not the same as the column subscript of the non-zero element of the product, then the open addressing method is used to determine the free hash bucket, and the non-zero element of the product is stored in the free hash bucket of the first hash table.

[0146] In an exemplary embodiment of the present invention, the storage module 840 can store the excess product non-zero element in the second hash table in the following manner: if a hash conflict is encountered during the insertion of the excess product non-zero element into the second hash table, it is determined whether the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, and based on the determination result, the excess product non-zero element is stored in the second hash table.

[0147] In an exemplary embodiment of the present invention, the storage module 840 may store the excess product non-zero element in the second hash table based on the judgment result in the following manner: if the judgment result is that the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, then the storage element stored in the second hash table and the excess product non-zero element are added and merged and stored in the second hash table; if the judgment result is that the column subscript of the storage element stored in the second hash table is not the same as the column subscript of the excess product non-zero element, then the open addressing method is used to determine the free hash bucket, and the excess product non-zero element is stored in the free hash bucket of the second hash table.

[0148] In an exemplary embodiment of the present invention, the buffer includes a current buffer and a newly generated buffer. The cache module 850 can traverse the first hash table and the second hash table to write the non-zero elements of the product into the buffer of the processor in the following manner: traverse the first hash table and the second hash table to write the non-zero elements of the product into the current buffer of the processor; in response to the current buffer being full, store the non-zero elements of the product that are not stored in the current buffer into the newly generated buffer, and record the current buffer and the newly generated buffer based on the pointer.

[0149] In an exemplary embodiment of the present invention, the generation module 860 can obtain the output matrix based on the non-zero elements of the product stored in the buffer in the following manner: create an output matrix memory space; based on a pointer, copy the non-zero elements of the product stored in the buffer to the output matrix memory space to obtain the output matrix.

[0150] Fig. 9 An example of a physical structure diagram of an electronic device is shown in FIG. Fig. 9 As shown, the electronic device may include: a processor (processor) 910, a communication interface (Communications Interface) 920, a memory (memory) 930 and a communication bus 940, wherein the processor 910, the communication interface 920, and the memory 930 communicate with each other through the communication bus 940. The processor 910 can call the logic instructions in the memory 930 to execute the sparse matrix parallel solution method, wherein the sparse matrix parallel solution method can be applied to a parallel computing platform, the parallel computing platform includes multiple processors, the processor includes a high-speed local memory and a main memory, and the sparse matrix parallel solution method includes: receiving a first input matrix and a second input matrix, and storing the first non-zero element of the first input matrix and the second non-zero element of the second input matrix row by row respectively; matching the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculating the row product of the first input matrix and the second input matrix row by row through the processor; establishing a first hash table in the high-speed local memory, and establishing a second hash table in the main memory; obtaining product non-zero elements based on the row product, and storing the product non-zero elements in the first hash table and the second hash table; traversing the first hash table and the second hash table, and writing the product non-zero elements into the processor's buffer; obtaining an output matrix based on the product non-zero elements stored in the buffer.

[0151] In addition, the logic instructions in the above-mentioned memory 930 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0152] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the sparse matrix parallel solution method provided by the above methods, wherein the sparse matrix parallel solution method can be applied to a parallel computing platform, the parallel computing platform includes multiple processors, the processor includes a high-speed local memory and a main memory, and the sparse matrix parallel solution method includes: receiving a first input matrix and a second input matrix, and storing the first non-zero element of the first input matrix and the second non-zero element of the second input matrix row by row respectively; matching the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculating the row product of the first input matrix and the second input matrix row by row through the processor; establishing a first hash table in the high-speed local memory, and establishing a second hash table in the main memory; obtaining product non-zero elements based on row products, and storing the product non-zero elements in the first hash table and the second hash table; traversing the first hash table and the second hash table, and writing the product non-zero elements into the buffer of the processor; obtaining an output matrix based on the product non-zero elements stored in the buffer.

[0153] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the sparse matrix parallel solution method provided by the above methods, wherein the sparse matrix parallel solution method can be applied to a parallel computing platform, the parallel computing platform includes multiple processors, the processor includes a high-speed local memory and a main memory, and the sparse matrix parallel solution method includes: receiving a first input matrix and a second input matrix, and storing the first non-zero element of the first input matrix and the second non-zero element of the second input matrix row by row respectively; matching the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculating the row product of the first input matrix and the second input matrix row by row through the processor; establishing a first hash table in the high-speed local memory, and establishing a second hash table in the main memory; obtaining product non-zero elements based on row products, and storing the product non-zero elements in the first hash table and the second hash table; traversing the first hash table and the second hash table, and writing the product non-zero elements into the buffer of the processor; obtaining an output matrix based on the product non-zero elements stored in the buffer.

[0154] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0155] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A parallel solution method for sparse matrices, It is characterized in that The method is applied to a parallel computing platform, the parallel computing platform includes a plurality of processors, the processors include a high-speed local memory and a main memory, and the method includes: Receiving a first input matrix and a second input matrix, and storing first non-zero elements of the first input matrix and second non-zero elements of the second input matrix row by row respectively; Matching the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculating, by the processor, the row product of the first input matrix and the second input matrix row by row; Establishing a first hash table in the high-speed local memory and establishing a second hash table in the main memory; Obtaining product non-zero elements based on the row products, and storing the product non-zero elements in the first hash table and the second hash table; Traversing the first hash table and the second hash table, and writing the non-zero elements of the product into the buffer of the processor; An output matrix is ​​obtained based on the non-zero elements of the products stored in the buffer.

2. The sparse matrix parallel solution method according to claim 1, It is characterized in that The calculating, by the processor, row products of the first input matrix and the second input matrix row by row based on the matching result comprises: determining a computing capability of the processor; Based on the computing capability, matching a corresponding number of product calculations for the processor; Based on the matching result, the processor calculates row products of the first input matrix and the second input matrix row by row corresponding to the number of product calculations.

3. The sparse matrix parallel solution method according to claim 1, It is characterized in that The storing the non-zero elements of the product into the first hash table and the second hash table comprises: If the number of non-zero elements of the product does not exceed a first number, storing the non-zero elements of the product in the first hash table; If the number of the product non-zero elements exceeds a first number, the excess product non-zero elements are stored in the second hash table, wherein the first number is a preset multiple of the storage capacity of the high-speed local memory, and the excess product non-zero elements are the product non-zero elements in the product non-zero elements that exceed the first number.

4. The sparse matrix parallel solution method according to claim 3, It is characterized in that Storing the non-zero elements of the product into the first hash table includes: If a hash conflict occurs during the insertion of the non-zero element of the product into the first hash table, it is determined whether the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, and based on the determination result, the non-zero element of the product is stored in the first hash table.

5. The sparse matrix parallel solution method according to claim 4, It is characterized in that Based on the judgment result, storing the non-zero element of the product into the first hash table includes: If the judgment result is that the column subscript of the storage element stored in the first hash table is the same as the column subscript of the non-zero element of the product, then the storage element stored in the first hash table and the non-zero element of the product are added and merged, and stored in the first hash table; If the judgment result is that the column subscript of the storage element stored in the first hash table is different from the column subscript of the non-zero element of the product, an open addressing method is used to determine an idle hash bucket, and the non-zero element of the product is stored in the idle hash bucket of the first hash table.

6. The sparse matrix parallel solution method according to claim 3, It is characterized in that The step of storing the excess product non-zero elements into the second hash table comprises: If a hash conflict occurs during the insertion of the excess product non-zero element into the second hash table, it is determined whether the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, and based on the determination result, the excess product non-zero element is stored in the second hash table.

7. The sparse matrix parallel solution method according to claim 6, It is characterized in that Based on the determination result, storing the excess product non-zero elements into the second hash table includes: If the judgment result is that the column subscript of the storage element stored in the second hash table is the same as the column subscript of the excess product non-zero element, then the storage element stored in the second hash table and the excess product non-zero element are added and merged, and stored in the second hash table; If the judgment result is that the column subscript of the storage element stored in the second hash table is different from the column subscript of the excess product non-zero element, an open addressing method is used to determine an idle hash bucket, and the excess product non-zero element is stored in the idle hash bucket of the second hash table.

8. The sparse matrix parallel solving method according to claim 1, It is characterized in that The buffer includes a current buffer and a newly generated buffer, and the traversing the first hash table and the second hash table to write the non-zero element of the product into the buffer of the processor includes: Traversing the first hash table and the second hash table, and writing the non-zero element of the product into the current buffer of the processor; In response to the current buffer being full, the non-zero product elements that are not stored in the current buffer are stored in the newly generated buffer, and the current buffer and the newly generated buffer are recorded based on a pointer.

9. The sparse matrix parallel solving method according to claim 8, It is characterized in that The step of obtaining the output matrix based on the non-zero elements of the product stored in the buffer comprises: Create output matrix memory space; Based on the pointer, the non-zero elements of the product stored in the buffer are copied to the output matrix memory space to obtain the output matrix.

10. A sparse matrix parallel solution device, It is characterized in that The device is applied to a parallel computing platform, the parallel computing platform includes a plurality of processors, the processors include a high-speed local memory and a main memory, and the device includes: A receiving module, configured to receive a first input matrix and a second input matrix, and store a first non-zero element of the first input matrix and a second non-zero element of the second input matrix row by row respectively; a calculation module, configured to match the subscripts of the first non-zero element and the second non-zero element, and based on the matching result, calculate the row product of the first input matrix and the second input matrix row by row through the processor; A creation module, configured to establish a first hash table in the high-speed local memory and a second hash table in the main memory; A storage module, configured to obtain a non-zero element of a product based on the row product, and store the non-zero element of the product in the first hash table and the second hash table; A cache module, configured to traverse the first hash table and the second hash table, and write non-zero elements of the product into a buffer of the processor; A generating module is used to obtain an output matrix based on the non-zero elements of the product stored in the buffer.

11. The sparse matrix parallel solving device according to claim 10, It is characterized in that The calculation module calculates the row product of the first input matrix and the second input matrix row by row through the processor based on the matching result in the following manner: determining a computing capability of the processor; Based on the computing capability, matching a corresponding number of product calculations for the processor; Based on the matching result, the processor calculates row products of the first input matrix and the second input matrix row by row corresponding to the number of product calculations.

12. The sparse matrix parallel solving device according to claim 10, It is characterized in that The storage module stores the non-zero elements of the product into the first hash table and the second hash table in the following manner: If the number of non-zero elements of the product does not exceed a first number, storing the non-zero elements of the product in the first hash table; If the number of the product non-zero elements exceeds a first number, the excess product non-zero elements are stored in the second hash table, wherein the first number is a preset multiple of the storage capacity of the high-speed local memory, and the excess product non-zero elements are the product non-zero elements in the product non-zero elements that exceed the first number.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, It is characterized in that When the processor executes the program, the steps of the sparse matrix parallel solution method as described in any one of claims 1 to 9 are implemented.

14. A non-transitory computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the steps of the sparse matrix parallel solution method according to any one of claims 1 to 9 are implemented.

15. A computer program product comprising a computer program, It is characterized in that When the computer program is executed by a processor, the steps of the sparse matrix parallel solution method according to any one of claims 1 to 9 are implemented.

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