A new sensor architecture system based on memristor

Abstract

The invention discloses a novel sensor architecture system based on a memristor, wherein the output end of the sensor is connected to the input end of a corresponding comparator, the output end of the comparator is connected to the input end of a corresponding D-type flip-flop, the output end of each D-type flip-flop is connected to the input end of a time-to-digital converter, the output end of the time-to-digital converter is connected to a parallel-to-serial module; the output end of an oscillator is connected to the input end of a phase-locked loop, the first output end of the phase-locked loop is connected to the reference clock input end of the time-to-digital converter, and the second output end of the phase-locked loop is connected to the reference clock input end of the parallel-to-serial module. The system can effectively solve the problems of complex system hardware structure, high power consumption, large amount of data transmission and low efficiency in the prior art.

Description

Technical Field

[0001] The present invention relates to a novel sensor architecture system, and in particular to a novel sensor architecture system based on a memristor. Background Art

[0002] Sensors are devices used to detect, monitor, and respond (if necessary) to physical parameters such as temperature, pressure, humidity, and motion. They are an integral component of many real-world systems and are widely used in industrial, consumer, automotive, medical, and military applications. In the past, data acquired from sensors was sent directly to a central unit, which might then use discrete hardware or digital logic to perform post-processing or display the sensor data. With the advent of embedded processor solutions such as 8-bit microcontrollers (MCUs), the advantages of replacing fixed-program central hardware with MCUs that can be programmed to perform specific tasks required by the application have become increasingly apparent. However, 8-bit MCUs can only perform basic system processing tasks that are not computationally intensive.

[0003] As the third generation of artificial neural networks, spiking neural networks (SNNs) have received more and more attention and research. Spiking neural networks are artificial neural networks that process information based on discrete neural pulses. Thanks to their good biological rationality, they can well imitate the working principle of biological neurons. Spiking neural networks encode information into the membrane potential and pulse delay of neurons, and use pulses to achieve efficient and low-cost information transmission and processing.

[0004] Most of the existing bionic sensor units need to use certain external circuits to convert external stimuli into signals that can be processed by pulse neural networks. These circuits are usually complex and result in high power consumption.

[0005] Ordinary sensors output analog electrical signals, and communication between the two requires relatively complex conversion circuits, which often results in complex system hardware structure, high power consumption, large amount of data transmitted, and low efficiency. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a new sensor architecture system based on memristor, which can effectively solve the problems of complex system hardware structure, high power consumption, large amount of data transmitted and low efficiency in the prior art.

[0007] To achieve the above-mentioned purpose, the novel sensor architecture system based on memristor described in the present invention includes a power supply, a plurality of sensor pulse output units and an ASIC chip, wherein the ASIC chip includes a low voltage drop linear regulator, a bandgap reference, a time digital converter, a parallel-to-serial module, an oscillator, a phase-locked loop, a plurality of comparators and a plurality of D flip-flops; the sensor pulse output unit includes a sensor based on memristor;

[0008] One sensor corresponds to one comparator and one D flip-flop, the output end of the sensor is connected to the input end of the corresponding comparator, the output end of the comparator is connected to the input end of the corresponding D flip-flop, the output end of each D flip-flop is connected to the input end of the time digital converter, and the output end of the time digital converter is connected to the parallel-to-serial module;

[0009] The output end of the oscillator is connected to the input end of the phase-locked loop, the first output end of the phase-locked loop is connected to the reference clock input end of the time-to-digital converter, the second output end of the phase-locked loop is connected to the reference clock input end of the parallel-to-serial module, the power supply is connected to the input end of the low-voltage difference linear regulator, the output end of the low-voltage difference linear regulator is connected to the input end of the bandgap reference circuit, and the output end of the bandgap reference circuit is connected to the reference voltage input end of the comparator.

[0010] The sensor is a capacitive sensor.

[0011] The sensor is a resistance type sensor.

[0012] The memristor is a Mott memristor.

[0013] The low dropout linear regulator consists of a high-gain wide-input operational amplifier, a power tube and a feedback unit.

[0014] The bandgap reference circuit adopts a self-biasing structure.

[0015] The comparator is a static comparator with rail-to-rail input.

[0016] The comparator is a windowed hysteresis comparator.

[0017] The present invention has the following beneficial effects:

[0018] The novel sensor architecture system based on memristor described in the present invention adopts a sensor based on memristor during specific operation, filters and shapes the triangular pulse signals output by several sensors through a comparator to reduce phase noise, and then sends them to a time-to-digital converter for simultaneous processing, thereby avoiding the addition of a more complex conversion circuit, solving the problems of complex system hardware structure, high power consumption, large amount of data transmission and low efficiency in the prior art, and finally converting the digital codes converted by the multi-channel signals into a parallel-to-serial output encoding format through a parallel-to-serial module to reduce the excessive I / O interfaces required for the multi-channel signals, with a simple structure, convenient operation and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is the principle diagram of the present invention;

[0020] Figure 2 It is the structural diagram of the sensor pulse output unit;

[0021] Figure 3 This is a diagram of the triangular pulse signal output by the sensor pulse output unit;

[0022] Figure 4 It is a circuit diagram of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only an embodiment of a part of the present invention, not all embodiments, and is not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concepts disclosed in the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0024] The accompanying drawings show schematic diagrams of structures according to embodiments disclosed in the present invention. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0025] refer to Figures 1 to 4The novel sensor architecture system based on memristor of the present invention comprises a power supply VBAT, a plurality of sensor pulse output units and an ASIC chip, wherein the ASIC chip comprises a low voltage dropout linear regulator LDO, a bandgap reference BGR, a time digital converter TDC, a parallel-to-serial module PtS, an oscillator OSC, a phase-locked loop PLL, a plurality of comparators T and a plurality of D flip-flops D; the sensor pulse output unit comprises a sensor based on memristor;

[0026] The sensing pulse output unit includes a sensor based on a memristor, wherein the sensor is a capacitive sensor or a resistive sensor, and the memristor is a Mott memristor.

[0027] One of the sensors corresponds to a comparator T and a D flip-flop D, the output end of the sensor is connected to the input end of the corresponding comparator T, the output end of the comparator T is connected to the input end of the corresponding D flip-flop D, the output end of each D flip-flop D is connected to the input end of the time digital converter TDC, and the output end of the time digital converter TDC is connected to the parallel-to-serial module PtS;

[0028] The output end of the oscillator OSC is connected to the input end of the phase-locked loop PLL, the first output end of the phase-locked loop PLL is connected to the reference clock input end of the time-to-digital converter TDC, the second output end of the phase-locked loop PLL is connected to the reference clock input end of the parallel-to-serial module PtS, the power supply VBAT is connected to the input end of the low-voltage dropout linear regulator LDO, the output end of the low-voltage dropout linear regulator LDO is connected to the input end of the bandgap reference circuit BGR, and the output end of the bandgap reference circuit BGR is connected to the reference voltage input end of the comparator T.

[0029] The working principle of the present invention is:

[0030] The triangular wave signals output by each sensor enter the corresponding comparator T for de-jittering and shaping, and the triangular wave signals containing large noise are converted into square wave signals, and divided by two to reduce their phase noise. Then, they are simultaneously input into the time-to-digital converter TDC with n channels after passing through the D trigger D, and are synchronously quantized according to the reference clock frequency by the time-to-digital converter TDC to obtain the quantized digital code for output; the multi-channel parallel data output by the time-to-digital converter TDC is converted into serial data through the parallel-to-serial module PtS and then output.

[0031] In the entire architecture, the low-dropout linear regulator LDO is used to convert the input voltage source into an ultra-low noise voltage that can be used for the operation of various modules inside the chip; the oscillator OSC is used to generate a stable serial port output clock, which can be generated inside the ASIC chip or connected to an external crystal oscillator device, and then provided to the time-to-digital converter TDC and the parallel-to-serial module PtS as the reference clock for quantization and output respectively through the phase-locked loop PLL; the bandgap reference circuit BGR is used to provide the necessary voltage reference and current bias for the analog circuit part of the entire ASIC chip.

[0032] The time digital converter (TDC) is mainly composed of n+1 counters, where the n+1th counter is based on f. ref1 The reference counter is used as the reference frequency benchmark; the first n counters are the Mott counters of the n-channel input; the n+1 counters count simultaneously, and when the reference counter counts, all input frequency signals are reset and the counter value is locked; at the same time, the values ​​of the first n Mott counters are output. The biggest advantages of this structure are: 1) all-digital design; 2) it can quantize n input frequency signals at the same time.

[0033] The time-to-digital converter (TDC) quantizes multiple input frequency signals simultaneously, but it consumes too many I / O interfaces for data output. Therefore, adding a parallel-to-serial module (PtS) can greatly reduce the I / O overhead. The parallel-to-serial data communication uses the SPI protocol. When the CS_N signal becomes low, data transmission begins. On the basis of the multi-bit data output by the time-to-digital converter (TDC), a start bit, a stop bit, and multi-bit address bits are added, and the serial port output is performed according to the reference clock.

[0034] It should be noted that the number of sensors in the present invention is one or more.

[0035] The sensor is a memristor-based sensor, and the memristor may be a Mott memristor, or other types of circuit structures, and the entire unit can generate a pulse signal;

[0036] The power supply part in the signal parallel processing unit can be designed independently. The power supply module in this structure provides power and reference for the signal processing unit inside the ASIC chip. The low-dropout linear regulator LDO is composed of a high-gain wide-input operational amplifier, a power tube and a feedback unit. The bandgap reference circuit BGR adopts a self-biased structure to save excess circuit overhead. The m-bit trimming technology (for example, m=4 can achieve 16 steps of fine adjustment capability) is added to generate accurate reference voltage; and by increasing the n-bit EN control terminal for feedback coefficient adjustment, the required dynamically adjustable reference voltage value can be generated through later debugging, and a wider and more flexible sensor impedance range can also be matched during application.

[0037] The comparator T can adopt a static comparator with rail-to-rail input or a hysteresis comparator with a window. By comparing with the dynamically adjustable reference voltage value generated by the bandgap reference circuit BGR, the signal generated by the sensor is converted into a square wave signal, and then its phase noise is reduced through multi-channel frequency division to achieve better quantization effect.

[0038] The time-to-digital converter (TDC) can quantize one or multiple signals at the same time, quantize multiple pulse signals into digital quantities, and output them through the serial port in a preset coding format.

[0039] A global initialization function is added to the time-to-digital converter TDC, which can adaptively match the maximum impedance value of the external sensor and set the corresponding minimum quantization frequency. When the system is powered on for the first time, after the sensor is connected, the sensor is at a high resistance value and the frequency signal of the oscillator OSC is at a low frequency. When the external enable signal EN becomes a high level, global initialization begins, and the quantization data of the signal frequency at this time is written into the register inside the chip, and the minimum quantization data is output. After the initialization is completed, the time-to-digital converter TDC enters a normal working state, and the quantization data output by the time-to-digital converter TDC is the difference between the input frequency at this time and the initial frequency.

[0040] The present invention converts the digital codes converted from multiple signals into parallel-to-serial output by a parallel-to-serial module PtS, so as to reduce the excessive I / O interfaces required by the multiple signals. The parallel-to-serial module PtS waits for the time digital converter TDC to send a quantization completion signal. After receiving the digital completion signal, the parallel-to-serial module PtS starts to work, outputs the multiple digital codes in sequence according to a fixed address or an externally specified address, adds a start bit, an address bit and a stop bit on the basis of the quantized digital code, and when the n-th signal is output, the cyclic output of the n-way quantized data is completed, and the parallel-to-serial module PtS enters an idle state, waiting for the next quantization completion signal of the time digital converter TDC.

[0041] The examples described above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the overall architecture of the present invention shall be included in the protection scope of the present invention.

Claims

1. A novel sensor architecture system based on memristor, characterized in that: It includes a power supply (VBAT), several sensor pulse output units and an ASIC chip, wherein the ASIC chip includes a low voltage dropout linear regulator (LDO), a bandgap reference (BGR), a time digital converter (TDC), a parallel-to-serial module (PtS), an oscillator (OSC), a phase-locked loop (PLL), several comparators (T) and several D flip-flops (D); the sensor pulse output unit includes a sensor based on a memristor; One sensor corresponds to one comparator (T) and one D flip-flop (D), the output end of the sensor is connected to the input end of the corresponding comparator (T), the output end of the comparator (T) is connected to the input end of the corresponding D flip-flop (D), the output end of each D flip-flop (D) is connected to the input end of the time digital converter (TDC), and the output end of the time digital converter (TDC) is connected to the parallel-to-serial module (PtS); The output end of the oscillator (OSC) is connected to the input end of the phase-locked loop (PLL), the first output end of the phase-locked loop (PLL) is connected to the reference clock input end of the time-to-digital converter (TDC), the second output end of the phase-locked loop (PLL) is connected to the reference clock input end of the parallel-to-serial module (PtS), the power supply (VBAT) is connected to the input end of the low-dropout linear regulator (LDO), the output end of the low-dropout linear regulator (LDO) is connected to the input end of the bandgap reference circuit (BGR), and the output end of the bandgap reference circuit (BGR) is connected to the reference voltage input end of the comparator (T).

2. The novel sensor architecture system based on memristor according to claim 1 is characterized in that: The sensor is a capacitive sensor.

3. The novel sensor architecture system based on memristor according to claim 1 is characterized in that: The sensor is a resistance type sensor.

4. The novel sensor architecture system based on memristor according to claim 1 is characterized in that: The memristor is a Mott memristor.

5. The novel sensor architecture system based on memristor according to claim 1 is characterized in that: The low dropout linear regulator (LDO) consists of a high-gain wide-input operational amplifier, a power tube and a feedback unit.

6. The novel sensor architecture system based on memristor according to claim 1, characterized in that: The bandgap reference circuit (BGR) adopts a self-biasing structure.

7. The novel sensor architecture system based on memristor according to claim 1 is characterized in that: The comparator (T) is a static comparator with rail-to-rail input.

8. The novel sensor architecture system based on memristor according to claim 1, characterized in that: The comparator (T) is a hysteresis comparator with a window.

9. The novel sensor architecture system based on memristor according to claim 1, characterized in that: A time-to-digital converter (TDC) is capable of processing one or more sensor signals.

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