Facilitating page table entry (PTE) maintenance in processor-based devices

Abstract

Maintaining page table entries (PTEs) in a processor-based device is disclosed. In this regard, the processor-based device includes processing elements (PEs) configured to support two new coherency states: walker-readable (W) and modified walker-accessible (M W ). The W coherency state indicates that read accesses by a hardware table walker (HTW) to a corresponding coherency granule are permitted, but all write operations and all read operations by non-HTW agents are forbidden. The M W coherency state indicates that cached copies of the coherency granule that are only visible to HTWs can exist in other caches. In some embodiments, each PE is further configured to support a special page table entry (SP-PTE) field store instruction to modify the SP-PTE field of a PTE to indicate to a local cache of the PE that a corresponding coherency granule should transition to the M W state and to indicate to remote local caches that copies of the coherency granule should update their coherency state.

Description

Technical Field

[0001] The technology disclosed herein relates to page tables in processor-based devices, and more specifically, to mechanisms for updating page table entries more efficiently. Background Technology

[0002] Page tables are data structures used by modern processor-based devices to provide virtual memory functionality. A page table provides page table entries (PTEs) that map virtual memory addresses to their corresponding physical memory addresses (i.e., addresses of memory locations within system memory). When a processor-based device needs to translate a virtual memory address to a physical memory address, it uses a hardware table walker (HTW) to access the page table to locate the page table entry associated with the virtual memory address and then reads the corresponding physical memory address from the page table entry. The HTW, or the PTE recently accessed by the software, can also be cached by the processor-based device in a translation lookup buffer (TLB) for later reuse without repeating the translation process. By using page tables to implement virtual memory functionality, processor-based devices enable software processes to access secure memory spaces that are isolated from each other and, conceptually, can collectively exceed the available physical memory.

[0003] Each PTE includes fields used by the hardware, such as bits representing pointers to other page tables, permission bits, memory attributes, etc., as non-limiting examples. Other fields within a PTE (referred to herein as "SP-PTE fields") are used only by the software and, as non-limiting examples, may include bits for tracking page counts and / or page age, managing page table updates, etc. Therefore, the maintenance and management of page tables by a processor-based device may involve reading and writing SP-PTE fields that are not used by the HTW and / or are unrelated to virtual-to-physical address translation.

[0004] As long as a local copy of a specific PTE exists in the TLB of a processor-based device, the HTW ignores modifications to the SP-PTE field and continues to access the PTE as needed. However, performance issues can arise if the TLB is too small to hold a working set of PTEs. While updates to the SP-PTE field are transparent to the HTW, PTEs held in the local cache may be invalidated when the SP-PTE field is modified by software. Therefore, if the PTE required for virtual-to-physical address translation does not exist in the TLB, and the cache has invalidated its copy of the PTE due to a modification to the SP-PTE field, the processor-based device must perform a memory read operation to retrieve a copy of the PTE from system memory. This performance issue can be exacerbated in processor-based devices that include multiple processing units (PEs) all attempting to access the same coherent granularity (i.e., the smallest memory block maintaining coherence, corresponding to a cache line) containing the PTEs within their local caches.

[0005] Therefore, a more efficient mechanism is desired for maintaining PTE while avoiding excessive cache contention. Summary of the Invention

[0006] The exemplary embodiments disclosed herein include facilitating page table entry (PTE) maintenance in a processor-based device. In one exemplary embodiment, the processor-based device includes a plurality of processing elements (PEs), each configured to support two new consistency states: traverser readable (W) and modified traverser accessible (M). W The W consistency state indicates that the corresponding consistency granule is consistent for the purpose of being read by the Hardware Table Worn (HTW), but not for other purposes. Therefore, read access to the consistency granule with the W consistency state is permitted by the Hardware Table Worn (HTW), but all write operations and all read operations to the consistency granule by non-HTW agents are prohibited. W The consistency state indicates that a cached copy of the consistency granularity, visible only to the HTW (i.e., with a consistency state W), may exist in other caches. Furthermore, M W The consistency status indicates that when a consistent particle is later evicted from the PE's local cache, the PE holding the corresponding consistent particle is responsible for updating the system memory. In some embodiments, each PE can be configured to support storing instructions using a special page table entry (SP-PTE) field to modify the SP-PTE field of the PTE, and to indicate to the PE's local cache that the corresponding consistent particle should be transformed into an M. WThe state is then displayed, and the corresponding replicas of the consistency granules are instructed to update their consistency state in the remote local cache. In such an embodiment, M W The consistency status indicates that the PE is allowed to execute SP-PTE field storage instructions to update the SP-PTE field without making an additional bus request.

[0007] In some embodiments, the SP-PTE field store instruction can be a custom store instruction or a custom compare-swap instruction. Some embodiments may specify that the SP-PTE field store instruction is a regular memory store instruction that targets an address range associated with a page table and modifies only the SP-PTE field. In such embodiments, a processor-based device can automatically detect regular memory store instructions and treat them as SP-PTE field store instructions, as described herein. Some embodiments may also specify that each PE is further configured to support new bus requests, including: an rd_e_w (exclusive read, traverser) bus request indicating that the SP-PTE field is being updated and the PE does not hold the corresponding consistency granule; an rd_x_w (for any read, traverser) bus request indicating that the PE is performing a read on behalf of HTW and, if necessary, can accept a copy of the corresponding consistency granule in a W consistency state; and a prex_w (promotion to exclusive, traverser) bus request indicating that the PE has a shared copy of the corresponding consistency granule and wishes to manage the SP-PTE field.

[0008] In another exemplary embodiment, a processor-based device is provided. The processor-based device includes a plurality of physical processes (PEs) communicatively coupled to each other via an interconnect bus. Each PE includes an execution pipeline, system memory, and a local cache. The pipeline includes a decoding stage and an execution stage, and the system memory includes page tables. A first PE of the plurality of PEs is configured to use the decoding stage of the execution pipeline to decode a Special Page Table Entry (SP-PTE) field store instruction. The first PE is also configured to use the execution stage of the execution pipeline to execute the SP-PTE field store instruction to modify the SP-PTE field of a PTE cached in a corresponding coherence granule in the first PE's local cache. A second PE of the plurality of PEs is configured to receive a bus request for a coherence granule from the first PE via the interconnect bus. The second PE is also configured to update the coherence state of a copy of the coherence granule in the second PE's local cache to an traverser-readable (W) coherence state, indicating that the copy of the coherence granule can only be read by the hardware table traverser (HTW) of the second PE.

[0009] In another exemplary embodiment, a method for facilitating PTE maintenance is provided. The method includes decoding a Special Page Table Entry (SP-PTE) field storage instruction using a decoding phase of the execution pipeline of a first processing element (PE) of a plurality of PEs of a processor-based device. The method also includes executing the SP-PTE field storage instruction to modify the SP-PTE field of a PTE in a page table in the system memory of the processor-based device, wherein the PTE is cached in a coherent granule corresponding to the PTE in the local cache of the first PE. The method further includes receiving a bus request for a coherent granule from the first PE via an interconnect bus by a second PE of the plurality of PEs. The method further includes updating the coherence state of a copy of the coherent granule in the local cache of the second PE to an traverser-readable (W) coherence state, indicating that the copy of the coherent granule can only be read by the hardware table traverser (HTW) of the second PE.

[0010] In another exemplary embodiment, a non-transient computer-readable medium is provided. The computer-readable medium stores computer-executable instructions thereon that, when executed by a processor, cause the processor to: decode a Special Page Table Entry (SP-PTE) field storage instruction. The computer-executable instructions further cause the processor to: execute an SP-PTE field storage instruction to modify the SP-PTE field of a PTE in a page table in system memory, wherein the PTE is cached in a coherent granule corresponding to that PTE in the local cache of a first PE among a plurality of PEs. The computer-executable instructions further cause the processor to: receive a bus request for a coherent granule from the first PE via an interconnect bus from a second PE among a plurality of PEs. The computer-executable instructions further cause the processor to: update the coherence state of a copy of the coherent granule in the local cache of the second PE to an traverser-readable (W) coherence state, indicating that the copy of the coherent granule can only be read by the hardware table traverser (HTW) of the second PE.

[0011] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement additional embodiments thereof. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] Figure 1 This is a schematic diagram of an exemplary processor-based device that includes a plurality of processing elements (PEs) configured to facilitate page table entry (PTE) maintenance;

[0014] Figure 2 It is a diagram showing the process of... Figure 1 A flowchart of exemplary logic for the first PE application of a processor-based device, for executing special PTE (SP-PTE) field storage instructions and updating the consistency state of the target consistency granularity;

[0015] Figure 3 It is a diagram showing the process of... Figure 1 A flowchart of exemplary logic for a second PE application of a processor-based device, used to respond to a sniff bus request and update the consistency state of a shared copy of the target consistency granule;

[0016] Figure 4 It is a diagram showing the process of... Figure 1 A flowchart of exemplary logic for a second PE application of a processor-based device, for performing a read operation on a shared copy of the target consistency granularity by the hardware table traverser (HTW) of the second PE;

[0017] Figure 5 The diagram illustrates the response to Figure 1 A graph of consistency state transitions for consistency granularities, executed by the first PE of a processor-based device, which stores SP-PTE field instructions.

[0018] Figure 6 The diagram illustrates the response to Figure 1 A diagram illustrating the consistency state transitions for consistency granularities as the first PE of a processor-based device performs regular memory storage operations.

[0019] Figure 7 The diagram illustrates the response to Figure 1 A diagram illustrating the consistency state transitions of a local copy of a consistent granularity during the HTW execution of a read operation by the second PE of a processor-based device.

[0020] Figure 8 The diagram illustrates the response to Figure 1 A diagram illustrating the consistency state transitions of a local copy of a processor-based device's second PE non-HTW agent read operation for consistency granularity.

[0021] Figure 9A and Figure 9B It's a diagram. Figure 1 A flowchart illustrating exemplary operation of the first PE of a processor-based device, for using an iterator-readable (W) consistent state and, in some embodiments, a modified iterator-accessible (M) state. W Consistent state facilitates PTE maintenance;

[0022] Figure 10 It's a diagram. Figure 1A flowchart of further exemplary operation of the first PE of the processor-based device for issuing bus commands to determine whether a shared copy of the consistency granule, which is the target of the SP-PTE field storage instruction, exists in other PEs;

[0023] Figure 11 It's a diagram. Figure 1 A flowchart of a further exemplary operation of the second PE of a processor-based device for allowing HTW reads of a shared copy of a consistent granular state having a consistency state of W;

[0024] Figure 12 It's a diagram. Figure 1 A flowchart illustrating further exemplary operation of the second PE of the processor-based device for disabling reads performed by a non-HTW agent; and

[0025] Figure 13 It is an exemplary processor-based device (such as) configured to facilitate PTE maintenance. Figure 1 A block diagram of a processor-based device. Detailed Implementation

[0026] The exemplary embodiments disclosed herein include facilitating page table entry (PTE) maintenance in a processor-based device. In one exemplary embodiment, the processor-based device includes a plurality of processing elements (PEs), each configured to support two new consistency states: traverser readable (W) and modified traverser accessible (M). W The W consistency state indicates that the corresponding consistency granule is consistent for the purpose of being read by the Hardware Table Worn (HTW), but not for other purposes. Therefore, read access to the consistency granule with the W consistency state is permitted by the Hardware Table Worn (HTW), but all write operations and all read operations to the consistency granule by non-HTW agents are prohibited. W The consistency state indicates that a cached copy of the consistency granularity, visible only to the HTW (i.e., with a consistency state W), may exist in other caches. Furthermore, M W Consistency Status Indication: When a consistent particle is later evicted from the PE's local cache, the PE holding the corresponding consistent particle is responsible for updating the system memory. In some embodiments, each PE can be configured to support storing instructions using a special page table entry (SP-PTE) field to modify the SP-PTE field of the PTE, and instructing the PE's local cache that the corresponding consistent particle should be transformed into an M. W The state is then displayed, and the corresponding replicas of the consistency granules are instructed to update their consistency state in the remote local cache. In such an embodiment, M WThe consistency status indicates that the PE is allowed to execute SP-PTE field storage instructions to update the SP-PTE field without making an additional bus request.

[0027] in this regard, Figure 1 An exemplary processor-based device 100 is illustrated, which provides a plurality of PEs 102(0)-102(P) for concurrent processing of executable instructions. Each PE among PEs 102(0)-102(P) may include a central processing unit (CPU) having one or more processor cores, or may include an individual processor core including a logical execution unit and associated cache and functional units. Figure 1 In the example, PE 102(0)-102(P) are communicatively coupled via interconnect bus 104, and inter-processor communication (such as sniffing requests and sniffing responses as a non-limiting example) is conducted via interconnect bus 104. In some embodiments, interconnect bus 104 may include components not shown for clarity. Figure 1 Additional components are shown (e.g., bus controller circuitry and / or arbitration circuitry, as non-limiting examples). PE 102(0)-102(P) are also communicatively coupled to system memory 106 and shared cache 108 via interconnect bus 104.

[0028] Figure 1 System memory 106 stores page table 110 containing PTEs 112(0)-112(T). Each PTE in PTEs 112(0)-112(T) represents a mapping from a virtual memory address to a physical memory address in system memory 106 and can be used for virtual-to-physical address translation. PTEs 112(0)-112(T) include corresponding SP-PTE fields 114(0)-114(T) used only by software, and, as a non-limiting example, may include bits for tracking page counts and / or page age, managing page table updates, etc. It should be understood that in some embodiments, PTEs 112(0)-112(T) may include Figure 1 Additional fields not shown in the table, and it should also be understood that, according to some embodiments, page table 110 may be a multi-level page table comprising multiple page tables. Figure 1 Each PE 102(0)-102(P) also includes a corresponding HTW 116(0)-116(P), which embodies the logic for searching page table 110 to locate the PTEs among the multiple PTEs 112(0)-112(T) required to perform virtual-to-physical address translation. HTW 116(0)-116(P) includes corresponding Translation Lookaside Buffers (TLBs) 118(0)-118(P) for caching recently accessed PTEs 112(0)-112(T).

[0029] Figure 1 PE 102(0)-102(P) also includes corresponding execution pipelines 120(0)-120(P), which are configured to execute corresponding instruction streams including computer-executable instructions. Figure 1 In the example, execution pipelines 120(0)-120(P) respectively include fetch stages 122(0)-122(P) for retrieving instructions for execution, decode stages 124(0)-124(P) for converting the fetched instructions into control signals for instruction execution, and execution stages 126(0)-126(P) for actually executing the instructions. It should be understood that some embodiments of PE 102(0)-102(P) may include... Figure 1 The examples illustrate those fewer or more stages.

[0030] Figure 1 PE 102(0)-102(P) also includes a corresponding local cache 128(0)-128(P), each local cache 128(0)-128(P) storing multiple corresponding consistency granules 130(0)-130(C), 130'(0)-130'(C) (in Figure 1 Each of them is labeled "COGRAN". Consistency granules 130(0)-130(C) and 130'(0)-130'(C) represent the smallest memory block for which consistency is maintained, and can also be referred to as "cache line 130(0)-130(C) and 130'(0)-130'(C)". Figure 1 As seen, consistent particles 130(0) and 130'(0) each have corresponding consistent states 132 and 132' (in... Figure 1 Each of these is labeled "CS" to indicate the consistency status of the corresponding consistency granules 130(0) and 130'(0). Although Figure 1 Not shown, but it should be understood that each consistency particle 130(0)-130(C), 130'(0)-130'(C) includes a consistency state that is functionally corresponding to consistency states 132, 132'.

[0031] Coherence granules 130(0)-130(C) and 130'(0)-130'(C) are configured to hold copies of previously fetched data, including, for example, coherence granules corresponding to PTEs among a plurality of PTEs 112(0)-112(T). Thus, for example, if the PTE required for HTW 116(0) to perform virtual-to-physical address translation is not found in TLB 118(0), HTW 116(0) may then attempt to fetch the PTE from one of the coherence granules 130(0)-130(C) of the local cache 128(0) before fetching the PTE from system memory 106. In some embodiments, the local caches 128(0)-128(P) and the shared cache 108 may represent different levels in a cache hierarchy. For example, in such an embodiment, the local cache 128(0)-128(P) can represent a level 2 (L2) cache, while the shared cache 108 can represent a level 3 (L3) cache.

[0032] Figure 1 The processor-based device 100 may encompass any of the following: known digital logic elements, semiconductor circuits, processing cores and / or memory structures, and combinations thereof. The embodiments described herein are not limited to any particular element arrangement, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor sockets or packages. It should be understood that some embodiments of the processor-based device 100 may include, in addition to… Figure 1 Components other than those shown in the diagram. For example, PE 102(0)-102(P) may also include cache controller circuitry for each local cache in local cache 128(0)-128(P), and / or additional memory devices, cache and / or controller circuitry.

[0033] As noted above, as long as a local copy of the specific PTE 112(0)-112(T) required by one of the HTWs 116(0)-116(P) exists in the corresponding TLB 118(0)-118(P), HTW 116(0)-116(P) will ignore modifications to the SP-PTE fields 114(0)-114(T) of PTE 112(0)-112(T), and PTE 112(0)-112(T) will continue to be accessed as needed. However, performance issues may occur if TLB 118(0)-118(P) is too small to hold a working set of PTEs. Although updates to SP-PTE fields 114(0)-114(T) are transparent to HTW 116(0)-116(P), when the software modifies SP-PTE fields 114(0)-114(T), PTEs held in local cache 128(0)-128(P) may be invalidated from local cache 128(0)-128(P). Therefore, if there is no PTE in the TLB 112(0)-112(T) required for virtual-to-physical address translation in the TLB 118(0)-118(P), and the corresponding local cache 128(0)-128(P) has invalidated its copy of PTE 112(0)-112(T) due to the modification of the SP-PTE field 114(0)-114(T), then the corresponding HTW 116(0)-116(P) must perform a memory read operation to obtain a copy of PTE 112(0)-112(T) from the system memory 106. This performance problem can be exacerbated in processor-based devices that include multiple PEs 102(0)-102(P) that attempt to access the same coherent granules (e.g., coherent granules 130(0) and 130'(0)) within their local caches 128(0)-128(P) containing PTEs 112(0)-112(T).

[0034] In this regard, PEs 102(0)-102(P) are each configured to support two new consistency states: traverser readable (W) and modified traverser accessible (M). W The W consistency state indicates that HTW 116(0)-116 is permitted to read (P) the corresponding consistency particles (e.g., consistency particles 130(0)-130(C), 130'(0)-130'(C)), but all write and read operations on the consistency particles by non-HTW agents (such as non-HTW agent 134 of PE 102(P)) are prohibited. WThe consistency state indicates that a cached copy of the consistency granule, visible only to HTW 116(0)-116(P) (i.e., with a consistency state of W), exists in other local caches 128(0)-128(P). Furthermore, M W The consistency status indicates that when a consistent particle is later evicted from its local cache, the PE holding the corresponding consistent particle is responsible for updating the system memory. Each PE 102(0)-102(P) is also configured to support the use of SP-PTE field storage instruction 136 to modify the SP-PTE fields 114(0)-114(T) of PTE 112(0)-112(T) and indicate to the corresponding local cache 128(0)-128(P) that the corresponding consistent particle (e.g., one of the corresponding consistent particles 130(0)-130(C) or 130'(0)-130'(C)) should be transformed into M. W The consistency status is determined, and the remote local caches 128(0)-128(P) are instructed that the copies of the corresponding consistency granules 130(0)-130(C) and 130'(0)-130'(C) should update their consistency status (e.g., consistency status 132, 132'). In some embodiments, the SP-PTE field store instruction 136 may be a custom store instruction or a custom compare-swap instruction, or it may be a regular memory store instruction that targets the address range associated with page table 110 and modifies only the SP-PTE fields (such as SP-PTE fields 114(0)-114(T)). In the latter case, the hardware of the corresponding PEs 102(0)-102(P) can determine that the regular memory store instruction modifies only the SP-PTE fields of the PTEs of page table 110, and can process the regular memory store instruction in response, as described herein.

[0035] In an exemplary operation, the decoding phase 124(0) of the execution pipeline 120(0) of PE 102(0) (“first PE 102(0)”) decodes the SP-PTE field storage instruction 136, which is then executed by the execution phase 126(0) of the execution pipeline 120(0) to modify the SP-PTE field of the PTE (e.g., SP-PTE field 114(0) of PTE 112(0)). In some embodiments, the first PE 102(0) updates the consistency state of the consistency granule corresponding to PTE 112(0) (e.g., consistency state 132 of consistency granule 130(0) in local cache 128(0)) to consistency state M. WThis indicates that a cached copy of consistency granule 130(0), visible only to HTW 116(0)-116(P), exists in one or more local caches in local caches 128(0)-128(P).

[0036] In some embodiments, in response to a first PE 102(0) determining that the consistency granule 130(0) corresponding to PTE 112(0) in local cache 128(0) is shared by one or more local caches 128(0)-128(P) of other PEs 102(0)-102(P) (e.g., local cache 128(P) of PE 102(P)), the consistency state 132 can be updated to M. W For example, if the consistency state 132 of consistency particle 130(0) is in a consistent state of shared modified (O), recently shared (R), or shared clean (S), then PE 102(0) can transmit a prex_w (promoted to exclusive, traverser) bus request 138 via interconnect bus 104 to indicate that the first PE 102(0) has a shared copy of consistency particle 130(0) and seeks the SP-PTE field 114(0) of management PTE 112(0). The first PE 102(0) can then determine whether consistency particle 130(0) is shared by another local cache 128(0)-116(P) based on the response 140 (“PREX_W RESP”) to the prex_w bus request 138. Similarly, if the consistency state 132 of consistency particle 130(0) is in a consistent state that is readable by the traverser (W) or invalid (I), then PE 102(0) can transmit rd_e_w (exclusive read, traverser) bus request 142 via interconnect bus 104 to indicate that the first PE 102(0) is updating the SP-PTE field 114(0) of PTE 112(0) and does not hold a consistent copy of consistency particle 130(0). The first PE 102(0) can then determine whether consistency particle 130(0) is shared by another local cache 128(0)-128(P) based on the response 144 (“RD_E_W RESP”) to rd_e_w bus request 142.

[0037] In some embodiments, the consistency particles 130(0)-130(C) and 130'(0)-130'(C) also include HTW installation indicators, such as HTW installation indicators 146 and 146' (in Figure 1(The text is labeled "HTWII"). HTW installation indicators 146 and 146' indicate whether the corresponding consistency particles 130(0) and 130'(0) are installed in the corresponding local caches 128(0)-128(P) as a result of an HTW request. In such an embodiment, the first PE 102(0) may update the consistency state 132 of the consistency particle 130(0) in response to determining that the HTW installation indicator 146 is set and the SP-PTE field storage instruction 136 is a regular memory storage instruction that only modifies the SP-PTE field 114(0) of the PTE 112(0).

[0038] Upon receiving a bus request (e.g., prex_w bus request 138 or rd_e_w bus request 142) from the first PE 102(0), the second PE 102(P) may transmit a response (e.g., response 140 or response 144) indicating that a copy of the consistency particle (i.e., consistency particle 130'(0) or "copy 130'(0)") is cached in the local cache 128(P). The second PE 102(P) then updates the consistency state 132' of copy 130'(0) to a consistency state W to indicate that copy 130'(0) can only be read by the HTW 116(P) of the second PE 102(P).

[0039] Subsequently, the second PE 102(P) can determine that HTW 116(P) is seeking to read replica 130'(0) and can also determine that replica 130'(0) has a consistent state W. The second PE 102(P) can then allow HTW 116(P) to read replica 130'(0). However, if the second PE 102(P) determines that a non-HTW agent is seeking to read replica 130'(0) (or any agent (HTW or non-HTW) is seeking to write to replica 130'(0)) and replica 130'(0) has a consistent state W, the second PE 102(P) will invalidate replica 130'(0) in the local cache 128(P) and process the request to read replica 130'(0) as a cache miss on the local cache 128(P).

[0040] Figure 2 A flowchart 200 is shown according to some embodiments, illustrating a process such as Figure 1 Exemplary logic for the PE application of the first PE 102(0) of the processor-based device 100, for executing SP-PTE field storage instructions and updating the consistency state of consistency granules. Figure 2As seen in the diagram, the PE executes the SP-PTE field store instruction for the consistency granule 130(0) (box 202). The PE's local cache then determines whether the consistency state of the consistency granule is exclusive clean (E) or modified (M) (box 204). If so, the PE can determine that no shared copy of the consistency granule exists (box 206). The PE can also determine that no bus request is required (box 208). Therefore, the consistency granule transitions to the next consistency state M. W Or M (box 210). A consistent granule is a particle that transitions to a consistent state M. W Whether M is selected depends on the specific implementation of the processor-based device 100. For example, in some embodiments, the processor-based device 100 may choose to transition the consistency state of the consistency granules to M, such that any subsequent modifications to the non-SP-PTE fields of the consistency granules will not require a bus request to change the consistency state back to M to complete the write to the non-SP-PTE fields. Other embodiments may choose to always transition to the consistency state M. W .

[0041] If the PE's local cache determines at decision box 204 that the consistency state of the consistency granularity is not E or M, then the local cache next determines whether the consistency state of the consistency granularity is M. W (Box 212). If so, the PE can determine that no copy of the consistent particle with consistent state O, R, or S exists (Box 214). The PE can also determine that no bus request is required (Box 216). Therefore, the consistent particle transitions to the next consistent state M. W (Box 218)

[0042] If the consensus state of the consensus granule determined at decision box 212 is not M W The local cache then determines whether the consistency state of the consistency granule is O, R, or S (box 220). If so, the PE determines that the consistency state of the consistency granule should be upgraded to M. W (Box 222). Therefore, the PE sends a prex_w bus request to any other PE to indicate that the first PE has a shared copy of the consistency particle and seeks to manage the SP-PTE field, which is not visible to the HTW (Box 224). Once a response is received, the PE determines whether the response indicates that the consistency particle is shared (Box 226). If so, the consistency particle transitions to the consistency state M. W (Box 228). Otherwise, the consistent granules are transformed into consistent state M (Box 230).

[0043] If the local cache determines at decision box 220 that the consistency state of the consistency granule is not O, R, or S, then the local cache next determines whether the consistency state is W or I (box 232). If so, the PE can determine that the consistency granule with the consistency state M must be obtained. W The copy of the consistency granule (box 234). Therefore, the PE sends an rd_e_w bus request to any other PE to indicate that the PE is updating the SP-PTE field which is not visible to the HTW and does not hold a consistent copy of the consistency granule (box 236). The process then resumes as described above at box 226. Note that the local cache determines at decision box 232 that the consistency state of the consistency granule is not W or I in the scenario where the effective consistency state is M. W Illegal scenarios that should never occur in the embodiments of E, O, R, S, W, and I (box 238). Note that some embodiments may include more or fewer consistency states than those described herein.

[0044] To illustrate, such as Figure 1 Exemplary logic for the PE application of the second PE 102(P) of the processor-based device 100, Figure 3 Flowchart 300 is provided, which is exemplary logic for responding to bus requests and updating the consistency state of a shared copy of the consistency granule on which SP-PTE field storage instructions have been operated. In some embodiments, the PE receives an rd_e_w bus request for the consistency granule (block 302). The PE's local cache then determines whether the consistency state of the consistency granule is M or M. W (Box 304). If so, the PE transfers the responsibility of updating the memory to the new master (Box 306). The PE indicates in its sniff response that the consistency granules are shared (Box 308). The PE also changes the consistency state of the consistency granules to W (Box 310). If the local cache determines at decision box 304 that the consistency state of the consistency granules is not M or M... W The local cache then determines whether the consistency state of the consistency granules is E (box 312). If yes, processing continues at box 308, as discussed above. If the consistency state is not E, processing resumes at box 314.

[0045] The local cache then determines whether the consistency state of the consistency granule is R, S, or W (box 314). If so, processing continues at box 308, as discussed above. If the local cache determines at decision box 314 that the consistency state is not R, S, or W, then the local cache determines whether the consistency state of the consistency granule is O (box 316). If so, the PE transfers the responsibility of updating memory to the new master (box 318). Processing then continues at box 308, as discussed above. If the local cache determines at decision box 316 that the consistency state of the consistency granule is not O, then the local cache next determines whether the consistency state of the consistency granule is I (box 320). If so, processing continues in the normal manner (box 322). Note that the scenario where the local cache determines at decision box 320 that the consistency state of the consistency granule is not I is when the only valid consistency states are M, M W Illegal scenarios that should never occur in the embodiments of E, O, R, S, W, and I (box 324). Note that some embodiments may include more or fewer consistency states than those described herein.

[0046] In some embodiments, the PE may receive a prex_w bus request for a consistency granularity (box 326). If so, processing continues at box 314, as discussed above.

[0047] Figure 4 Flowchart 400 is shown, illustrating a process such as Figure 1 Exemplary logic for the PE application of the second PE 102(P) of the processor-based device 100, which is used to perform a read operation on a shared copy of the consistent granularity by the HTW. (Example logic follows.) Figure 4 As seen in the diagram, the PE performs an HTW memory read access operation for the consistency granularity (box 402). The PE's local cache then determines whether the consistency state of the consistency granularity is E, M, M. W O, R, S, or W (Box 404). If so, the PE uses data from the local cache to satisfy the HTW read (Box 406). There is also no change to the consistency state of the consistency granularity (Box 408).

[0048] If the local cache determines at decision box 404 that the consistency state of the consistency granularity is not E, M, M WIf the PE determines that the consistency state of the consistent granule is I (Box 410), then the local cache next determines whether the consistency state of the consistent granule is I (Box 410). If yes, the PE sends an rd_x_w bus request (for any read, traverser) indicating that the PE is performing a read operation on behalf of the HTW and can accept a consistent granule in the W consistency state if necessary (Box 412). Based on the response to the rd_x_w bus request, the PE determines whether the consistent granule will be acquired with a consistency state W (Box 414). If yes, the PE sets the consistency state of the consistent granule to W (Box 416). If not, the PE follows the normal rules to set the consistency state of the consistent granule to one of E, M, O, R, or S (Box 418). Note that a scenario where the local cache determines at decision box 410 that the consistency state of the consistent granule is not I is an illegal scenario that should never occur (Box 420).

[0049] Figure 5 The diagram illustrates the response to Figure 1 A diagram 500 illustrates an exemplary consistency state transition for a consistency granule (such as consistency granule 130(0)) by the first PE 102(0) of the processor-based device 100 executing the SP-PTE field storage instruction 136. Figure 5 As seen, if the consistency state 132 of the consistency particle 130(0) is in the initial state M W If no bus request is sent, then the consistency state 132 of consistency granule 130(0) will transition to M. W As indicated by arrow 502. If the consistency state 132 of consistency particle 130(0) is in the initial state M or E, no bus request is sent, and the consistency state 132 of consistency particle 130(0) transitions to M. W Or M, as indicated by arrows 504, 505, 506, and 507. (See above regarding...) Figure 2 The consensus particle 130(0) discussed is the one that transforms into the consensus state M. W M can depend on the specific implementation of the processor-based device 100.

[0050] If the consistency state 132 of consistency particle 130(0) is in the initial state O, R, or S, then the first PE 102(0) sends a prex_w bus request to the other PEs among the plurality of PEs 102(0)-102(P) to indicate that the first PE 102(0) has a shared copy of consistency particle 130(0) and seeks to manage the SP-PTE field which is not visible to HTW 116(0)-116(P). If the response to the prex_w bus request indicates that the shared copy of consistency particle 130(0) is held by the other PEs among the plurality of PEs 102(0)-102(P), then the consistency state 132 transitions to M. W As indicated by arrows 508, 510, and 512. Otherwise, consistency state 132 transitions to M, as indicated by arrows 514, 516, and 518.

[0051] Finally, if the consistency state 132 of consistency particle 130(0) is in initial state W or I, then the first PE 102(0) sends an rd_e_w bus request to the other PEs among the plurality of PEs 102(0)-102(P) to indicate that the first PE 102(0) is updating an SP-PTE field that is not visible to HTW 116(0)-116(P) and does not hold consistency particle 130(0). If the response to the rd_e_w bus request indicates that a shared copy of consistency particle 130(0) is held by another PE among the plurality of PEs 102(0)-102(P), then consistency state 132 transitions to M. W As indicated by arrows 520 and 522. Otherwise, consistency state 132 transitions to M, as indicated by arrows 524 and 526.

[0052] To illustrate the response Figure 1 The first PE 102(0) of the processor-based device 100 performs regular memory storage operations for coherent granularities (such as... Figure 1 The consistency state transition of the consistency particle 130(0)). Figure 6 Diagram 600 is provided. If the consistency state 132 of the consistency particle 130(0) is in the initial state M W Then, the first PE 102(0) sends a prex (promotion to exclusive) bus request to the other PEs among the plurality of PEs 102(0)-102(P) to indicate that the first PE 102(0) has a shared copy of the consensus particle 130(0). The consensus state 132 then transitions to M, as indicated by arrow 602. If the consensus state 132 of the consensus particle 130(0) is in the initial state M or E, no bus request is sent, and the consensus state 132 transitions to M, as indicated by arrows 604 and 606.

[0053] If the consistency state 132 of the consistency particle 130(0) is in the initial state O, R, or S, then the first PE 102(0) sends prex bus requests 102(0)-102(P) to the other PEs among the plurality of PEs to indicate that the first PE 102(0) has a shared copy of the consistency particle 130(0). The consistency state 132 then transitions to M, as indicated by arrows 608, 610, and 612. Finally, if the consistency state 132 of the consistency particle 130(0) is in the initial state W or I, then the first PE 102(0) sends an rd_e (exclusive read) bus request to indicate that the first PE 102(0) does not hold a consistent copy of the consistency particle 130(0). The consistency state 132 then transitions to M, as indicated by arrows 614 and 616.

[0054] Figure 7 The diagram shows the response to Figure 1 The first PE 102(0) of the processor-based device 100 performs a read operation on the HTW 116(0) for a consistency granularity (such as...). Figure 1 A diagram 700 showing the consistency state transition of the consistency particle 130(0)). Figure 7 In the example, if the consistency state 132 of the consistency particle 130(0) is in the initial state M W If the coherence state 132 of the coherence particle 130(0) is in initial state I, then the first PE 102(0) sends an rd_x_w bus request, and the coherence state 132 is appropriately changed to M, E, O, R, S, or W, as indicated by arrow 716.

[0055] Figure 8 Provides graphical responses to non-HTW agents (such as...) Figure 1 A diagram 800 illustrating the consistency state transitions for consistency granularities during read operations of the second PE 102(P) of a processor-based device (non-HTW agent 134). (See diagram 800.) Figure 8 As seen in the diagram, if the consistency state 132' of the consistency particle 130'(0) is in the initial state M W If the coherence state 132' of coherence particle 130'(0) is in the initial state W or I, then no bus request is sent and the coherence state 132' remains unchanged, as indicated by arrows 802, 804, 806, 808, 810, and 812. If the coherence state 132' of coherence particle 130'(0) is in the initial state W or I, then an rd_x bus request is sent, and the coherence state 132' appropriately transitions to M, E, O, R, or S, as indicated by arrows 814 and 816.

[0056] For illustration Figure 1 The first PE 102(0) of the processor-based device 100 is used to facilitate the use of M W Exemplary operations for PTE maintenance of a consistent state. Figure 9A and Figure 9B A flowchart (900) is provided. For clarity, in the description... Figure 9A and Figure 9B Referenced at the time Figure 1 Components. In some embodiments, Figure 9A The operation begins with the first PE 102(0) of the plurality of PEs 102(0)-102(P) installing the coherence particle 130(0) corresponding to PTE 112(0) into the local cache 128(0) of the first PE 102(0) (box 902). The first PE 102(0) can then set the HTW installation indicator 146 for the coherence particle 130(0) to indicate whether the coherence particle 130(0) is installed as a result of an HTW request (box 904). The decoding phase 124(0) of the execution pipeline 120(0) of the processor-based device 100 of the plurality of PEs 102(0)-102(P) then decodes the SP-PTE field store instruction 136 (box 906). The first PE 102(0) then uses the execution stage 126(0) of the execution pipeline 120(0) to execute the SP-PTE field store instruction 136 to modify the SP-PTE field 114(0) of the PTE 112(0) in the page table 110 of the system memory 106 of the processor-based device 100, wherein the PTE 112(0) is cached in the coherence granularity 130(0) corresponding to the PTE 112(0) in the local cache 128(0) of the first PE 102(0) (box 908).

[0057] The second PE 102(P) receives a bus request (as a non-limiting example, such as prex_w bus request 138 or rd_e_w bus request 142) for the coherence particle 130(0) from the first PE 102(0) via interconnect bus 104 (box 910). In some embodiments, the second PE 102(P) transmits a response to the bus request (e.g., response 140 or response 144 as a non-limiting example) to the first PE 102(0) via interconnect bus 104 to indicate that a copy 130'(0) of the coherence particle 130(0) is cached in the local cache 128(P) of the second PE 102(P) (box 912). Processing is then performed on the first PE 102(P). Figure 9B Continue at box 914.

[0058] Now for reference Figure 9B The second PE 102(P) then updates the consistency state 132' of the copy 130'(0) of the consistency particle 130(0) in the local cache 128(P) of the second PE 102(P) to a consistency state W, indicating that the copy 130'(0) of the consistency particle 130(0) can only be read by the HTW (such as HTW 116(P)) of the second PE 102(P) (box 914). In some embodiments, the first PE 102(0) may determine whether the consistency particle 130(0) corresponding to PTE 112(0) in the local cache 128(0) of the first PE 102(0) is shared by one or more local caches 128(1)-128(P) of one or more other PEs 102(1)-102(P) (box 916). If the consistency particle 130(0) is not shared by one or more local caches 128(1)-128(P), the process continues in the normal manner (box 918). However, if the first PE 102(0) determines at decision box 910 that the consistency particle 130(0) is shared by one or more local caches 128(1)-128(P) (or the first PE 102(0) does not perform the operation of decision box 916), then the first PE 102(0) updates the consistency state 132 of the consistency particle 130(0) corresponding to PTE 112(0) in the local cache 128(0) of the first PE (102(0)) to the consistency state M. W This indicates that a cached copy of the consistency particle 130(0), visible only to the HTW, may exist in one or more local caches 128(1)-128(P) of one or more corresponding other PEs 102(1)-102(P) among multiple PEs 102(0)-102(P) (box 920). In some embodiments, in response to determining that the HTW installation indicator 146 for consistency particle 130(0) is set and the SP-PTE field store instruction 136 is a regular memory store instruction that only modifies the SP-PTE field 114(0) of PTE 112(0), the consistency state 132 is updated to the consistency state M. W The operation in box 914 is performed (box 922).

[0059] Figure 10 A flowchart 1000 according to some embodiments is provided, illustrating... Figure 1Further exemplary operation of the first PE 102(0) of the processor-based device 100, which is used to send a bus command to determine whether a shared copy of the consistency granule 130(0), which is the target of the SP-PTE field storage instruction 136, exists in the other PEs 102(1)-102(P) (and therefore, the other PEs 102(1)-102(P) need to set their shared copies to a consistent state W). For clarity, in the description Figure 10 Referenced at the time Figure 1 Components. In Figure 10 In this process, the operation begins with the first PE 102(0) determining the consistency state 132 (box 1002) of the consistency particle 130(0) corresponding to PTE 112(0) in its local cache 128(0). If the first PE 102(0) determines at decision box 1002 that the consistency particle 130(0) corresponding to PTE 112(0) in its local cache 128(0) is in a consistency state O, R, or S, then the first PE 102(0) transmits a prex_w bus request 138 via the interconnect bus 104 of the processor-based device 100, which indicates that the first PE 102(0) has a shared copy 130'(0) of the consistency particle 130(0) and seeks to manage the SP-PTE field 114(0) of PTE 112(0). However, if the first PE 102(0) determines at decision box 1002 that the consistency particle 130(0) corresponding to PTE 112(0) in its local cache 128(0) is in a consistent state W or I, then the first PE 102(0) transmits an rd_e_w bus request 142 indicating that the first PE 102(0) is updating the SP-PTE field 114(0) of PTE 112(0) and does not hold a consistent copy 130'(0) of the consistency particle 130(0) (box 1006). In the scenario represented by boxes 1004 and 1006, as described above regarding Figure 9A As described in block 910, the bus request received by the second PE 102(P) may include prex_w bus request 128 or rd_e_w bus request 142, respectively.

[0060] Figure 11 A flowchart 1100 according to some embodiments is provided, illustrating... Figure 1Further exemplary operation of the second PE 102(P) of the processor-based device 100, which is used to allow HTW reads of a shared copy 130'(0) of the consistent granule 130'(0) having a consistent state W. For clarity, in the description Figure 11 Referenced at the time Figure 1 Components. In Figure 11 In this process, the operation begins with the local cache 128(P) of the second PE 102(P) determining that the HTW 116(P) of the second PE 102(P) seeks to read a copy 130'(0) of the consistent particle 130(0) (box 1102). The local cache 128(P) of the second PE 102(P) then determines that the copy 130'(0) of the consistent particle 130(0) has a consistent state W (box 1104). In response to determining that the copy 130'(0) of the consistent particle 130(0) has a consistent state W, the local cache 128(P) of the second PE 102(P) allows the HTW 116(P) to read the copy 130'(0) of the consistent particle 130(0) (box 1106).

[0061] For illustration Figure 1 Further exemplary operation of the second PE of the processor-based device, Figure 12 Flowchart 1200 is provided, an exemplary operation for preventing non-HTW agents from reading the shared copy 130'(0) of the consistency granule 130(0) having a consistent state W. For clarity, in the description Figure 12 Referenced at the time Figure 1 Components. Figure 12 The operation begins when the local cache 128(P) of the second PE 102(P) determines that the non-HTW agent 134 of the second PE 102(P) seeks to read a copy 130'(0) of the consistent granule 130(0) (box 1202). The local cache 128(P) of the second PE 102(P) determines that the copy 130'(0) of the consistent granule 130(0) has a consistent state W (box 1204). In response to determining that the copy 130'(0) of the consistent granule 130(0) has a consistent state W, the local cache 128(P) performs a series of operations (box 1206). The local cache 128(P) invalidates the copy 130'(0) of the consistent granule 130(0) (box 1208). The local cache 128(P) then processes the request to read the copy 130'(0) of the consistent granule 130(0) as a cache miss (box 1210). It should be understood that in some embodiments, the local cache 128(P) also prohibits all memory storage operations on the copy 130'(0) of the consistency granule 130(0) having a consistent state W.

[0062] Figure 13 This is an example of a processor-based device (such as) that provides facilitated PTE maintenance. Figure 1 A block diagram of a processor-based device 100) 1300. The processor-based device 1300 may be included in an electronic board such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing board, a mobile device, or any other device, and may represent one or more circuits in, for example, a server or a user's computer. In this example, the processor-based device 1300 includes a processor 1302. The processor 1302 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc., and may correspond to... Figure 1 PE 102(0)-102(P). Processor 1302 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 1302 includes an instruction cache 1304 and instruction processing circuitry 1310 for temporary fast access memory storage of instructions. Instructions fetched or prefetched from memory such as system memory 1308 via system bus 1306 are stored in instruction cache 1304. Instruction processing circuitry 1310 is configured to process instructions fetched into instruction cache 1304 and process the instructions for execution.

[0063] Processor 1302 and system memory 1308 are coupled to system bus 1306 (corresponding to Figure 1 The interconnect bus 104 can interconnect peripheral devices included in the processor-based device 1300. It is well known that the processor 1302 communicates with these other devices by exchanging address, control, and data information on the system bus 1306. For example, the processor 1302 can transmit bus transaction requests to the memory controller 1312 in the system memory 1308, which is an example of a peripheral device. Although... Figure 13 Not shown, but multiple system buses 1306 may be provided, each forming a different architecture. In this example, memory controller 1312 is configured to provide memory access requests to memory array 1314 in system memory 1308. Memory array 1314 includes an array of storage bit cells for storing data. As a non-limiting example, system memory 1308 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0064] Other devices can be connected to system bus 1306. For example... Figure 13As illustrated, these devices may include, for example, system memory 1308, one or more input devices 1316, one or more output devices 1318, modem 1324, and one or more display controllers 1320. The input devices 1316 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 1318 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 1324 may be any device configured to allow data exchange to and from network 1326. Network 1326 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetexts. TM Networks and the Internet. Modem 1324 can be configured to support any type of communication protocol required. Processor 1302 can also be configured to access multiple display controllers 1320 via system bus 1306 to control information sent to one or more displays 1322. The multiple displays 1322 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0065] Figure 13 The processor-based device 1300 may include a set of instructions 1328, which may be encoded using an arrival-based explicit consumer naming model for execution by the processor 1302 for any application desired according to the instructions. The instructions 1328 may be stored in system memory 1308, processor 1302, and / or instruction cache 1304, as an example of non-transient computer-readable medium 1330. The instructions 1328 may also reside wholly or at least partially in system memory 1308 and / or in processor 1302 during their execution. The instructions 1328 may also be transmitted or received over network 1326 via modem 1324, such that network 1326 includes computer-readable medium 1330.

[0066] Although computer-readable medium 1330 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions 1328. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform any or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0067] The embodiments disclosed herein include various steps. These steps can be formed by hardware components or embodied by machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with these instructions to perform the steps. Alternatively, these steps can be performed by a combination of hardware and software.

[0068] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.) and so on.

[0069] Unless otherwise explicitly stated and apparent from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulate data and memory represented as physical (electronic) quantities within registers of a computer system and transform them into other data similarly represented as physical quantities within computer system memory or registers or other such information storage, transmission, or display devices.

[0070] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will become apparent from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0071] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable instruction medium, and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How this functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of these embodiments.

[0072] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0073] The embodiments disclosed herein can be embodied in hardware and instructions, which are stored in hardware and may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0074] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussion. The described operations can be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0075] Unless otherwise expressly stated, any method described herein is not intended to be construed as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually state the order in which its steps are followed, or if the claims or description do not otherwise specifically state that these steps are restricted to a particular order, then no particular order is to be inferred.

[0076] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments in conjunction with the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A processor-based device comprising a plurality of processing elements (PEs) communicatively coupled to each other via an interconnect bus, each PE comprising: The execution pipeline includes a decoding phase and an execution phase; System memory, including page tables; as well as Local cache; The first PE among the plurality of PEs is configured as follows: The decoding phase of the execution pipeline is used to decode the special page table entry SP-PTE field storage instruction; and The execution phase of the execution pipeline is used to execute the SP-PTE field storage instruction to modify the SP-PTE field of the PTE, which is cached in the local cache of the first PE in the corresponding consistency granularity of the PTE; as well as The second PE among the plurality of PEs is configured as follows: Receive bus requests for the coherence granules from the first PE via the interconnect bus; as well as The consistency state of the copy of the consistency granule in the local cache of the second PE is updated to a consistency state that is readable by the traverser W, indicating that the copy of the consistency granule can only be read by the hardware table traverser HTW of the second PE.

2. The processor-based device of claim 1, wherein the second PE of the plurality of PEs is configured to: in response to receiving a bus request from the first PE for the coherent granule, transmit a response to the bus request to the first PE via the interconnect bus, the response indicating that the copy of the coherent granule is cached in the local cache of the second PE.

3. The processor-based device according to claim 1, wherein the second PE of the plurality of PEs is further configured to: The second PE's local cache determines that the second PE's HTW seeks to read the copy of the consistency granules; The local cache of the second PE determines that the replica of the consistency granule has a consistency state of W; as well as In response to determining that the replica of the consistent particle has a consistent state of W, the local cache of the second PE allows the HTW to read the replica of the consistent particle.

4. The processor-based device according to claim 1, wherein the second PE of the plurality of PEs is further configured to: The local cache of the second PE determines that the non-HTW agent of the second PE seeks to read the copy of the consistency granules; The local cache of the second PE determines that the replica of the consistency granule has a consistency state of W; as well as In response to determining that the replica of the consistent granule has a consistent state of W: The local cache of the second PE invalidates the copy of the consistency granularity; and The request to read the copy of the consistent granule is processed as a cache miss.

5. The processor-based device of claim 1, wherein the first PE is further configured to: update the consistency state of the consistency granule corresponding to the PTE in the local cache of the first PE to the modified traverser-accessible M. W The consistency state, wherein M W The consistency status indicates that the cached copy of the consistency granule, visible only to the HTW, may exist in one or more local caches of one or more other corresponding PEs among the plurality of PEs.

6. The processor-based device of claim 5, wherein the first PE is further configured to: Determine that the consistency granule corresponding to the PTE in the local cache of the first PE is shared by one or more local caches of one or more other PEs among the plurality of PEs; and In response to determining that the consistency granule corresponding to the PTE in the local cache of the first PE is shared by one or more local caches of one or more other PEs among the plurality of PEs, the consistency state of the consistency granule corresponding to the PTE in the local cache of the first PE is updated.

7. The processor-based device of claim 1, wherein the first PE is further configured to: The consistency granule corresponding to the PTE in the local cache of the first PE is determined to be in a consistency state of shared modified O, a consistency state of recently shared R, or a consistency state of shared clean S. as well as In response to determining that the consistency particle corresponding to the PTE in the local cache of the first PE is in a consistent state of O, R or S, a prex_w bus request is transmitted via the interconnect bus, the prex_w bus request indicating that the first PE has a shared copy of the consistency particle and seeks to manage the SP-PTE field of the PTE; The bus request mentioned therein includes the prex_w bus request.

8. The processor-based device of claim 1, wherein the first PE is further configured to: It is determined that the consistency granule corresponding to the PTE in the local cache of the first PE is in a consistency state that is readable by the traverser or invalid. as well as In response to determining that the consistency particle corresponding to the PTE in the local cache of the first PE is in a W or I consistency state, an rd_e_w bus request is transmitted, the rd_e_w bus request indicating that the first PE is updating the SP-PTE field of the PTE and does not hold a consistency copy of the consistency particle. The bus request mentioned therein includes the rd_e_w bus request.

9. The processor-based device of claim 5, wherein the first PE is further configured to: Install the consistency granule corresponding to the PTE into the local cache of the first PE; and Set an HTW installation indicator for the consistency particle to indicate whether the consistency particle was installed as a result of an HTW request; Specifically, the consistency status of the consistency granule corresponding to the PTE in the local cache of the first PE is updated to M. W The consistency status is determined in response to the following: the HTW installation indicator for the consistency particle is set, and the SP-PTE field storage instruction is a regular memory storage instruction that only modifies the SP-PTE field of the PTE.

10. The processor-based device of claim 1, wherein the SP-PTE field storage instruction is one of the following: a custom storage instruction, a custom compare / execute instruction, and a conventional memory storage instruction that modifies only the SP-PTE field of the PTE for an address range associated with the page table.

11. A method for facilitating the maintenance of Page Table Entries (PTEs), comprising: The decoding phase of the execution pipeline of the first PE among multiple processing elements (PEs) of a processor-based device is used to decode the special page table entry SP-PTE field storage instruction. The SP-PTE field storage instruction is executed to modify the SP-PTE field of the PTE in the page table of the system memory of the processor-based device, wherein the PTE is cached in the local cache of the first PE among the plurality of PEs in a coherence granule corresponding to the PTE. The second PE among the plurality of PEs receives a bus request for the consistency granules from the first PE via an interconnect bus; as well as The second PE updates the consistency state of the copy of the consistency granule in the local cache of the second PE to a consistency state that is readable by the traverser W, indicating that the copy of the consistency granule can only be read by the hardware table traverser HTW of the second PE.

12. The method of claim 11, further comprising transmitting a response to the bus request from the second PE to the first PE via the interconnect bus, the response indicating that the copy of the consistency granule is cached in the local cache of the second PE.

13. The method of claim 11, further comprising: The second PE's local cache determines that the second PE's HTW seeks to read the copy of the consistency granules; The local cache of the second PE determines that the replica of the consistency granule has a consistency state of W; as well as In response to determining that the replica of the consistent particle has a consistent state of W, the local cache of the second PE allows the HTW to read the replica of the consistent particle.

14. The method of claim 11, further comprising: The local cache of the second PE determines that the non-HTW agent of the second PE seeks to read the copy of the consistency granules; The local cache of the second PE determines that the replica of the consistency granule has a consistency state of W; as well as In response to determining that the replica of the consistent granule has a consistent state of W: The local cache of the second PE invalidates the copy of the consistency granularity; and The request to read the copy of the consistent granule is processed as a cache miss.

15. The method of claim 11, further comprising: The first PE among the plurality of PEs updates the consistency state of the consistency granule corresponding to the PTE in the local cache of the first PE to the modified traverser-accessible M. W The consistency status, indicating that a cached copy of the consistency granule, visible only to the hardware table traverser HTW, may exist in one or more local caches of one or more corresponding other PEs among the plurality of PEs.

16. The method of claim 15, further comprising: It is determined that the consistency granule corresponding to the PTE in the local cache of the first PE is shared by the local caches of one or more other corresponding PEs among the plurality of PEs; as well as In response to determining that the consistency granule corresponding to the PTE in the local cache of the first PE is shared by the local caches of one or more other corresponding PEs among the plurality of PEs, the consistency state of the consistency granule corresponding to the PTE in the local cache of the first PE is updated.

17. The method of claim 11, further comprising: The first PE determines that the consistency granule corresponding to the PTE in the local cache of the first PE is in a consistency state of shared modified O, a consistency state of recently shared R, or a consistency state of shared clean S. as well as In response to determining that the consistency particle corresponding to the PTE in the local cache of the first PE is in a consistent state of O, R or S, a prex_w bus request is transmitted via the interconnect bus, the prex_w bus request indicating that the first PE has a shared copy of the consistency particle and seeks to manage the SP-PTE field of the PTE; The bus request mentioned therein includes the prex_w bus request.

18. The method of claim 11, further comprising: The first PE determines that the consistency granule corresponding to the PTE in the local cache of the first PE is in a consistency state that is readable by the traverser or invalid. as well as In response to determining that the consistency particle corresponding to the PTE in the local cache of the first PE is in a W or I consistency state, an rd_e_w bus request is transmitted, the rd_e_w bus request indicating that the first PE is updating the SP-PTE field of the PTE and does not hold a consistency copy of the consistency particle. The bus request mentioned therein includes the rd_e_w bus request.

19. The method of claim 15, further comprising: The first PE among the plurality of PEs installs the consistency particle corresponding to the PTE into the local cache of the first PE; as well as Set an HTW installation indicator for the consistency particle to indicate whether the consistency particle was installed as a result of an HTW request; Specifically, the consistency status of the consistency granule corresponding to the PTE in the local cache of the first PE is updated to M. W The consistency status is determined in response to the following: the HTW installation indicator for the consistency particle is set, and the SP-PTE field storage instruction is a regular memory storage instruction that only modifies the SP-PTE field of the PTE.

20. A non-transitory computer-readable medium storing computer-executable instructions, which, when executed by a processor, cause the processor to: Decode the SP-PTE field storage instruction for special page table entries; The SP-PTE field storage instruction is executed to modify the SP-PTE field of the PTE in the page table in the system memory, wherein the PTE is cached in the local cache of the first PE among a plurality of PEs in a consistency granule corresponding to the PTE. The second PE among the plurality of PEs receives a bus request for the consistency granules from the first PE via an interconnect bus; as well as The second PE updates the consistency state of the copy of the consistency granule in the local cache of the second PE to a consistency state that is readable by the traverser W, indicating that the copy of the consistency granule can only be read by the hardware table traverser HTW of the second PE.

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