Method for manufacturing vertical device
By etching grooves on the GaN-based semiconductor substrate and forming P-type and N-type semiconductor layers, combined with planarization processing, the problem of poor controllability of the gate structure in the vertical device manufacturing process is solved, and precise performance control and current capacity are achieved.
Patent Information
- Application Number
- CN201980099912.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-09-12
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2039-09-12
AI Technical Summary
The manufacturing process of existing vertical devices leads to performance deviating from pre-design, especially the controllability of the gate structure.
The grooves are etched on the GaN-based semiconductor substrate, and the P-type and N-type semiconductor layers are formed in sequence, and these layers are retained by planarization to avoid the problem of difficult etching depth, and then the gate, source and drain structures are formed on the front and back sides of the substrate.
It realizes the precise controllability of the performance of vertical devices, improves current capacity and reduces power consumption, and enhances the reliability and performance consistency of the device.
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Figure CN114303249B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a vertical device. Background Art
[0002] Group III nitride semiconductor substrates represented by gallium nitride are receiving more and more attention because group III nitride semiconductor substrates can be widely used as light-emitting diodes (LEDs) for semiconductor lighting, high-power power electronics and radio frequency devices.
[0003] Transistors are categorized as vertical or planar based on whether their conductive channel is perpendicular or parallel to the semiconductor substrate. Because vertical devices utilize the semiconductor substrate's thickness, they can improve substrate area utilization compared to planar devices, achieving high withstand voltage, low on-resistance, and high transconductance.
[0004] However, the performance of vertical devices formed by existing manufacturing processes may deviate from the pre-designed performance. In other words, the manufacturing process causes the performance of vertical devices, especially the gate structure, to be poorly controllable.
[0005] In view of this, it is necessary to provide a new method for manufacturing a vertical device to solve the above technical problems. Summary of the Invention
[0006] The object of the present invention is to provide a method for manufacturing a vertical device to improve the performance controllability of the manufacturing process.
[0007] To achieve the above-mentioned object, the present invention provides a method for manufacturing a vertical device, comprising:
[0008] Providing a GaN-based semiconductor substrate, wherein the semiconductor substrate has a front surface and a back surface opposite to each other, and etching the semiconductor substrate from the front surface to form a groove;
[0009] forming a P-type semiconductor layer and an N-type semiconductor layer in sequence on the bottom wall, the side wall and the front surface of the semiconductor substrate of the groove, wherein the P-type semiconductor layer partially fills the groove;
[0010] planarizing the N-type semiconductor layer and the P-type semiconductor layer, and retaining the P-type semiconductor layer and the N-type semiconductor layer in the groove;
[0011] A gate structure, a source electrode and a drain electrode are formed respectively; the gate structure is located in the gate region on the front side of the semiconductor substrate, the source electrode is located on both sides of the gate structure; and the drain electrode is located on the back side of the semiconductor substrate.
[0012] It should be noted that planarization means that after the process is completed, the upper surface of the semiconductor layer inside and outside the groove is flat.
[0013] Optionally, in the step of sequentially forming a P-type semiconductor layer and an N-type semiconductor layer on the bottom wall, the side wall and the front surface of the semiconductor substrate of the groove, the N-type semiconductor layer at least fills the groove.
[0014] Optionally, in the step of sequentially forming a P-type semiconductor layer and an N-type semiconductor layer on the bottom wall, the side wall and the front surface of the semiconductor substrate of the groove, the N-type semiconductor layer partially fills the groove.
[0015] Optionally, the number of the grooves is N, where N≥2; and the number of the gate structures is N-1.
[0016] Optionally, the N-type semiconductor layer and / or the P-type semiconductor layer include GaN-based materials.
[0017] Optionally, the materials of the semiconductor substrate, and / or the N-type semiconductor layer, and / or the P-type semiconductor layer are the same or different.
[0018] Optionally, the N-type semiconductor layer and the P-type semiconductor layer are planarized by chemical mechanical polishing.
[0019] Optionally, the GaN-based semiconductor substrate is an N-type semiconductor substrate.
[0020] Optionally, the semiconductor substrate includes an N-type ion heavily doped layer and an N-type ion lightly doped layer from bottom to top, and the groove is formed in the N-type ion lightly doped layer.
[0021] Optionally, the gate structure includes a gate insulating layer and a gate disposed on the gate insulating layer.
[0022] Compared with the prior art, the present invention has the following beneficial effects:
[0023] 1) First, a GaN-based semiconductor substrate is etched from the front to form a groove. A P-type semiconductor layer and an N-type semiconductor layer are then sequentially formed on the bottom wall, sidewalls, and front of the semiconductor substrate, with the P-type semiconductor layer at least partially filling the groove. The N-type and P-type semiconductor layers are then planarized, while retaining the P-type and N-type semiconductor layers within the groove. A gate structure is then formed in the gate region on the front of the semiconductor substrate, a source electrode is formed on both sides of the gate structure, and a drain electrode is formed on the back of the semiconductor substrate. Etching the N-type and P-type semiconductor layers to form the gate structure is avoided, thereby preventing the gate structure's controllability from deviating from the pre-designed controllability due to difficulty in accurately controlling the etching depth. As a result, the performance of the vertical device can be precisely controlled through the manufacturing process.
[0024] 2) In the optional scheme, a) in the step of sequentially forming a P-type semiconductor layer and an N-type semiconductor layer on the bottom wall, sidewalls, and front surface of the recess, the N-type semiconductor layer may completely fill the recess; the N-type semiconductor layer and the P-type semiconductor layer are planarized, and the process stops when the semiconductor substrate is exposed. Or b) in the step of sequentially forming a P-type semiconductor layer and an N-type semiconductor layer on the bottom wall, sidewalls, and front surface of the recess, the N-type semiconductor layer may partially fill the recess; and during the step of planarizing the N-type semiconductor layer and the P-type semiconductor layer, a portion of the thickness of the semiconductor substrate is removed. Both schemes a) and b) can form an N-type source region and a P-type channel region. The N-type source region can be in-situ doped with N-type ions, and the P-type channel region can be in-situ doped with P-type ions. Compared to ion implantation and diffusion processes, the size and ion concentration of the N-type source region and the P-type channel region can be precisely controlled.
[0025] 3) In an alternative solution, two grooves are provided. The semiconductor substrate between the two grooves ensures that the depletion region formed by the P-type semiconductor layer and the semiconductor substrate resides primarily within the semiconductor substrate region, effectively preventing punch-through between the source and drain. Furthermore, compared to a single groove, a double groove increases the number of channels, thereby improving current capacity.
[0026] In option 4), the number of grooves is N, where N ≥ 3; the number of gate structures is N-1, and each gate structure extends from the P-type semiconductor layer in one groove to the P-type semiconductor layer in an adjacent groove. Compared to option 3), this option further increases the number of channels, thereby further improving current capacity.
[0027] 5) In an optional solution, the gate structure of the vertical device includes a gate insulating layer and a gate stacked from bottom to top; or the gate structure includes only the gate. The solution of the present invention can be used for both insulated gate field-effect transistors and Schottky gate field-effect transistors, and is highly compatible with existing processes. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a flow chart of a method for manufacturing a vertical device according to a first embodiment of the present invention;
[0029] Figures 2(a) to 6 yes Figure 1 Schematic diagram of the intermediate structure corresponding to the process in;
[0030] Figure 7 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a vertical device according to a second embodiment of the present invention;
[0031] Figure 8 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a vertical device according to a third embodiment of the present invention;
[0032] Figure 9is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a vertical device according to a fourth embodiment of the present invention;
[0033] Figure 10 is a flow chart of a method for manufacturing a vertical device according to a fifth embodiment of the present invention;
[0034] Figures 11 to 13 yes Figure 10 Schematic diagram of the intermediate structure corresponding to the process in;
[0035] Figure 14 is a schematic diagram of an intermediate structure corresponding to a method for manufacturing a vertical device according to a sixth embodiment of the present invention;
[0036] Figure 15 Schematic diagram of the intermediate structure corresponding to the method for manufacturing a vertical device according to the seventh embodiment of the present invention. To facilitate understanding of the present invention, all reference numerals appearing in the present invention are listed below:
[0037] GaN-based semiconductor substrate 10 Semiconductor substrate front surface 10a
[0038] Semiconductor substrate back side 10b grooves 101, 101'
[0039] P-type semiconductor layer 11 N-type semiconductor layer 12
[0040] Gate structure 13 Source 14
[0041] Drain 15 Gate insulating layer 131
[0042] Gate 132 DETAILED DESCRIPTION
[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0044] Figure 1 is a flow chart of a method for manufacturing a vertical device according to a first embodiment of the present invention; Figures 2(a) to 6 yes Figure 1 Schematic diagram of the intermediate structure corresponding to the process in .
[0045] First, step S1: Figures 2(a) to 3 As shown, a GaN-based semiconductor substrate 10 is provided. The semiconductor substrate 10 has a front surface 10 a and a back surface 10 b opposite to each other. A groove 101 is formed by etching the semiconductor substrate 10 from the front surface 10 a.
[0046] Figure 3 It is along Figure 2(a) to Figure 2(c) Cross-sectional view along line AA in FIG.
[0047] The GaN-based semiconductor substrate 10 may have a single-layer structure or a stacked-layer structure. The material of each layer may be GaN, AlGaN, or AlInGaN, or other semiconductor materials containing Ga atoms and N atoms, or at least two of the above materials or a mixture thereof. The GaN-based semiconductor substrate 10 may also be ion-doped to form an N-type semiconductor substrate.
[0048] The shape of the groove 101 in the plane where the GaN-based semiconductor substrate 10 is located can be rectangular, as shown in FIG2(a), or hexagonal, as shown in FIG2(b). In other optional embodiments, the shape of the groove 101 in the plane where the GaN-based semiconductor substrate 10 is located can also be circular or other shapes, which are not limited by the present invention.
[0049] In addition, the shape of the groove 101 in the plane where the GaN-based semiconductor substrate 10 is located can be a strip-shaped groove as shown in FIG. 2( c ).
[0050] Reference Figures 2(a) to 3 As shown, in this embodiment, the number of the grooves 101 is two. In other embodiments, the number of the groove 101 may also be one.
[0051] Then, step S2: Figure 4 As shown, a P-type semiconductor layer 11 and an N-type semiconductor layer 12 are sequentially formed in the groove 101 and the semiconductor substrate front surface 10 a . The P-type semiconductor layer 11 partially fills the groove 101 , and the N-type semiconductor layer 12 at least fills the groove 101 .
[0052] The P-type semiconductor layer 11 partially fills the groove 101 , and the N-type semiconductor layer 12 at least fills the groove 101 . This can be achieved by forming a thinner P-type semiconductor layer 11 and a thicker N-type semiconductor layer 12 .
[0053] The N-type semiconductor layer 12 may be Figure 4 As shown, the groove 101 is overfilled, that is, the sum of the thicknesses of the N-type semiconductor layer 12 and the P-type semiconductor layer 11 at the groove 101 is greater than the depth of the groove 101. In other optional solutions, the N-type semiconductor layer 12 can also just fill the groove 101, that is, the sum of the thicknesses of the N-type semiconductor layer 12 and the P-type semiconductor layer 11 at the groove 101 is equal to the depth of the groove 101.
[0054] The materials of the P-type semiconductor layer 11 and the N-type semiconductor layer 12 can be the same or different, and both can include GaN-based materials. GaN-based materials are semiconductor materials containing at least Ga atoms and N atoms, such as GaN, AlGaN, AlInGaN, etc. The materials of the P-type semiconductor layer 11 and the N-type semiconductor layer 12 can also be the same as or different from the material of the semiconductor substrate 10.
[0055] The P-type semiconductor layer 11 and the N-type semiconductor layer 12 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or plasma enhanced chemical vapor deposition (PECVD). o Plasma Enhanced Chemical Vapor Deposition), or low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or metal organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof.
[0056] The doping ions in the P-type semiconductor layer 11 and the N-type semiconductor layer 12 may be achieved by in-situ doping.
[0057] Then, step S3: Figure 5 As shown, the N-type semiconductor layer 12 and the P-type semiconductor layer 11 are planarized, and the P-type semiconductor layer 11 and the N-type semiconductor layer 12 in the groove 101 are retained.
[0058] Specifically, chemical mechanical polishing (CMP) can be used to planarize the N-type semiconductor layer 12 and the P-type semiconductor layer 11. After the planarization process is completed, the N-type semiconductor layer 12 in the groove 101 is flush with the upper surface of the semiconductor substrate 10 outside the groove 101.
[0059] Then, step S4: Figure 6 As shown, a gate structure 13, a source 14 and a drain 15 are formed respectively; the gate structure 13 is located in the gate region of the front side 10a of the semiconductor substrate, the source 14 is located on both sides of the gate structure 13; the drain 15 is located on the back side 10b of the semiconductor substrate.
[0060] In step S4 , if the groove 101 is a strip-shaped groove in the plane where the GaN-based semiconductor substrate 10 is located, the gate structure 13 , source 14 and drain 15 are correspondingly: a strip-shaped gate structure 13 , a strip-shaped source 14 and a strip-shaped drain 15 parallel to the extending direction of the groove 101 .
[0061] Reference Figure 6 As shown, to simplify the process, the gate structure 13 may extend from the P-type semiconductor layer 11 in one groove 101 to the P-type semiconductor layer 11 in another groove 101 .
[0062] also, Figure 6 In the embodiment, the gate structure 13 includes a gate insulating layer 131 and a gate 132 stacked from bottom to top, for example, the vertical device is an insulated gate field effect transistor. In other optional solutions, the gate structure 13 may also include only the gate 132, for example, the vertical device is a Schottky gate field effect transistor.
[0063] Compared with the vertical device with a trench-type gate structure 13, the above-mentioned manufacturing method avoids etching the N-type semiconductor layer 12 and the P-type semiconductor layer 11 to form the gate structure 13, thereby avoiding the control capability of the gate structure 13 deviating from the pre-designed control capability due to the difficulty in accurately controlling the etching depth, so that the performance of the vertical device can be precisely controlled through the manufacturing process.
[0064] Reference Figure 6 As shown, when the vertical device is an enhancement type, a positive conduction voltage is applied to the gate 132, and the P-type semiconductor layer 11 below the gate structure 13 is inverted to N-type, thereby forming a channel. At this time, if there is a voltage difference between the source 14 and the drain 15, then as shown by the dotted line, a conduction current flows between the source 14 and the drain 15. When the vertical device is a depletion type, no voltage is applied to the gate 132, and the P-type semiconductor layer 11 below the gate structure 13 is inverted to N-type, thereby forming a channel. At this time, if there is a voltage difference between the source 14 and the drain 15, then as shown by the dotted line, a conduction current flows between the source 14 and the drain 15.
[0065] In addition, the semiconductor substrate 10 between the two grooves 101 realizes a shorter channel, effectively avoiding the occurrence of a punch-through effect between the source 14 and the drain 15 .
[0066] It can be understood that, compared with the single groove 101 , the double groove 101 increases the number of channels, thereby increasing current capacity, reducing power consumption, and improving gain.
[0067] Figure 7 It is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a vertical device according to the second embodiment of the present invention.
[0068] Reference Figure 7 and Figure 6 As shown, the manufacturing method of the vertical device of the second embodiment is substantially the same as that of the first embodiment, with the only difference being that in step S1 of the first embodiment, the vertical cross-section of the groove 101 formed is rectangular, while in step S1 of the second embodiment, the vertical cross-section of the groove 101' formed is U-shaped. The vertical cross-section is perpendicular to the plane of the GaN-based semiconductor substrate 10.
[0069] In other optional solutions, the vertical cross-section of the groove 101 ′ may also be in other shapes such as a V-shape, and the present invention is not limited thereto.
[0070] Figure 8 It is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a vertical device according to the third embodiment of the present invention.
[0071] Reference Figure 8 and Figure 6 As shown, the manufacturing method of the vertical device of the third embodiment is roughly the same as the manufacturing method of the vertical device of the first and second embodiments, with the only difference being that: in step S1, the provided GaN-based semiconductor substrate 10 includes an N-type ion heavily doped layer 103 and an N-type ion lightly doped layer 104 from bottom to top; and the groove 101 is formed in the N-type ion lightly doped layer 104.
[0072] Figure 9 It is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a vertical device according to the fourth embodiment of the present invention.
[0073] Reference Figure 9 、 Figures 6 to 8 As shown, the manufacturing method of the vertical device of the fourth embodiment is substantially the same as the manufacturing method of the vertical device of the first to third embodiments, with the only difference being that in step S1 , the number of grooves 101 formed is three.
[0074] There are two gate structures 13, each extending from the P-type semiconductor layer 11 in one groove 101 to the P-type semiconductor layer 11 in an adjacent groove 101. Increasing the number of grooves 101 further increases the number of channels, connecting multiple vertical conductive structures in parallel, thereby increasing current capacity, reducing power consumption, and improving gain.
[0075] In other optional solutions, the number of grooves 101 can be N, where N>3. The number of gate structures 13 is N-1, and each gate structure 13 extends from the P-type semiconductor layer 11 in one groove 101 to the P-type semiconductor layer 11 in an adjacent groove 101. The advantages are: further increasing current capacity, reducing power consumption, and improving gain.
[0076] When the solution of the fourth embodiment of the present invention is combined with the solution of the third embodiment, a plurality of grooves 101 are formed in the N-type ion lightly doped layer 104 .
[0077] Figure 10 is a flow chart of a method for manufacturing a vertical device according to a fifth embodiment of the present invention; Figures 11 to 13 yes Figure 10 Schematic diagram of the intermediate structure corresponding to the process in .
[0078] Reference Figures 10 to 13 ,and Figures 1 to 7As shown, the manufacturing method of the vertical device of the fifth embodiment is substantially the same as the manufacturing method of the vertical device of the first and second embodiments, with the only difference being that in step S2 ′, the N-type semiconductor layer 12 partially fills the groove 101 .
[0079] Reference Figure 11 As shown, the P-type semiconductor layer 11 and the N-type semiconductor layer 12 partially fill the groove 101 by forming a thinner P-type semiconductor layer 11 and a thinner N-type semiconductor layer 12 .
[0080] So, refer to Figure 12 As shown, in step S3 , in the step of planarizing the N-type semiconductor layer 12 and the P-type semiconductor layer 11 , a portion of the thickness of the semiconductor substrate 10 is removed.
[0081] Reference Figure 13 As shown, when the vertical device is an enhancement type, a positive conduction voltage is applied to the gate 132, and the P-type semiconductor layer 11 below the gate structure 13 is inverted to N-type, thereby forming a channel. At this time, if there is a voltage difference between the source 14 and the drain 15, then as shown by the dotted line, a conduction current flows between the source 14 and the drain 15. When the vertical device is a depletion type, no voltage is applied to the gate 132, and the P-type semiconductor layer 11 below the gate structure 13 is inverted to N-type, thereby forming a channel. At this time, if there is a voltage difference between the source 14 and the drain 15, then as shown by the dotted line, a conduction current flows between the source 14 and the drain 15.
[0082] Figure 14 It is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a vertical device according to the sixth embodiment of the present invention.
[0083] Reference Figure 14 and Figure 13 As shown, the manufacturing method of the vertical device of the sixth embodiment is substantially the same as the manufacturing method of the vertical device of the fifth embodiment, with the only difference being that: in step S1, the provided GaN-based semiconductor substrate 10 includes an N-type ion heavily doped layer 103 and an N-type ion lightly doped layer 104 from bottom to top; and the groove 101 is formed in the N-type ion lightly doped layer 104.
[0084] Figure 15 It is a schematic diagram of an intermediate structure corresponding to the method for manufacturing a vertical device according to the seventh embodiment of the present invention.
[0085] Reference Figure 15 、 Figure 13 and Figure 14 As shown, the manufacturing method of the vertical device of the seventh embodiment is substantially the same as the manufacturing method of the vertical device of the fifth and sixth embodiments, with the only difference being that in step S1 , the number of grooves 101 formed is three.
[0086] There are two gate structures 13, each extending from the P-type semiconductor layer 11 in one groove 101 to the P-type semiconductor layer 11 in an adjacent groove 101. Increasing the number of grooves 101 further increases the number of channels, connecting multiple vertical conductive structures in parallel, thereby increasing current capacity, reducing power consumption, and improving gain.
[0087] In other optional solutions, the number of grooves 101 can be N, where N>3. The number of gate structures 13 is N-1, and each gate structure 13 extends from the P-type semiconductor layer 11 in one groove 101 to the P-type semiconductor layer 11 in an adjacent groove 101. The advantages are: further increasing current capacity, reducing power consumption, and improving gain.
[0088] When the solution of the seventh embodiment of the present invention is combined with the solution of the sixth embodiment, a plurality of grooves 101 are formed in the N-type ion lightly doped layer 104 .
[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for manufacturing a vertical device, characterized in that: include: Providing a GaN-based semiconductor substrate (10), wherein the semiconductor substrate (10) has a front surface (10a) and a back surface (10b) opposite to each other, and etching the semiconductor substrate (10) from the front surface (10a) to form a groove (101); A P-type semiconductor layer (11) and an N-type semiconductor layer (12) are sequentially formed on the bottom wall, side walls and the front surface (10a) of the groove (101), wherein the P-type semiconductor layer (11) partially fills the groove (101); planarizing the N-type semiconductor layer (12) and the P-type semiconductor layer (11), and retaining the P-type semiconductor layer (11) and the N-type semiconductor layer (12) in the groove (101); A gate structure (13), a source electrode (14), and a drain electrode (15) are formed respectively; the gate structure (13) is located in the gate region of the front side (10a) of the semiconductor substrate, the source electrode (14) is located on both sides of the gate structure (13); and the drain electrode (15) is located on the back side (10b) of the semiconductor substrate; The step of sequentially forming a P-type semiconductor layer (11) and an N-type semiconductor layer (12) on the bottom wall, the side wall and the front surface (10a) of the groove (101) includes: The P-type semiconductor layer (11) is deposited on the bottom wall, the side wall and the front surface (10a) of the groove (101), and the N-type semiconductor layer (12) is formed on the deposited P-type semiconductor layer (11) to avoid etching the N-type semiconductor layer (12) and the P-type semiconductor layer (11).
2. The method for manufacturing a vertical device according to claim 1, wherein: In the step of sequentially forming a P-type semiconductor layer (11) and an N-type semiconductor layer (12) on the bottom wall, side walls and the front surface (10a) of the groove (101), the N-type semiconductor layer (12) at least fills the groove (101).
3. The method for manufacturing a vertical device according to claim 1, wherein: In the step of sequentially forming a P-type semiconductor layer (11) and an N-type semiconductor layer (12) on the bottom wall, side walls and the front surface (10a) of the groove (101), the N-type semiconductor layer (12) partially fills the groove (101).
4. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The number of the grooves (101) is N, where N≥2; and the number of the gate structures (13) is N-1.
5. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The N-type semiconductor layer (12) and / or the P-type semiconductor layer (11) include GaN-based materials.
6. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The materials of the semiconductor substrate (10), and / or the N-type semiconductor layer (12), and / or the P-type semiconductor layer (11) are the same or different.
7. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The N-type semiconductor layer (12) and the P-type semiconductor layer (11) are planarized using a chemical mechanical polishing method.
8. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The GaN-based semiconductor substrate (10) is an N-type semiconductor substrate (10).
9. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The semiconductor substrate (10) comprises, from bottom to top, an N-type ion heavily doped layer (103) and an N-type ion lightly doped layer (104), and the groove (101) is formed in the N-type ion lightly doped layer (104).
10. The method for manufacturing a vertical device according to any one of claims 1 to 3, characterized in that: The gate structure (13) comprises a gate insulating layer (131) and a gate (132) arranged on the gate insulating layer (131).
Citation Information
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