Testing equipment and method for ADC chip

Abstract

The embodiment of the present invention provides a test device and method for an ADC chip, which belongs to the field of chip testing technology. The device includes: a power conversion module, an operational amplifier, and ATE, wherein the power conversion module is used to convert the single power supply voltage output by the DPS module of the ATE into a dual power supply voltage that meets the driving power supply requirements of the operational amplifier; the operational amplifier is used to amplify the first test signal output by the ATE to generate a second test signal, and the second test signal meets the input amplitude requirements of the ADC chip under test; the ADC chip under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE; and the ATE is used to obtain and output the test parameters of the ADC chip under test based on the analog-to-digital converted signal. The technical solution can realize the test of ADC chips that require high swing input. In addition, it has the advantages of low cost, small size, and easy programming control.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a testing device and method for an ADC chip. Background Art

[0002] With the rapid development of electronic communication technology and the continuous improvement of integrated circuit manufacturing technology, new materials and digital signal processing technology have been continuously improved. High-swing and high-resolution analog-to-digital converter (ADC) chips are widely used in signal acquisition and processing systems such as smart grids to achieve real-time acquisition and monitoring of grid status and information. In many scenarios, the ADC chip collects input signals as high as ±10V. In order to meet the needs of the acquisition scenario, the input of the ADC chip must also meet these requirements when it is tested.

[0003] However, the current automatic test equipment (ATE) used for batch test production generally cannot achieve a high swing and high precision test signal output of ±10V. The test signal output amplitude of the most advanced ATE test equipment in the industry is generally lower than ±5V, and its power supply voltage output is generally 6-8V, generally lower than 10V. If chip design manufacturers need to produce high swing and high resolution ADC chip products with a maximum input signal swing of up to ±10V and a resolution higher than 16bit, they will face the dilemma that the available ATE cannot meet their requirements. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a testing device and method for an ADC chip, so as to at least solve the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a test device for an analog-to-digital converter ADC chip, the device comprising: a power conversion module, an operational amplifier, and automatic test equipment ATE, the power conversion module is used to convert the single power supply voltage output by the digital power supply DPS module of the ATE into a dual power supply voltage that meets the driving power supply requirement of the operational amplifier; the operational amplifier is used to amplify the first test signal output by the ATE to generate a second test signal, and the second test signal meets the input amplitude requirement of the ADC chip under test; the ADC chip under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE; and the ATE is used to obtain and output the test parameters of the ADC chip under test based on the analog-to-digital converted signal.

[0006] Optionally, the device also includes: a calibration acquisition module and a processor; the device is also used to perform the following calibration process: the ATE generates a first calibration test signal based on the test signal required by the ADC chip under test; the operational amplifier amplifies the first calibration test signal to generate a second calibration test signal, and the second calibration test signal meets the input amplitude requirement of the ADC chip under test; the calibration acquisition module acquires the second calibration test signal; the processor fits the second calibration test signal to generate an ideal test signal, and when a first error between the second calibration test signal and the ideal test signal is greater than a preset error, the second calibration test signal is calibrated based on the first error to generate a third calibration test signal, and the third calibration test signal is transmitted to the ATE; and the ATE generates a new first calibration test signal based on the third calibration test signal to repeat the calibration process until the error between the generated second calibration test signal and the ideal test signal is not greater than the preset error, wherein the ATE uses the final calibration test signal as the first test signal.

[0007] Optionally, the processor uses a calibration fitting compensation algorithm to fit the second calibration test signal to generate the ideal test signal.

[0008] Optionally, the acquisition module is further used to acquire the second calibration test signal multiple times, and the processor is further used to average the multiple acquired second calibration test signals, and fit the averaged second calibration test signal to generate an ideal test signal.

[0009] Optionally, the processor is further configured to issue an alarm message when the number of cycles of the calibration process exceeds a preset number and a first error between the second calibration test signal and the ideal test signal is greater than the preset error.

[0010] Optionally, the resolution of the calibration acquisition module is higher than the resolution of the ADC chip under test.

[0011] Optionally, the calibration acquisition module is a digitizer module in the ATE, or the calibration acquisition module is an independent digitizer module.

[0012] Optionally, the device also includes: a signal path switching module, used to: switch the signal output by the operational amplifier to the calibration acquisition module when executing the calibration process, and switch the signal output by the operational amplifier to the ADC chip under test when testing the ADC chip under test.

[0013] Optionally, the device further includes: a noise suppression module, used to suppress power switch noise of the power conversion module.

[0014] Optionally, the power conversion module is implemented based on a direct current (DC-DC) switching power supply, and the noise suppression module is a linear power supply regulator.

[0015] Correspondingly, an embodiment of the present invention also provides a testing method for an ADC chip, the method comprising: a power conversion module amplifies the power supply voltage output by the DPS module of the ATE to meet the driving power demand of the operational amplifier; the operational amplifier amplifies the first test signal output by the ATE to generate a second test signal, and the second test signal meets the input amplitude demand of the ADC chip under test; the ADC chip under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE; and the ATE obtains and outputs the test parameters of the ADC chip under test based on the analog-to-digital converted signal.

[0016] Optionally, the method also includes performing the following calibration process: the ATE generates a first calibration test signal based on the test signal required by the ADC chip under test; the operational amplifier amplifies the first calibration test signal to generate a second calibration test signal, and the second calibration test signal meets the input amplitude requirement of the ADC chip under test; the calibration acquisition module acquires the second calibration test signal; the processor fits the second calibration test signal to generate an ideal test signal, and when a first error between the second calibration test signal and the ideal test signal is greater than a preset error, calibrates the second calibration test signal based on the first error to generate a third calibration test signal, and transmits the third calibration test signal to the ATE; and the ATE generates a new first calibration test signal based on the third calibration test signal to repeat the calibration process until the error between the generated second calibration test signal and the ideal test signal is no greater than the preset error, wherein the ATE uses the final calibration test signal as the first test signal.

[0017] Optionally, the processor uses a calibration fitting compensation algorithm to fit the second calibration test signal to generate the ideal test signal.

[0018] Optionally, during the calibration process, the acquisition module is also used to acquire the second calibration test signal multiple times, and the processor is also used to average the multiple acquired second calibration test signals, and fit the averaged second calibration test signal to generate an ideal test signal.

[0019] Optionally, the method further includes: when the number of cycles of the calibration process exceeds a preset number and a first error between the second calibration test signal and the ideal test signal is greater than the preset error, the processor issues an alarm message.

[0020] Through the above technical solution, an external power conversion module is added to the ATE, and the single power supply voltage provided by the ATE is replaced with a dual power supply voltage to power the operational amplifier. The operational amplifier amplifies the first test signal output by the ATE to generate a second test signal that meets the input amplitude requirement of the ADC chip under test. The ADC chip performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE. The ATE can obtain and output the test parameters of the ADC chip under test based on the analog-to-digital converted signal. The technical solution can realize the test of ADC chips that require high swing input. In addition, the technical solution has the advantages of low cost, small size, and easy programming control.

[0021] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0023] Figure 1 A structural block diagram of a testing device for an ADC chip according to an embodiment of the present invention is shown;

[0024] Figure 2 A structural block diagram of a testing device for an ADC chip according to another embodiment of the present invention is shown;

[0025] Figure 3 A schematic diagram showing a flow chart of a testing method for an ADC chip according to an embodiment of the present invention; and

[0026] Figure 4 A schematic diagram of a calibration process in a testing method for an ADC chip according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0027] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0028] Figure 1 FIG. 4 is a block diagram showing a structure of a test device for an ADC chip according to an embodiment of the present invention. Figure 1As shown, an embodiment of the present invention provides a test device for an ADC chip, and the device may include: a power conversion module 120 , an operational amplifier 130 , and an ATE 110 .

[0029] The power conversion module 120 is used to convert the single power supply voltage output by the digital power supply (DPS) module of the ATE into a dual power supply voltage that meets the driving power supply requirements of the operational amplifier 130. The operational amplifier 130 is used to amplify the first test signal output by the ATE 110 to generate a second test signal, and the second test signal meets the input amplitude requirement of the ADC chip 140 under test. The ADC chip 140 under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE 110. The ATE 110 is used to obtain and output the test parameters of the ADC chip 140 under test based on the analog-to-digital converted signal.

[0030] The signal output by the ADC chip under test after analog-to-digital conversion is judged and collected through the digital channel of ATE and stored in the ATE machine, and then the software algorithm set in ATE is used to reconstruct the signal under test and process the digital signal, and the static and dynamic parameters of the ADC chip under test are calculated, so as to obtain the test parameters of the ADC chip under test. The software algorithm can be mainly carried out by Fourier transform (FFT). The collected time domain waveform is transformed to the frequency domain through FFT, and normalized to obtain noise, fundamental wave and harmonic energy, and then the required test parameter results are calculated. The test parameters can mainly include signal-to-noise ratio (SNR), total harmonic distortion (THD), signal-to-noise ratio (SINAD), etc.

[0031] The signal swing of the ADC chip under test is greater than the output amplitude of the test signal that the ATE can provide. The operational amplifier is a wide-amplitude power operational amplifier to meet the signal swing of the ADC chip under test.

[0032] According to the static and dynamic test signals required by the ADC chip under test, the corresponding signal amplitude, frequency, phase and other parameters are first set by ATE to generate a first test signal. The static and dynamic test signals can be obtained according to some main parameters of the ADC chip, wherein the main parameters may include, for example, resolution, sampling frequency, signal amplitude, phase, whether high swing or low swing is required, and the main parameters may be determined according to specific application scenarios. If the signal swing of the ADC chip under test is not greater than the output amplitude of the test signal that the ATE can provide, it is a low swing. If the signal swing of the ADC chip under test is greater than the output amplitude of the test signal that the ATE can provide, it is a high swing.

[0033] The first test signal output by the ATE may be set and generated by an arbitrary waveform generator module of the ATE. According to the performance parameters of the ADC chip under test, the output of the first test signal may be realized by programming the ATE.

[0034] The first test signal is input to the operational amplifier to be amplified to the required amplitude output, wherein the operational amplifier is a wide-amplitude power operational amplifier. The wide-amplitude power operational amplifier is powered by a power conversion module. The power input of the power conversion module can be provided by a programmable power module of ATE, and the output of the power conversion module is controlled by ATE programming. The output of the wide-amplitude power operational amplifier is set by ATE according to the test requirements of the ADC chip under test.

[0035] In order for the wide-range power operational amplifier to amplify the test signal normally, the power supply of the wide-range power operational amplifier needs to be greater than the signal swing. It is difficult for general ATE equipment to directly provide a sufficiently high power supply voltage through its programmable power module, so it needs to be realized through a power conversion module. The single power supply output by the programmable power module is used to achieve high-amplitude positive and negative power output through the power conversion module to provide the required driving power to the wide-range power operational amplifier, so as to amplify the small-amplitude test signal output by the ATE into a large-amplitude test signal, thereby meeting the input amplitude requirements of the ADC chip under test.

[0036] After the ADC integrated chip under test performs analog-to-digital conversion on the input analog wave signal, the converted digital signal is connected to the digital channel of ATE through the output pin. After the digital channel of ATE collects and judges it, the data is stored in ATE, and ATE completes the operation of the test algorithm to obtain the corresponding test parameters of the ADC chip under test, thereby completing the test of the ADC chip under test.

[0037] During the test, the power input of the power conversion module, the first test signal input to the operational amplifier, and the power and control signals of the ADC chip under test are all generated by ATE, and the setting and control of the entire calibration process are achieved through software programming.

[0038] In an optional embodiment, the device provided by the embodiment of the present invention may further include a noise suppression module for suppressing the power switch noise of the power conversion module. The noise suppression module may be any noise suppression module in the art.

[0039] In an optional case, the power conversion module can be implemented based on a direct current-direct current (DC-DC) switching power supply. The noise suppression module can be a linear power regulator, which is used to suppress the ripple and noise of the DC-DC switching power supply, so that the power conversion module outputs a high-quality bipolar DC regulated power supply, thereby providing a high-quality power supply to the operational amplifier circuit.

[0040] The technical solution provided by the embodiment of the present invention is particularly suitable for testing ADC chips that require high swing input. The ATE 110 can be any ATE known in the art. Usually, the amplitude of the test signal output by the ATE is lower than ±5V, and the output power supply voltage is generally between 6V and 8V. According to the performance parameters of the ADC chip under test, an operational amplifier that can meet the test signal swing, bandwidth and accuracy requirements of the ADC chip under test can be selected. Then, according to the driving power supply requirements of the operational amplifier and its output signal swing, a suitable power conversion module is selected. The power conversion module can be, for example, a programmable power conversion module. The operational amplifier can be an ultra-low noise differential programmable gain instrument operational amplifier. The power conversion module, the linear power supply regulator, the operational amplifier and related circuits can be arranged on the ATE carrier board. During design, when selecting devices, try to select ultra-low noise differential programmable gain instrument operational amplifiers and linear power supply regulators with high power supply noise suppression ratios; when designing the carrier board, the circuit of the operational amplifier output to the ADC chip under test should be placed as close as possible to the signal input pins of the ADC chip under test to reduce the noise, signal distortion and other factors introduced during the wiring process, which may lead to signal performance deterioration. If relays are required to select and switch multiple signals in the carrier board design, RF surface mount packaged relays should be used as much as possible to reduce signal degradation caused by the relays.

[0041] The test equipment for ADC chip provided by the embodiment of the present invention adds a power conversion module to ATE, replaces the single power supply voltage provided by ATE with a dual power supply voltage to power the operational amplifier, the operational amplifier amplifies the first test signal output by ATE to generate a second test signal that meets the input amplitude requirement of the ADC chip under test, the ADC chip performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to ATE, and ATE can obtain and output the test parameters of the ADC chip under test based on the analog-to-digital converted signal. The technical solution can realize the test of ADC chips that require high swing input. The technical solution has the advantages of low cost, small size, and easy programming control. In addition, since the generation of the test signal of the ADC chip can be based on the ATE in the prior art, the programming flexibility required for mass production testing of ADC chips and the stability required for large-scale mass production testing can be met.

[0042] Figure 2 FIG. 4 is a block diagram showing a test device for an ADC chip according to another embodiment of the present invention. Figure 2 As shown, Figure 1 The difference between the illustrated embodiment is that the test device for ADC chip provided by the embodiment of the present invention may further include a calibration acquisition module 150 and a processor 160 for implementing a calibration process. The calibration process is used to calibrate the test signal output by the ATE so that the test signal is closer to the ideal analog signal.

[0043] The calibration process is described in detail below.

[0044] The ATE generates a first calibration test signal based on the test signal required by the ADC chip under test. Specifically, according to the static and dynamic test signals required by the ADC chip under test, the corresponding signal amplitude, frequency, phase and other parameters are first set by the ATE to generate the first calibration test signal. The first calibration test signal is set and generated by the arbitrary waveform generator module of the ATE, and then output to the operational amplifier. The operational amplifier amplifies the first calibration test signal to generate a second calibration test signal, and the second calibration test signal meets the input amplitude requirement of the ADC chip under test. The calibration acquisition module acquires the second calibration test signal. After being acquired by the calibration acquisition module, the second calibration test signal is converted into a digital signal.

[0045] The processor fits the second calibration test signal collected by the calibration acquisition module to generate an ideal test signal. The processor can use a calibration fitting compensation algorithm to fit the second calibration test signal to generate the ideal test signal. The calibration fitting compensation algorithm can be, for example, a least squares method or other suitable fitting algorithms. The fitting algorithm module of ATE is expensive and has high testing costs. In the embodiment of the present invention, the processor uses a calibration fitting compensation algorithm for fitting, which can effectively save testing costs.

[0046] In the case where the first error between the second calibration test signal and the ideal test signal is greater than the preset error, the second calibration test signal is calibrated based on the first error to generate a third calibration test signal, and the third calibration test signal is transmitted to the ATE. The calibration of the second calibration test signal aims to ensure that the first error between the generated third calibration test signal and the ideal test signal is less than the preset error, and the specific calibration amplitude can be reasonably set according to actual needs. A storage module can be provided in the processor for storing the third calibration test signal. The preset error can be set to any appropriate value as needed.

[0047] It can be understood that in actual operation, the first error between the second calibration test signal and the ideal analog signal can be quantified in real time. Specifically, the difference between the value of each time domain point of the ideal test signal and the second calibration test signal is calculated, and the calculated difference is represented and stored in digital form, thereby realizing the quantification of the first error. If the first error between the second calibration test signal and the ideal test signal at a certain time domain point is greater than the preset error, the value of the time domain point on the second calibration test signal is calibrated.

[0048] The ATE generates a new first calibration test signal based on the third calibration test signal to repeat the calibration process until the error between the generated second calibration test signal and the ideal test signal is no greater than the preset error, wherein the ATE uses the final calibration test signal as the first test signal. The final calibration test signal may also be referred to as a pre-distortion test waveform. The waveform is downloaded to the arbitrary waveform generator of the ATE. The arbitrary waveform generator generates a pre-distortion test waveform, and after being amplified by the operational amplifier, the pre-distortion test waveform generated by the calibration offsets the test signal distortion caused by the arbitrary waveform generator and the operational amplifier, thereby improving the test output signal quality through the calibration process.

[0049] The number of cycles of the calibration process can also be limited. Specifically, the processing can also be used to issue an alarm message when the number of cycles of the calibration process exceeds a preset number and the first error between the second calibration test signal and the ideal test signal is greater than the preset error. The alarm signal can be issued, for example, by flashing an indicator light, a voice message, etc. The staff can modify the test index (for example, adjust the size of the preset error, etc.) or change the circuit design, etc. according to the alarm message. The preset number of times can be set to any appropriate number as needed.

[0050] In order to avoid the influence of random noise on the calibration data, the acquisition module can collect the second calibration test signal multiple times. The processor can also average the collected multiple second calibration test signals to suppress the influence of random noise as much as possible. Accordingly, the processor uses the averaged second calibration test signal to fit to generate an ideal test signal. The number of times the acquisition module collects the second calibration test signal can be set to any appropriate number as needed.

[0051] The resolution of the calibration acquisition module is preferably higher than the resolution of the ADC chip under test. The calibration acquisition module can be implemented by using a digitizer in the ATE with a higher resolution than the ADC chip under test. If there is no digitizer module in the ATE with a higher resolution than the ADC chip under test, a digitizer module with a higher resolution than the ADC chip under test can be externally connected to implement the calibration acquisition module, that is, an independent digitizer module is selected as the calibration acquisition module.

[0052] The static and dynamic test signals required by the ADC chip under test can be calibrated one by one to eliminate the system errors that may be introduced by the power conversion module, operational amplifier and arbitrary waveform generator module of ATE under the corresponding test signal conditions.

[0053] refer to Figure 2 The test device for ADC chip provided by the embodiment of the present invention may further include a signal path switching module 130, whose input is connected to the operational amplifier and whose output is connected to the calibration acquisition module and the ADC chip under test, and is used to: when executing the calibration process, switch the signal output by the operational amplifier to the calibration acquisition module, and when performing a test on the ADC chip under test, switch the signal output by the operational amplifier to the ADC chip under test.

[0054] After the calibration process is completed, the final calibration test signal is downloaded to the arbitrary waveform generator of the ATE to generate the test signal required by the ADC chip under test. The test signal may include static and dynamic test signals. The test signal is amplified by the operational amplifier and transmitted to the input end of the ADC chip under test by the signal path switching module. The ADC chip under test performs analog-to-digital conversion on the test signal and inputs the analog-to-digital converted signal to the ATE. The ATE obtains and outputs the test parameters of the ADC chip under test based on the analog-to-digital converted signal.

[0055] By executing the calibration process, the system errors that may be introduced by the power conversion module, the operational amplifier and the arbitrary waveform generator module of the ATE can be eliminated. The test process performed after the calibration process is completed has the same principles and benefits as the test process provided in the above embodiments, which will not be repeated here.

[0056] Figure 3 FIG. 1 is a flow chart of a method for testing an ADC chip according to an embodiment of the present invention. Figure 3As shown, an embodiment of the present invention further provides a test method for an ADC chip, the method comprising: S310, the power conversion module amplifies the power supply voltage output by the DPS module of the ATE to meet the driving power demand of the operational amplifier; S320, the operational amplifier amplifies the first test signal output by the ATE to generate a second test signal, and the second test signal meets the input amplitude requirement of the ADC chip under test; S330, the ADC chip under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE; and S340, the ATE obtains and outputs the test parameters of the ADC chip under test based on the analog-to-digital converted signal.

[0057] The test method for ADC chip provided by the embodiment of the present invention adds a power conversion module to ATE, replaces the single power supply voltage provided by ATE with a dual power supply voltage to power the operational amplifier, and the operational amplifier amplifies the first test signal output by ATE to generate a second test signal that meets the input amplitude requirement of the ADC chip under test, and the ADC chip performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to ATE, and ATE can obtain and output the test parameters of the ADC chip under test based on the analog-to-digital converted signal. The technical solution can realize the test of ADC chips that require high swing input. The technical solution has the advantages of low cost, small size, and easy programming control. In addition, since the generation of the test signal of the ADC chip can be based on ATE in the prior art, the programming flexibility required for mass production testing of ADC chips and the stability required for large-scale mass production testing can be met.

[0058] Figure 4 FIG. 2 is a schematic diagram showing a calibration process in a test method for an ADC chip according to an embodiment of the present invention. Figure 4As shown, the test method for an ADC chip provided by an embodiment of the present invention may further include the following calibration process: S410, the ATE generates a first calibration test signal based on the test signal required by the ADC chip under test; S420, the operational amplifier amplifies the first calibration test signal to generate a second calibration test signal, and the second calibration test signal meets the input amplitude requirement of the ADC chip under test; S430, the calibration acquisition module acquires the second calibration test signal; S440, the processor fits the second calibration test signal to generate an ideal test signal, and in the case where the first error between the second calibration test signal and the ideal test signal is greater than a preset error, calibrates the second calibration test signal based on the first error to generate a third calibration test signal, and transmits the third calibration test signal to the ATE; S450, the ATE generates a new first calibration test signal based on the third calibration test signal to repeat the calibration process until the error between the generated second calibration test signal and the ideal test signal is not greater than the preset error, wherein the ATE uses the final calibration test signal as the first test signal.

[0059] In some optional embodiments, the processor fits the second calibration test signal using a calibration fitting compensation algorithm to generate the ideal test signal.

[0060] In some optional embodiments, during the calibration process, the acquisition module is further used to acquire the second calibration test signal multiple times, and the processor is further used to average the multiple acquired second calibration test signals, and fit the averaged second calibration test signal to generate an ideal test signal.

[0061] In some optional embodiments, the testing method for an ADC chip provided by an embodiment of the present invention may further include: when the number of cycles of the calibration process exceeds a preset number and the first error between the second calibration test signal and the ideal test signal is greater than the preset error, the processor issues an alarm message.

[0062] The calibration process can eliminate system errors that may be introduced by the power conversion module, operational amplifier, and arbitrary waveform generator module of the ATE.

[0063] The specific working principle and benefits of the test method for ADC chip provided by the embodiment of the present invention can be found in the specific working principle and benefits of the test device for ADC chip provided by the embodiment of the present invention, which will not be repeated here.

[0064] The following describes the testing device and method for ADC chips provided by the embodiment of the present invention by taking the ATE as V93000 type, and implementing the test of high swing ADC chips with an external power conversion module and an operational amplifier as an example. The operational amplifier is a programmable wide power low noise operational amplifier.

[0065] The V93000 ATE sets a single voltage output 5V power supply through the board programming of the DPS module. The 5V single power supply is converted into a ±18V bipolar wide-band power supply output through the power conversion module. The power conversion module can be implemented based on a DC-DC switching power supply and needs to work at a certain switching frequency. If it is directly used as the working power supply of the operational amplifier, its ripple and noise performance is poor. In order to suppress the ripple and noise of the power conversion module, a linear power supply regulator circuit is added to the output end of the power conversion module to achieve high power supply ripple and noise suppression. There will be a certain voltage difference between the input and output of the linear power supply regulator circuit. Therefore, the output of the power conversion module needs to consider the input and output voltage difference of the linear power supply regulator circuit and the target power supply voltage of the operational amplifier. For example, if the target power supply voltage of the operational amplifier is ±15V, the power conversion module can be set to ±18V output. In this way, through the power conversion module and the linear power supply regulator circuit, the single 5V power supply programmed output of the V93000 ATE can be converted into a bipolar ±15V output with a high noise suppression ratio to power the operational amplifier. The test signal of the ADC chip under test is generated by the arbitrary waveform generator of the V93000 ATE. The waveform, frequency or period, and output amplitude of the signal can be flexibly controlled through programming.

[0066] Since the maximum amplitude of the V93000 ATE output signal is only ±3.25V. In order to achieve a high swing test signal, the V93000 ATE arbitrary waveform generator needs to be programmed to generate a test signal and input into the operational amplifier circuit for amplification. The amplification gain of the operational amplifier can be set through the V93000 ATE digital channel, thereby increasing the flexibility of the test system. The operational amplifier power supply is powered by the ±15V output of the linear power regulator, which can achieve a high swing test signal output with a peak-to-peak amplitude of approximately 30V. If you want to achieve a test signal output with a higher swing, you can use a power conversion module with a higher output voltage, a linear power regulator and an operational amplifier circuit.

[0067] Before testing the ADC chip under test, the test signal generated by the V93000 ATE arbitrary waveform generator and operational amplifier circuit needs to be calibrated. The calibration acquisition module can select the low-frequency digitizer module of the V93000 ATE, which has an ultra-high resolution of 24 bits, or an external high-resolution digitizer can be selected. The control signal path switching module connects the operational amplifier output to the calibration acquisition module. If the calibration acquisition module uses the low-frequency digitizer of the V93000 ATE, its maximum input range is only ±3V, and the output of the operational amplifier circuit needs to be divided by precision resistors for acquisition and calibration. The acquired calibration data is then fitted by the processor using the calibration fitting compensation algorithm to generate an ideal test signal. The fitting algorithm can be based on the least squares method or other common or special fitting algorithms, and quantify the error between the acquired calibration signal and the ideal test signal. In order to avoid the influence of random noise on the calibration data, multiple calibration acquisitions can be performed and averaged to suppress the influence of random noise as much as possible. Based on the quantization error, a calibrated test signal is generated, and the calibrated test signal is downloaded to the arbitrary waveform generator of the V93000 ATE. The calibration process is repeated until the quantization error is no greater than the preset error. The final calibrated test signal is also called a pre-distortion test waveform. This waveform is downloaded to the arbitrary waveform generator of the V93000 ATE. The arbitrary waveform generator generates a pre-distortion test waveform. After amplification by the operational amplifier, the calibrated pre-distortion test waveform offsets the test signal distortion caused by the arbitrary waveform generator and the operational amplifier, thereby improving the test output signal quality through the calibration process and eliminating the test signal quality degradation caused by the arbitrary waveform generator and the operational amplifier.

[0068] The pre-distortion test waveform is amplified by the operational amplifier and input to the ADC chip under test through the signal path switching module. The digital channel of the V93000 ATE collects the converted digital signal output of the ADC integrated chip under test (5) and stores it in the V93000 ATE. After subsequent digital signal processing, the static and dynamic test parameters of the ADC chip under test are calculated, thereby completing the test of the ADC chip under test.

[0069] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0070] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0071] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0072] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0073] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0074] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0075] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0076] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0077] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A test device for an analog-to-digital converter ADC chip, characterized in that: The equipment includes: a power conversion module, an operational amplifier, and an automatic test equipment ATE, The power conversion module is used to convert the single power supply voltage output by the digital power supply DPS module of the ATE into a dual power supply voltage that meets the driving power supply requirements of the operational amplifier; The operational amplifier is used to amplify the first test signal output by the ATE to generate a second test signal, wherein the second test signal meets the input amplitude requirement of the ADC chip under test; The ADC chip under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to the ATE; and The ATE is used to obtain and output the test parameters of the ADC chip under test based on the signal after the analog-to-digital conversion. The device further comprises: a calibration acquisition module and a processor; the device is also used to perform the following calibration process: The ATE generates a first calibration test signal based on a test signal required by the ADC chip under test; The operational amplifier amplifies the first calibration test signal to generate a second calibration test signal, wherein the second calibration test signal meets the input amplitude requirement of the ADC chip under test; The calibration acquisition module acquires the second calibration test signal; The processor fits the second calibration test signal to generate an ideal test signal, and when a first error between the second calibration test signal and the ideal test signal is greater than a preset error, calibrates the second calibration test signal based on the first error to generate a third calibration test signal, and transmits the third calibration test signal to the ATE; and The ATE generates a new first calibration test signal based on the third calibration test signal to repeatedly perform the calibration process until the error between the generated second calibration test signal and the ideal test signal is no greater than the preset error, wherein the ATE uses the final calibration test signal as the first test signal.

2. The device according to claim 1, characterized in that The processor fits the second calibration test signal using a calibration fit compensation algorithm to generate the ideal test signal.

3. The device according to claim 1, characterized in that The acquisition module is further used to acquire the second calibration test signal multiple times, and the processor is further used to average the multiple acquired second calibration test signals, and fit the averaged second calibration test signal to generate the ideal test signal.

4. The device according to claim 1, characterized in that The processor is further configured to issue an alarm message when the number of cycles of the calibration process exceeds a preset number and a first error between the second calibration test signal and the ideal test signal is greater than the preset error.

5. The device according to claim 1, characterized in that The resolution of the calibration acquisition module is higher than the resolution of the ADC chip under test.

6. The device according to claim 5, characterized in that The calibration acquisition module is a digitizer module in the ATE, or the calibration acquisition module is an independent digitizer module.

7. The device according to claim 1, characterized in that The device also includes: The signal path switching module is used to: switch the signal output by the operational amplifier to the calibration acquisition module when executing the calibration process, and switch the signal output by the operational amplifier to the ADC chip under test when testing the ADC chip under test.

8. The device according to claim 1, characterized in that The device further comprises: a noise suppression module, which is used to suppress the power switch noise of the power conversion module.

9. The device according to claim 8, characterized in that The power conversion module is implemented based on a direct current (DC)-direct current (DC) switching power supply, and the noise suppression module is a linear power supply regulator.

10. A testing method for an ADC chip, characterized in that: The method comprises: The power conversion module amplifies the power supply voltage output by the DPS module of the ATE to meet the driving power demand of the operational amplifier; The operational amplifier amplifies the first test signal output by the ATE to generate a second test signal, wherein the second test signal meets the input amplitude requirement of the ADC chip under test; The ADC chip under test performs analog-to-digital conversion on the second test signal and inputs the analog-to-digital converted signal to ATE; and The ATE obtains and outputs the test parameters of the ADC chip under test based on the analog-to-digital converted signal; The method further comprises performing the following calibration process: The ATE generates a first calibration test signal based on a test signal required by the ADC chip under test; The operational amplifier amplifies the first calibration test signal to generate a second calibration test signal, wherein the second calibration test signal meets the input amplitude requirement of the ADC chip under test; The calibration acquisition module acquires the second calibration test signal; The processor fits the second calibration test signal to generate an ideal test signal, and when a first error between the second calibration test signal and the ideal test signal is greater than a preset error, calibrates the second calibration test signal based on the first error to generate a third calibration test signal, and transmits the third calibration test signal to the ATE; and The ATE generates a new first calibration test signal based on the third calibration test signal to repeatedly perform the calibration process until the error between the generated second calibration test signal and the ideal test signal is no greater than the preset error, wherein the ATE uses the final calibration test signal as the first test signal.

11. The method according to claim 10, characterized in that The processor fits the second calibration test signal using a calibration fit compensation algorithm to generate the ideal test signal.

12. The method according to claim 10, characterized in that During the calibration process, the acquisition module is further used to acquire the second calibration test signal multiple times, and the processor is further used to average the multiple acquired second calibration test signals, and fit the averaged second calibration test signal to generate the ideal test signal.

13. The method according to claim 10, characterized in that The method further includes: when the number of cycles of the calibration process exceeds a preset number and a first error between the second calibration test signal and the ideal test signal is greater than the preset error, the processor issues an alarm message.

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