An FPGA-based AI accelerator optimization system and method

Abstract

The embodiment of the present application discloses an FPGA-based AI accelerator optimization system and method, which relates to the field of chips. The AI ​​accelerator includes an instruction parsing unit, a multiplication-addition calculation unit, a data cache unit, and a general-purpose operation unit; the instruction parsing unit is interconnected with the multiplication-addition calculation unit, the data cache unit, and the general-purpose operation unit to form a parallel network structure, and the parsing unit adopts a serial processing strategy; the multiplication-addition calculation unit is responsible for receiving input data, performing convolution calculation and arithmetic calculation of a convolutional neural network, and the multiplication-addition calculation unit is the minimum logical resource combination of convolution calculation and arithmetic calculation in an FPGA chip; the general-purpose operation unit is used to perform convolution post-processing and image processing operations on the calculation results of the multiplication-addition calculation unit, and the general-purpose operation unit is the minimum resource combination of convolution post-processing and image processing operations in an FPGA chip. This solution can reduce the occupation of FPGA chip logic resources by the AI ​​accelerator and improve resource utilization.

Description

Technical Field

[0001] The application embodiments relate to the chip field, and in particular to an FPGA-based AI accelerator optimization system and method. Background Art

[0002] With the continuous promotion of deep learning research and application, the implementation method of AI accelerator based on convolutional neural network has attracted more and more attention. FPGA, with its high parallel computing advantages and flexibility, is increasingly used in the implementation of AI accelerator.

[0003] In related technologies, in order to improve the processing process and processing efficiency of the AI ​​accelerator, a pre-processing module and a post-processing module are usually added to the front and back processes of the AI ​​accelerator of the FPGA chip respectively. The pre-processing module and the post-processing module require additional deployment of the logic resources of the FPGA chip, which will occupy more logic resources and reduce the computing performance of the AI ​​accelerator. Summary of the invention

[0004] The embodiments of the present application provide an FPGA-based AI accelerator optimization system and method to solve the problem of AI accelerator occupying FPGA chip logic resources and utilization.

[0005] On the one hand, a FPGA-based AI accelerator optimization system is provided, wherein the system is used for an FPGA chip, and the FPGA chip includes the AI ​​accelerator;

[0006] The AI ​​accelerator includes an instruction parsing unit, a multiplication and addition calculation unit, a data cache unit and a general operation unit;

[0007] The instruction parsing unit is interconnected with the multiplication-addition calculation unit, the data cache unit and the general operation unit respectively to form a parallel network structure, and the instruction parsing unit adopts a serial processing strategy to control the multiplication-addition calculation unit, the data cache unit and the general operation unit to perform the CNN network acceleration function;

[0008] The multiplication-addition calculation unit is responsible for receiving input data, performing convolution calculation and multiplication-addition calculation of the convolutional neural network, and the multiplication-addition calculation unit is the minimum logic resource combination for calculating the convolution calculation and arithmetic calculation of the CNN network in the FPGA chip;

[0009] The general operation unit is connected to the multiplication and addition calculation unit and is used to perform convolution post-processing and image processing operations on the calculation results of the multiplication and addition calculation unit. The general operation unit is the minimum resource combination for convolution post-processing and image processing operations in the FPGA chip.

[0010] Specifically, the AI ​​accelerator also includes at least two feature input units, which are connected to the multiplication and addition computing unit and are used for convolution input of a convolutional neural network and data input of arithmetic calculation.

[0011] Specifically, the AI ​​accelerator includes a data cache unit, and the data cache is connected to the feature input unit respectively. The feature input unit reads cache data through the data cache unit and inputs the cache data to the multiplication and addition calculation unit.

[0012] Specifically, the multiplication and addition calculation unit receives the data input of the at least two feature input units to perform convolution and arithmetic calculation;

[0013] The multiplication and addition calculation unit is composed of the programmable logic unit, programmable I / O unit and wiring resources of the FPGA chip, and is used to implement at least one of an adder, a subtractor, an accumulator and a multiplier, and perform convolution calculation and arithmetic calculation. The arithmetic calculation includes addition calculation, subtraction calculation, accumulation calculation, multiplication calculation and square calculation.

[0014] Specifically, the general computing unit includes a resource logic set except for convolution calculation and basic arithmetic calculation in image pre-processing, image post-processing and CNN acceleration process;

[0015] When the multiplication and addition computing unit performs convolution calculation, the convolution post-processing performed by the general computing unit includes normalization, activation and pooling operations on the convolution result.

[0016] Specifically, when the multiplication and addition calculation unit performs image calculation, the pre-processing performed by the general operation unit also includes image scaling, filtering and feature value extraction operations; post-processing includes image scaling, result comparison and sorting operations on the calculation results of the multiplication and addition calculation unit.

[0017] On the other hand, a method for optimizing an AI accelerator based on FPGA is provided, the method comprising:

[0018] Reconstruct the logic resources of the FPGA chip to divide the instruction parsing unit, multiplication and addition calculation unit, data cache unit and general operation unit of the AI ​​accelerator; wherein the multiplication and addition calculation unit is the minimum logic resource combination for calculating the convolution calculation and arithmetic calculation of the CNN network in the FPGA chip, and the general operation unit is the minimum resource combination for the convolution post-processing and image processing calculation in the FPGA chip;

[0019] The instruction parsing unit, the multiplication-addition computing unit, the data cache unit, and the general computing unit of the AI ​​accelerator are interconnected to form a parallel network structure;

[0020] Receiving external instructions through the instruction parsing unit, and controlling the multiplication and addition calculation unit, the data cache unit and the general operation unit to perform a network acceleration function according to the serial processing strategy corresponding to the external instructions;

[0021] Among them, the instruction parsing unit is used to receive and parse the external instructions, the multiplication and addition calculation unit is used to perform convolution and arithmetic calculations according to the parsed instructions, and the general operation unit is used to perform convolution post-processing and image processing operations on the calculation results of the multiplication and addition calculation unit.

[0022] Specifically, the instruction parsing unit receives an external instruction, and controls the multiplication and addition calculation unit, the data cache unit, and the general operation unit to perform a network acceleration function according to a serial processing strategy corresponding to the external instruction, including:

[0023] In response to the instruction parsing unit receiving a first data instruction sent by the instruction generating module, the instruction parsing unit performs instruction parsing on the first data to obtain a first running instruction, wherein the first running instruction includes a serial processing strategy for the multiplication and addition calculation unit, the data cache unit, and the general operation unit, and the instruction generating module is an external module independent of the FPGA chip;

[0024] The feature input unit, the multiplication and addition calculation unit, the data cache unit and the general operation unit execute the first operation instruction;

[0025] In response to the instruction parsing unit receiving the second data instruction sent by the instruction generating module, the instruction parsing unit generates a second running instruction by parsing, where the second running instruction is an instruction that implements a function different from that of the first running instruction.

[0026] The beneficial effects brought about by the technical solution provided in the embodiment of the present application include at least: by integrating the existing image pre-processing module and image post-processing module into the AI ​​accelerator, the convolution calculations and basic arithmetic calculations involved in each module are extracted and separately combined into a multiplication-addition calculation unit, and the remaining functions of convolution post-processing and image processing are integrated into the general-purpose operation unit, ensuring that the multiplication-addition calculation unit can be used as the minimum logical resource combination for calculating the convolution calculation and arithmetic calculation of the CNN network in the FPGA chip, and the general-purpose operation unit can be used as the minimum resource combination for the convolution post-processing and image processing operations in the FPGA chip; the reconstructed AI accelerator system is set to a serial processing structure, and the feature input unit, the multiplication-addition calculation unit, the data cache unit and the general-purpose operation unit are controlled to work together according to the running instructions received and parsed by the instruction parsing unit, thereby improving the utilization rate of the FPGA logic resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1It is a system structure diagram of an existing FPGA internal AI accelerator provided in an embodiment of the present application;

[0028] Figure 2 It is a schematic diagram of the internal structure of the FPGA provided in the embodiment of the present application;

[0029] Figure 3 is a system structure diagram of the optimized AI accelerator provided in an embodiment of the present application;

[0030] Figure 4 This is an FPGA-based AI accelerator optimization method provided by another embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0032] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0033] like Figure 1 As shown, it is a system structure diagram of the AI ​​accelerator inside the FPGA in the related technology. It specifically includes a CNN acceleration module, an image pre-processing module, and an image post-processing module. Each module occupies part of the logic circuit in the FPGA chip. The function of the CNN acceleration module is mainly to realize the convolution calculation of the neural network, including a CNN acceleration instruction set. The instruction set is used to find and control the logical execution order of each internal unit or logic circuit of the CNN acceleration module, including a feature cache unit and a convolution multiplication and addition calculation unit. In addition, it also includes an acceleration unit for normalization, activation, and pooling functions, and the CNN acceleration module also includes a corresponding data cache unit for storing temporary data cached during the acceleration process.

[0034] However, AI accelerators often do not simply perform simple convolution calculations. For general AI accelerators, in order to ensure the network acceleration function, it is usually necessary to add image pre-processing modules and image post-processing modules in the FPGA chip for image processing. Correspondingly, two additional logic resources (or logic circuits) need to be allocated from the FPGA chip for resource deployment. For AI accelerators, which are already very resource-intensive system applications, the increase in logic resources requires the use of larger-scale FPGA chips, which correspondingly increases product costs and wiring pressure.

[0035] Figure 2It is an internal structure diagram of the FPGA chip. It includes a large number of programmable logic units (CLB) 21, programmable I / O units 22, wiring resources 23 and lookup tables (LUT) 24 and other resources. The FPGA structure includes a large number of programmable logic units 21. The programmable logic unit 21 is the basic unit for realizing user functions. Through the connection with the wiring resources 23, a searchable and editable logic circuit can be formed to complete the corresponding execution functions, such as addition and subtraction operations, multiplication and addition, and square calculations, etc., especially for CNN network composition convolution calculation circuits, etc. The more complex the calculation function to be realized, the more logic resources need to be deployed in the FPGA. The lookup table 24 is essentially a RAM, which realizes address search through several bits of address lines to locate the specific location of the logic resources in the FPGA.

[0036] In the existing AI accelerator structure, in order to pursue high performance and high response speed, the AI ​​structure is set as a multi-module parallel processing structure. Each unit module needs to occupy more logic resources (CLB and wiring resources) in the FPGA. When the FPGA chip carries other processes or services, it will affect the processing speed of other processes and the overall working performance of the chip. At the same time, the use efficiency of the logic resources within each module is not high, which leads to a waste of logic resources.

[0037] This solution provides a way to restructure and optimize the structure of existing AI accelerators, such as Figure 3 , which is a structural diagram of an FPGA-based AI accelerator optimization system provided in an embodiment of the present application.

[0038] The essence of AI accelerators is to realize the forward calculation and processing of neural networks. Therefore, when optimizing the layout, we consider the minimum execution unit and try to reduce the occupation of logic resources as much as possible while ensuring the realization of functions. For the image pre-processing module and the image post-processing module, it is essentially the processing process of image data, and the CNN acceleration process is to perform convolution calculations on the parameters. Therefore, based on the convolution calculation of data and basic arithmetic calculations, and the minimum resource combination required to realize the function, the multiplication and addition calculation unit is composed of the basic convolution calculation, addition calculation, subtraction calculation, multiplication calculation, multiplication and addition operation and square calculation as the unit, and deploys corresponding programmable logic units, programmable I / O interfaces, wiring resources, lookup tables, digital signal processors and other resources.

[0039] At the same time, in order to avoid the waste of resources caused by parallel processing of logical resources, the AI ​​acceleration structure is reconstructed into serial processing logic. For the general-purpose operation unit, the logic resources involved in basic arithmetic calculations and convolution calculations are omitted, and instead executed in coordination with the multiplication and addition calculation unit. Because whether it is the activation and pooling operations in the CNN acceleration module, or the functions such as feature extraction, image data scaling, comparison and sorting, logic resources need to be allocated separately to achieve basic arithmetic or convolution calculations, so a large amount of logic resources and wiring resources need to be allocated. When using serial processing, when the general-purpose operation unit needs to perform calculations, the multiplication and addition calculation unit is called through the lookup table to continue processing.

[0040] like Figure 3 As shown, in order to reduce resource occupation, at least two feature input units are used to implement two-phase input of basic data addition and subtraction calculations, multiplication calculations or convolution calculations. In addition, after adding a small amount of logic resources, division calculations can be implemented, which can further reduce the logic resource occupation of the general operation unit. The feature input unit is connected to the cache unit and is responsible for reading data from the data cache unit, so that the calculations of various functions can run efficiently in parallel.

[0041] The general operation unit and the data cache module are interconnected, and are used to read cached data from the data cache unit on the one hand, cache operation results on the other hand, and cache data from the data cache module for corresponding operations according to the running instructions. And considering that the CNN acceleration instruction set is separately set in the existing CNN acceleration module, it is necessary to generate instructions and control the operation of each functional module according to the acceleration instruction set, which further occupies logical resources. Therefore, the present invention adopts external input instructions, which are parsed and controlled by the instruction parsing unit. The external instructions are generated by the instruction generation module according to the functions implemented by the AI ​​accelerator as required, and can specifically be the instruction compiler on the CPU processor. The instruction parsing unit is responsible for receiving and identifying external instructions, and controlling the operation of each unit according to the recognition results. Due to the use of serial processing strategy control, the AI ​​accelerator needs to execute the image pre-processing process, the convolution calculation process and the image post-processing process in sequence, and the execution process requires the coordinated participation of the data cache unit, the multiplication and addition calculation unit, the general operation unit and the feature input unit, so that the utilization rate of FPGA logic resources can be improved.

[0042] The FPGA chip is also equipped with a DDR access controller. The on-chip DDR access controller is located between the data cache unit of the AI ​​accelerator and the off-chip memory, and is used for efficient data interaction between the data cache unit and the off-chip memory.

[0043] Since the functions of the image pre-processing and image post-processing modules are integrated into the AI ​​accelerator, the use of data cache units can be reduced. The feature input unit and the general computing unit use a data cache unit for reading, which can improve the execution efficiency of the AI ​​accelerator.

[0044] Figure 4 The FPGA-based AI accelerator optimization method provided in the embodiment of the present application includes the following steps:

[0045] Step 401, reconstruct the logic resources of the FPGA chip to divide the instruction parsing unit, multiplication and addition calculation unit, data cache unit and general operation unit of the AI ​​accelerator.

[0046] Considering the parallel processing logic used by existing AI accelerators, and the parallel processing logic requires the deployment of image processing pre-modules, CNN acceleration modules and image processing post-modules in the FPGA chip, and each module has relatively independent complete functions, there will be a problem that the logic resources cannot be efficiently utilized. In addition, the required FPGA scale is relatively large, which increases the cost investment and internal wiring pressure. After the logic resources are reconstructed, the instruction parsing unit, multiplication and addition calculation unit, data cache unit and general operation unit of the AI ​​accelerator are re-divided. Among them, the multiplication and addition calculation unit is the minimum logic resource combination for calculating the convolution calculation and arithmetic calculation of the CNN network in the FPGA chip, and the general operation unit is the minimum resource combination for convolution post-processing and image processing calculation in the FPGA chip. That is, the combination unit with corresponding functions is composed of the least programmable logic units, programmable I / O units and wiring resources, and a large number of logic resources for convolution calculation and arithmetic calculation are omitted in this resource combination, and the convolution calculation and arithmetic calculation functions are extracted separately and set as multiplication and addition calculation units.

[0047] Step 402: interconnect the instruction parsing unit, multiplication and addition computing unit, data cache unit, and general computing unit of the AI ​​accelerator to form a parallel network structure.

[0048] The reconstructed AI accelerator forms a parallel network structure to ensure that the instruction parsing unit, multiplication and addition calculation unit, data cache unit, and general operation unit can work together when executing instructions, thus preventing the units or modules from being idle and occupying the logic resources of the FPGA.

[0049] Step 403, receiving an external instruction through the instruction parsing unit, and controlling the multiplication and addition calculation unit, the data cache unit and the general operation unit to execute the network acceleration function according to the serial processing strategy corresponding to the external instruction.

[0050] The instruction parsing unit receives instructions generated by the external instruction generation module, which may include instructions such as image scaling, filtering and feature extraction before image processing, convolution, normalization and pooling during network acceleration, and image scaling, comparison and sorting after image processing. After receiving the corresponding data instructions, the instruction parsing unit controls the coordinated operation of various units inside the AI ​​accelerator. Specifically, it includes the following steps:

[0051] Step S1, in response to the instruction parsing unit receiving the first data instruction sent by the instruction generating module, performs instruction parsing on the first data to obtain a first running instruction, wherein the first running instruction includes a serial processing strategy for a multiplication and addition calculation unit, a data cache unit and a general operation unit.

[0052] As mentioned above, the reconstructed AI processor adopts a serial execution strategy. When the instruction parsing unit receives the first data instruction sent by the instruction generation module, it parses the first data instruction to obtain the first operation instruction. The first operation instruction includes a serial processing strategy for the multiplication and addition calculation unit, the data cache unit, and the general operation unit. For example, the first data instruction corresponds to the filtering function of image pre-processing, and the instruction parsing unit generates a first operation instruction containing multiple instructions according to the filtering function. The first operation instruction includes the processing sequence instructions of the multiplication and addition calculation unit, the data cache unit, and the general operation unit, and the multiplication and addition calculation unit, the data cache unit, and the general operation unit perform corresponding functions according to their corresponding instruction data.

[0053] Step S2, controlling the feature input unit, the multiplication and addition calculation unit, the data cache unit and the general operation unit to execute the first operation instruction.

[0054] Schematically, for example, the filtering process first inputs the convolution data through the feature input unit, then performs the convolution calculation through the multiplication and addition calculation unit, and then the calculation result is filtered by the general operation unit, and the generated cache is stored in the data cache unit. When the convolution calculation and basic arithmetic calculation need to be performed during the filtering process, the input is read through the data cache unit and sent to the multiplication and addition calculation unit. This process requires the logic circuits of all units to participate in the operation.

[0055] Step S3, in response to the instruction parsing unit receiving the second data instruction sent by the instruction generating module, the instruction parsing unit parses and generates a second operation instruction, where the second operation instruction is an instruction that implements a function different from that of the first operation instruction.

[0056] Due to the adoption of a serial execution strategy, when the first operation instruction is executed, the instruction parsing unit receives the second data instruction sent by the external instruction generation module again, and performs data parsing to obtain the second operation instruction, which is different from the first operation instruction. For example, if the first operation instruction is to implement the image filtering function before processing, the second instruction is expressed as switching the AI ​​accelerator to the CNN acceleration function, that is, the convolution processing and convolution post-processing process, which may include convolution processing, normalization, activation and pooling processes, and also requires the collaborative participation of all units. Due to the reconfiguration in the FPGA, the function is switched by reloading the bit, and the switching delay time is generally above the millisecond level. In addition, a third operation instruction may also be included, and the third operation instruction corresponds to the image post-processing process, such as data comparison and sorting processes. This embodiment will not be described in detail.

[0057] The response time of this solution is much less than microseconds, and it has high flexibility. Since the reconstructed AI accelerator greatly reduces the logical resources occupied by the FPGA chip, it can avoid the processing speed of FPGA processing other processes, and for the reconstructed AI processor, it can maximize the use of logical resources for processing tasks, thereby improving the utilization rate of logical resources in the FPGA chip.

[0058] To summarize, in the embodiment of the present application, by integrating the existing image pre-processing module and the image post-processing module into the AI ​​accelerator, the convolution calculations and basic arithmetic calculations involved in each module are extracted and combined into a multiplication-addition calculation unit separately, and the remaining functions of the remaining image pre-processing and post-processing are integrated into the general-purpose operation unit, ensuring that the multiplication-addition calculation unit can be used as the minimum logical resource combination for calculating CNN network convolution calculations and basic arithmetic calculations in the FPGA chip, and the general-purpose operation unit can be used as the minimum resource combination for convolution post-processing and image processing operations in the FPGA chip; the reconstructed AI accelerator system is set to a serial processing structure, and the feature input unit, the multiplication-addition calculation unit, the data cache unit and the general-purpose operation unit are controlled to work together according to the running instructions received and parsed by the instruction parsing unit, thereby improving the utilization rate of the FPGA logic resources.

[0059] The preferred embodiments of the present invention are described above; it should be understood that the present invention is not limited to the above-mentioned specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify them into equivalent embodiments with equivalent changes, which does not affect the essential content of the present invention; therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. An FPGA-based AI accelerator optimization system, characterized in that: The system is used for an FPGA chip, and the FPGA chip includes the AI ​​accelerator; The AI ​​accelerator includes an instruction parsing unit, a multiplication and addition calculation unit, a data cache unit and a general operation unit; The instruction parsing unit is interconnected with the multiplication-addition calculation unit, the data cache unit and the general operation unit respectively to form a parallel network structure, and the instruction parsing unit adopts a serial processing strategy to control the multiplication-addition calculation unit, the data cache unit and the general operation unit to perform the CNN network acceleration function; The multiplication and addition calculation unit is responsible for receiving input data, performing convolution calculation and multiplication and addition calculation of the convolutional neural network, and the multiplication and addition calculation unit is the minimum logic resource combination for calculating the convolution calculation and arithmetic calculation of the CNN network in the FPGA chip; the multiplication and addition calculation unit is composed of the programmable logic unit, programmable I / O unit and wiring resources of the FPGA chip, and is used to implement at least one of an adder, a subtractor, an accumulator and a multiplier, and perform convolution calculation and arithmetic calculation; the arithmetic calculation includes addition calculation, subtraction calculation, accumulation calculation, multiplication calculation and square calculation; The general operation unit is connected to the multiplication and addition calculation unit, and is used to perform convolution post-processing and image processing operations on the calculation results of the multiplication and addition calculation unit. The general operation unit is a minimum resource combination of convolution post-processing and image processing operations in the FPGA chip, including a resource logic set except convolution calculation and basic arithmetic calculation in image pre-processing, image post-processing and CNN acceleration process; When the multiplication and addition computing unit performs convolution computing, the convolution post-processing performed by the general computing unit includes normalizing, activating and pooling the convolution result; When the multiplication and addition calculation unit performs image calculation, the pre-processing performed by the general operation unit also includes image scaling, filtering and feature value extraction operations; the post-processing includes image scaling, result comparison and sorting operations on the calculation results of the multiplication and addition calculation unit.

2. The AI ​​accelerator optimization system according to claim 1, characterized in that: The AI ​​accelerator also includes at least two feature input units, which are connected to the multiplication and addition computing unit and are used for convolution input of a convolutional neural network and data input of arithmetic calculation.

3. The AI ​​accelerator optimization system according to claim 2, characterized in that: The AI ​​accelerator includes a data cache unit, and the data cache is connected to the feature input unit respectively. The feature input unit reads cache data through the data cache unit and inputs the cache data into the multiplication and addition calculation unit.

4. The AI ​​accelerator optimization system according to claim 3, characterized in that: The multiplication and addition calculation unit receives data input from the at least two feature input units to perform convolution and arithmetic calculations.

5. An FPGA-based AI accelerator optimization method, characterized in that: The method comprises: Reconstruct the logic resources of the FPGA chip to divide the instruction parsing unit, multiplication and addition calculation unit, data cache unit and general operation unit of the AI ​​accelerator; wherein the multiplication and addition calculation unit is the minimum logic resource combination for calculating the convolution calculation and arithmetic calculation of the CNN network in the FPGA chip, and the multiplication and addition calculation unit is composed of the programmable logic unit, programmable I / O unit and wiring resources of the FPGA chip, and is used to implement at least one of an adder, a subtractor, an accumulator and a multiplier, and perform convolution calculation and arithmetic calculation; arithmetic calculation includes addition calculation, subtraction calculation, accumulation calculation, multiplication calculation and square calculation; the general operation unit is the minimum resource combination for convolution post-processing and image processing operations in the FPGA chip, and the general operation unit includes a resource logic set except convolution calculation and basic arithmetic calculation in image pre-processing, image post-processing and CNN acceleration process; When the multiplication and addition computing unit performs convolution computing, the convolution post-processing performed by the general computing unit includes normalizing, activating and pooling the convolution result; When the multiplication and addition calculation unit performs image calculation, the pre-processing performed by the general operation unit also includes image scaling, filtering and feature value extraction operations; the post-processing includes image scaling, result comparison and sorting operations on the calculation results of the multiplication and addition calculation unit; The instruction parsing unit, the multiplication-addition computing unit, the data cache unit, and the general computing unit of the AI ​​accelerator are interconnected to form a parallel network structure; Receiving external instructions through the instruction parsing unit, and controlling the multiplication and addition calculation unit, the data cache unit and the general operation unit to perform a network acceleration function according to the serial processing strategy corresponding to the external instructions; Among them, the instruction parsing unit is used to receive and parse the external instructions, the multiplication and addition calculation unit is used to perform convolution and arithmetic calculations according to the parsed instructions, and the general operation unit is used to perform convolution post-processing and image processing operations on the calculation results of the multiplication and addition calculation unit.

6. The method according to claim 5, characterized in that The instruction parsing unit receives an external instruction, and controls the multiplication and addition calculation unit, the data cache unit, and the general operation unit to perform a network acceleration function according to a serial processing strategy corresponding to the external instruction, including: In response to the instruction parsing unit receiving a first data instruction sent by the instruction generating module, the instruction parsing unit performs instruction parsing on the first data to obtain a first running instruction, wherein the first running instruction includes a serial processing strategy for the multiplication and addition calculation unit, the data cache unit, and the general operation unit, and the instruction generating module is an external module independent of the FPGA chip; The feature input unit, the multiplication and addition calculation unit, the data cache unit and the general operation unit execute the first operation instruction; In response to the instruction parsing unit receiving the second data instruction sent by the instruction generating module, the instruction parsing unit generates a second running instruction by parsing, where the second running instruction is an instruction that implements a function different from that of the first running instruction.

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