Enhanced GaN PMOS device based on oxidation corrosion and preparation method

Abstract

The application relates to an enhanced GaN PMOS device based on oxidation corrosion and a preparation method, and the preparation method comprises the following steps: sequentially growing a nucleation layer, a GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, a p-type AlGaN layer and a p-type GaN cap layer on a substrate; etching off the p-type GaN cap layer in a gate region to expose the p-type AlGaN layer; selectively oxidizing the exposed p-type AlGaN layer and the p-type GaN cap layer, so that the p-type AlGaN layer forms an oxidized AlGaN layer; wet-etching the oxidized AlGaN layer to expose the GaN channel layer and form a gate recess structure; preparing a source electrode on the p-type GaN cap layer on one side of the gate recess structure and preparing a drain electrode on the p-type GaN cap layer on the other side; preparing a dielectric layer on the surfaces of the source electrode, the drain electrode, the p-type GaN cap layer and the gate recess structure; and preparing a gate electrode on the dielectric layer. The preparation method not only guarantees the etching depth while avoiding over-etching, but also protects the channel from being damaged by plasma etching, so that a better surface morphology is obtained, and the influence of surface states on the channel mobility is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microelectronics, and particularly relates to an enhanced GaN PMOS device based on oxidation corrosion and a preparation method. BACKGROUND

[0002] Ⅲ-V wide bandgap nitride semiconductor materials represented by GaN are important semiconductor materials for manufacturing microwave power devices, power electronic devices and light emitting diodes.

[0003] In recent years, GaN-based MOS devices have developed rapidly, especially the depletion mode and enhancement mode n-channel MOS tubes based on AlGaN / GaN heterojunction, which have the advantages of high working current, high breakdown voltage and high reliability. However, due to the difficulty of p-type doping of GaN material and the high background carrier concentration, the PMOS based on GaN material has a low working current. In addition, in order to realize the enhancement mode GaN-based MOS tube, a recessed gate etching technology is often used to deplete the two-dimensional electron gas or hole gas at the channel. This technology inevitably causes a certain damage to the channel, reduces the concentration and mobility of the carriers at the channel, and leads to the decline of the overall performance of the device. For PMOS, this will further reduce the overall performance of the device. Therefore, it is necessary to reduce or eliminate the etching damage, so as to realize the high threshold voltage and high performance of the enhancement mode GaN PMOS device.

[0004] In the past, researchers have applied a series of optimization methods to avoid or reduce the damage caused by etching to the device, such as gate annealing repair, TMAH repair, and the combination of shallow etching and ion treatment. However, whether it is annealing repair or TMAH repair, the repair ability of etching damage is limited, and it is difficult to greatly improve the performance of the device; although the combination of shallow etching and ion treatment effectively protects the channel, the depletion effect of ion treatment on the channel carriers is limited, and it is difficult to achieve a high threshold voltage. Therefore, it is urgent to find a method to realize high-performance PMOS devices with small etching damage and the ability to protect the channel. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides an enhanced GaN PMOS device based on oxidation corrosion and a preparation method. The technical problems to be solved by the application are solved by the following technical scheme:

[0006] The embodiment of the application provides a preparation method of an enhanced GaN PMOS device based on oxidation corrosion, comprising the following steps:

[0007] S1, growing a nucleation layer, a GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, a p-type AlGaN layer and a p-type GaN cap layer on a substrate in sequence;

[0008] S2, etching away the p-type GaN cap layer of the gate region to expose the p-type AlGaN layer;

[0009] S3, selectively oxidizing the exposed p-type AlGaN layer and the p-type GaN cap layer so that the p-type AlGaN layer forms an oxidized AlGaN layer;

[0010] S4, wet etching the oxidized AlGaN layer with an etching solution to expose the GaN channel layer, forming a gate recess structure;

[0011] S5, preparing a source electrode on the p-type GaN cap layer on one side of the gate recess structure and a drain electrode on the p-type GaN cap layer on the other side;

[0012] S6, preparing a dielectric layer on the surfaces of the source electrode, the drain electrode, the p-type GaN cap layer and the gate recess structure;

[0013] S7, preparing a gate electrode on the dielectric layer so that the gate electrode is located in the gate recess structure.

[0014] In an embodiment of the present application, the material of the substrate comprises one or more of sapphire, silicon carbide, silicon, gallium nitride.

[0015] In an embodiment of the present application, the nucleation layer, the GaN buffer layer, the AlGaN back barrier layer, the GaN channel layer, the p-type AlGaN layer and the p-type GaN cap layer are sequentially grown on the substrate by a metal organic chemical vapor deposition process.

[0016] In an embodiment of the present application, the material of the nucleation layer comprises one or more of AlN and GaN.

[0017] In an embodiment of the present application, the thickness of the nucleation layer is 10-100 nm,

[0018] The thickness of the GaN buffer layer is 2-4 μm,

[0019] The thickness of the AlGaN back barrier layer is 10-30 nm;

[0020] The thickness of the GaN channel layer is 3-5 nm,

[0021] The thickness of the p-type AlGaN layer is 50-70 nm,

[0022] The thickness of the p-type GaN cap layer is 1-3 nm.

[0023] In an embodiment of the present application, step S3 comprises:

[0024] The exposed p-type AlGaN layer and the p-type GaN cap layer are selectively oxidized at a temperature of 600-700℃ and an oxygen flow of 3-5L / min for 50-70min, so that the p-type AlGaN layer forms an oxidized AlGaN layer.

[0025] In an embodiment of the present application, the etching solution comprises one or more of KOH solution, NaOH solution, TMAH solution.

[0026] In an embodiment of the present application, step S4 comprises:

[0027] The oxidized AlGaN layer is etched in a KOH solution at a temperature of 70-80℃ for 40-60min, so that the GaN termination layer is exposed.

[0028] In an embodiment of the present application, the material of the dielectric layer comprises one or more of SiN x , SiO2, Al2O3, HfO2, and has a thickness of 10-30nm.

[0029] Another embodiment of the present application provides a preparation method of an enhanced GaN PMOS device based on oxidation etching, which is prepared by the preparation method according to any one of the above embodiments, and comprises a substrate, a nucleation layer, a GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, a p-type AlGaN layer, a p-type GaN cap layer, a dielectric layer, a source electrode, a drain electrode and a gate electrode, wherein,

[0030] The substrate, the nucleation layer, the GaN buffer layer, the AlGaN back barrier layer, the GaN channel layer, the p-type AlGaN layer and the p-type GaN cap layer are sequentially stacked;

[0031] The p-type AlGaN layer and the p-type GaN cap layer form a gate recess structure in the middle part thereof;

[0032] The source electrode is located on the p-type GaN cap layer at one side of the gate recess structure, and the drain electrode is located on the p-type GaN cap layer at the other side of the gate recess structure;

[0033] The dielectric layer is located on the surfaces of the source electrode, the drain electrode, the p-type GaN cap layer and the gate recess structure;

[0034] The gate electrode is located on the dielectric layer and in the gate recess structure.

[0035] Compared with the prior art, the present application has the following beneficial effects:

[0036] The application utilizes selective oxidation of GaN and AlGaN, first selectively oxidizes the p-type AlGaN layer to form an oxidized AlGaN layer, and then etches the oxidized AlGaN layer by wet etching, adopts the combination of oxidation and wet etching, the oxidized AlGaN layer is more easily etched by wet etching, and GaN is not easily oxidized, so it is not easily etched, so that the etching is automatically terminated at the GaN interface, not only the etching depth is ensured, but also the over-etching is avoided, and the channel is protected from damage by plasma etching, a better surface morphology is obtained, the influence of the surface state on the channel mobility is reduced, and the overall performance of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A flowchart of a preparation method of an enhanced GaN PMOS device based on oxidation etching is provided for the embodiment of the application.

[0038] Figures 2a-2l A process diagram of a preparation method of an enhanced GaN PMOS device based on oxidation etching is provided for the embodiment of the application.

[0039] Figure 3 A structure diagram of an enhanced GaN PMOS device based on oxidation etching is provided for the embodiment of the application. DETAILED DESCRIPTION

[0040] The application will be further described in detail below in combination with specific embodiments, but the embodiments of the application are not limited thereto.

[0041] Embodiment one

[0042] Please refer to Figure 1 and Figures 2a-2l , Figure 1 A flowchart of a preparation method of an enhanced GaN PMOS device based on oxidation etching is provided for the embodiment of the application, Figures 2a-2l A process diagram of a preparation method of an enhanced GaN PMOS device based on oxidation etching is provided for the embodiment of the application. The preparation method utilizes selective oxidation of GaN and AlGaN, oxidizes the AlGaN for a certain time, then etches the oxidized AlGaN by using an etching solution and stops at the GaN / AlGaN interface, realizes self-terminated recessed gate fabrication, realizes high-threshold-voltage enhanced PMOS, avoids damage to the channel by etching, and improves the overall performance of the GaN PMOS.

[0043] The preparation method specifically includes the following steps:

[0044] S1, growing a nucleation layer 2, a GaN buffer layer 3, an AlGaN back barrier layer 4, a GaN channel layer 5, a p-type AlGaN layer 6 and a p-type GaN cap layer 7 on the substrate 1 in sequence.

[0045] The step S1 specifically comprises:

[0046] S11, growing a nucleation layer 2 on the substrate 1, please refer to Figure 2a .

[0047] Specifically, the material of the substrate 2 includes one or more of sapphire, silicon carbide, silicon, gallium nitride. The material of the nucleation layer 2 includes one or more of AlN, GaN.

[0048] First, the substrate 1 is sequentially placed in a hydrofluoric acid solution, an acetone solution, an anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes, and finally dried with nitrogen; the cleaned substrate 1 is placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, the vacuum degree of the reaction chamber is reduced to less than 2x10 - 2 Torr; then a mixed gas of hydrogen and ammonia is introduced into the reaction chamber, the substrate 1 is heated to a temperature of 900-1200℃ under the condition that the pressure of the MOCVD reaction chamber reaches 20-760 Torr, and maintained for 5-10 min, completing the heat treatment of the substrate 1.

[0049] Then grow a nucleation layer 2 on the heat-treated substrate 1.

[0050] When the material of the nucleation layer 2 is AlN, the growth process is: using a metal-organic chemical vapor deposition (MOCVD) process to grow a 10-100 nm thick AlN nucleation layer 2 under the condition that the pressure of the reaction chamber is 20-60 Torr, the temperature is 700-900℃, the hydrogen flow rate is 1200 sccm, the ammonia flow rate is 200-300 sccm, and the aluminum source flow rate is 100-300 sccm.

[0051] When the material of the nucleation layer 2 is GaN, the growth process is: using a MOCVD process to grow a 10-100 nm thick GaN nucleation layer 2 under the condition that the pressure of the reaction chamber is 20-60 Torr, the temperature is 520-560℃, the gallium source flow rate is 50-100 sccm, the hydrogen flow rate is 1200 sccm, and the ammonia flow rate is 3000-4000 sccm.

[0052] S12, growing a GaN buffer layer 3 on the nucleation layer 2, please refer to Figure 2b .

[0053] Specifically, the MOCVD process is adopted to grow 2-4 μm of GaN material to form the GaN buffer layer 3 under the conditions of 20-60 Torr of reaction chamber pressure, 1000-1200 °C of temperature, 1200 sccm of hydrogen flow rate, 150-180 sccm of gallium source flow rate, and 2000-5000 sccm of ammonia flow rate.

[0054] S13, growing the AlGaN back barrier layer 4 on the GaN buffer layer 3, please refer to Figure 2c .

[0055] Specifically, the MOCVD process is adopted to grow 10-30 nm of AlGaN back barrier layer 4 under the conditions of 20-60 Torr of reaction chamber pressure, 1000-1200 °C of temperature, 20-50 sccm of Al source flow rate, 100-150 sccm of Ga source flow rate, 3000-6000 sccm of ammonia flow rate, and 1200 sccm of hydrogen flow rate.

[0056] S14, growing the GaN channel layer 5 on the AlGaN back barrier layer 4, please refer to Figure 2d .

[0057] Specifically, the MOCVD process is adopted to grow 3-5 nm of GaN material to form the GaN channel layer 5 under the conditions of 20-60 Torr of reaction chamber pressure, 1000-1200 °C of temperature, 1200 sccm of hydrogen flow rate, and 150-180 sccm of gallium source flow rate, and 2000-5000 sccm of ammonia flow rate.

[0058] S15, growing the p-type AlGaN layer 6 on the GaN channel layer 5, please refer to Figure 2e .

[0059] Specifically, the MOCVD process is adopted to grow 50-70 nm of p-type AlGaN layer 6 under the conditions of 20-60 Torr of reaction chamber pressure, 1000-1200 °C of temperature, 5-20 sccm of Al source flow rate, 100-150 sccm of Ga source flow rate, 100-180 sccm of Mg source flow rate, 3000-6000 sccm of ammonia flow rate, and 1200 sccm of hydrogen flow rate.

[0060] S16, growing the p-type GaN cap layer 7 on the p-type AlGaN layer 6, please refer to Figure 2f .

[0061] Specifically, the p-type GaN cap layer 7 with a thickness of 1-3 nm is grown by using the MOCVD process under the conditions of a reaction chamber pressure of 20-60 Torr, a temperature of 1000-1200 °C, a hydrogen flow rate of 1200 sccm, a gallium source flow rate of 150-180 sccm, an ammonia flow rate of 2000-5000 sccm, and a Mg source flow rate of 200-300 sccm.

[0062] After the p-type GaN cap layer 7 is grown, the mesa isolation of the device is formed by using the photolithography and etching processes.

[0063] S2, the p-type GaN cap layer 7 in the gate region is etched to expose the p-type AlGaN layer 6, please refer to Figure 2g .

[0064] Specifically, the p-type GaN cap layer 7 in the gate region is completely etched by using the photolithography and etching processes to expose the p-type AlGaN layer 6, wherein the gate region is located at the middle part of the p-type device.

[0065] In this embodiment, the depth of etching the p-type GaN cap layer 7 is greater than or equal to the thickness of the p-type GaN cap layer 7 and less than the sum of the thicknesses of the p-type GaN cap layer 7 and the p-type AlGaN layer 6, that is, the p-type GaN cap layer 7 is completely etched, a part of the p-type AlGaN layer 6 can be etched, or the p-type AlGaN layer 6 can not be etched, and the surface of the p-type AlGaN layer 6 can be exposed. Preferably, the p-type GaN cap layer 7 is over-etched, and a part of the p-type AlGaN layer 6 is etched to ensure that the surface of the p-type AlGaN layer 6 is exposed.

[0066] S3, the exposed p-type AlGaN layer 6 and p-type GaN cap layer 7 are selectively oxidized to form an oxidized AlGaN layer 6', please refer to Figure 2h .

[0067] Specifically, the exposed p-type AlGaN layer 6 and p-type GaN cap layer 7 are selectively high-temperature oxidized under the conditions of a temperature of 600-700 °C and an oxygen flow rate of 3-5 L / min, and the oxidation time is 50-70 min, so that the p-type AlGaN layer 6 forms the oxidized AlGaN layer 6'.

[0068] In this embodiment, since AlGaN and GaN have the characteristics of selective oxidation, the oxidation rates of the two are different, AlGaN is more easily oxidized, and GaN is not easily oxidized. Therefore, when the sample is oxidized with oxygen, AlGaN is more easily oxidized to form the structure of AlOGaN, that is, the oxidized AlGaN layer 6', and GaN remains the original lattice structure.

[0069] S4, etching the AlGaN layer 6' with a corrosion solution to expose the GaN channel layer 5 and form a gate recess structure 11', see Figure 2i .

[0070] In this embodiment, the corrosion solution is an alkaline solution, including one or more of KOH solution, NaOH solution, and TMAH solution.

[0071] Specifically, the AlGaN layer 6' is etched in a KOH solution at a temperature of 70-80℃ for 40-60min to expose the GaN channel layer 5 and form the gate recess structure 11'.

[0072] The conventional plasma etching method causes great damage to the channel, and the high surface state density caused by etching damage has a great scattering effect on the carriers in the channel, which reduces the mobility of the channel carriers and leads to a decrease in the overall performance of the enhancement-mode device realized by the plasma etching method. In this embodiment, the different oxidation rates of GaN and AlGaN are utilized to combine oxidation with KOH wet etching, which can protect the channel from plasma etching damage, obtain a better surface morphology, cause less damage to the conductive channel, reduce the influence of surface states on the channel mobility, and thus improve the overall performance of the device.

[0073] In addition, due to the instability of the process, the conventional plasma etching often leads to over-etching or insufficient etching depth, which has a great influence on the threshold voltage and working current of the device. In this embodiment, the different oxidation rates of GaN and AlGaN are utilized to make the KOH etching of AlGaN material that is more easily oxidized, and since GaN is not easily oxidized, the KOH etching automatically stops at the GaN interface, thereby ensuring the etching depth while avoiding over-etching.

[0074] S5, preparing a source electrode 9 on the p-type GaN cap layer 7 on one side of the gate recess structure 11' and a drain electrode 10 on the p-type GaN cap layer 7 on the other side, see Figure 2j .

[0075] Specifically, Ni / Au is sputtered on the source and drain regions by photolithography and magnetron sputtering process, and the source electrode 9 and the drain electrode 10 are formed by annealing at a high temperature of 550℃, wherein the source electrode 9 is located on the p-type GaN cap layer 7 on one side of the gate recess structure 11', and the drain electrode 10 is located on the p-type GaN cap layer 7 on the other side of the gate recess structure 11'.

[0076] S6, preparing a dielectric layer 8 on the surfaces of the source electrode 9, the drain electrode 10, the p-type GaN cap layer 7, and the gate recess structure 11', see Figure 2k .

[0077] Specifically, the PEALD or PECVD technology is used to deposit the dielectric layer 8 on the sample after the source and drain electrodes are deposited, and the material of the dielectric layer 8 includes one or more of SiN x , SiO2, Al2O3, HfO2, and has a thickness of 10-30 nm.

[0078] S7, the gate 11 is prepared on the dielectric layer 8, so that the gate 11 is located in the gate recess structure 11', please refer to Figure 2l .

[0079] Specifically, the photolithography and magnetron sputtering process are used to sputter Ni / Pt / Au or Ni / Au in the gate region to form the gate electrode 11, wherein the gate 11 is a T-shaped gate, the gate leg is located in the gate recess structure 11', and the gate cap is located on the gate leg and the dielectric layer 8.

[0080] Then, the dielectric layer 8 in the contact area of the source 9 and the drain 10 is etched away by photoetching, and the preparation of the enhancement-mode GaN PMOS device is completed.

[0081] The embodiment utilizes the selective oxidation of GaN and AlGaN, selectively oxidizes the p-type AlGaN layer to form an oxidized AlGaN layer, and then etches the oxidized AlGaN layer by wet etching. By combining oxidation and wet etching, the oxidized AlGaN layer is more easily etched by wet etching, while GaN is not easily oxidized and thus not easily etched, so that the etching is automatically terminated at the GaN interface. Not only the etching depth is ensured, but also over-etching is avoided, and the channel is protected from plasma etching damage, a better surface morphology is obtained, the influence of surface states on the channel mobility is reduced, and thus the overall performance of the device is improved.

[0082] Embodiment two

[0083] Based on the embodiment one, please refer to Figure 3 , Figure 3 A structure diagram of an enhancement-mode GaN PMOS device based on oxidation etching is provided in the embodiment of the application, and the GaN PMOS device is prepared by the preparation method of the embodiment one, and includes a substrate 1, a nucleation layer 2, a GaN buffer layer 3, an AlGaN back barrier layer 4, a GaN channel layer 5, a p-type AlGaN layer 6, and a p-type GaN cap layer 7, a dielectric layer 8, a source 9, a drain 10, and a gate 11.

[0084] Specifically, the substrate 1, the nucleation layer 2, the GaN buffer layer 3, the AlGaN back barrier layer 4, the GaN channel layer 5, the p-type AlGaN layer 6, and the p-type GaN cap layer 7 are sequentially stacked; the middle part of the p-type AlGaN layer 6 and the p-type GaN cap layer 7 forms the gate recess structure 11'; the source electrode 9 is located on the p-type GaN cap layer 7 on one side of the gate recess structure 11', and the drain electrode 10 is located on the p-type GaN cap layer 7 on the other side of the gate recess structure 11'; the dielectric layer 8 is located on the surfaces of the source electrode 9, the drain electrode 10, the p-type GaN cap layer 7, and the gate recess structure 11'; and the gate electrode 11 is located on the dielectric layer 8 and in the gate recess structure 11', forming a T-shaped gate structure.

[0085] The specific structural parameters of the GaN PMOS device can be found in Example One, and will not be repeated here.

[0086] Example Three

[0087] On the basis of Example One, the thickness of the GaN nucleation layer 2 on the sapphire substrate is 50 nm, the thickness of the GaN buffer layer 3 is 3 μm, the thickness of the AlGaN back barrier layer 4 is 10 nm, the GaN channel layer 5 is 3 nm, the p-type AlGaN layer 6 is 50 nm, the p-type GaN cap layer 7 is 2 nm, and the dielectric layer 8 is 10 nm of SiN x The preparation method of the enhanced GaN PMOS device is described by taking the GaN PMOS device as an example.

[0088] The preparation method comprises the steps of:

[0089] S1, sequentially growing the nucleation layer 2, the GaN buffer layer 3, the AlGaN back barrier layer 4, the GaN channel layer 5, the p-type AlGaN layer 6, and the p-type GaN cap layer 7 on the substrate 1.

[0090] S11, growing the nucleation layer 2 on the substrate 1, please refer to Figure 2a .

[0091] Firstly, the substrate 1 is cleaned. The sapphire substrate 1 is placed in hydrofluoric acid for ultrasonic cleaning for 5 min, then placed in an acetone solution for ultrasonic cleaning for 5 min, then placed in anhydrous ethanol solution for ultrasonic cleaning for 5 min, then placed in deionized water for ultrasonic cleaning for 5 min, and finally dried with nitrogen.

[0092] Then, the substrate 1 is heat treated. The cleaned sapphire substrate 1 is first placed in the MOCVD reaction chamber, the vacuum degree of the reaction chamber is reduced to less than 2×10 -2 Torr; then a mixed gas of hydrogen and ammonia is introduced into the reaction chamber, the substrate 1 is heated to a temperature of 1000℃ under the condition that the pressure of the MOCVD reaction chamber reaches 100 Torr, and maintained for 5 min, to complete the heat treatment of the sapphire substrate 1.

[0093] After that, the growth of GaN nucleation layer 2 is carried out. The heat-treated sapphire substrate is put into the MOCVD reaction chamber, the reaction chamber pressure is adjusted to 20 Torr, the temperature is 560 °C, and a 50 nm thick GaN nucleation layer 2 is grown on the substrate.

[0094] S12, growing GaN buffer layer 3 on nucleation layer 2, please refer to Figure 2b .

[0095] Specifically, a 3 μm thick GaN buffer layer 3 is grown on the GaN nucleation layer 2 using MOCVD process under the condition that the reaction chamber pressure is 40 Torr and the temperature is 1100 °C.

[0096] S13, growing AlGaN back barrier layer 4 on GaN buffer layer 3, please refer to Figure 2c .

[0097] Specifically, a 10 nm thick AlGaN back barrier layer 4 is grown on the GaN buffer layer 3 using MOCVD process under the condition that the reaction chamber pressure is 60 Torr and the temperature is 1000 °C.

[0098] S14, growing GaN channel layer 5 on AlGaN back barrier layer 4, please refer to Figure 2d .

[0099] Specifically, a 3 nm thick GaN channel layer 5 is grown on the AlGaN back barrier layer 4 using MOCVD process under the condition that the reaction chamber pressure is 40 Torr and the temperature is 1200 °C.

[0100] S15, growing p-type AlGaN layer 6 on GaN channel layer 5, please refer to Figure 2e .

[0101] Specifically, a 50 nm thick p-type AlGaN layer is grown on the GaN channel layer using MOCVD process under the condition that the reaction chamber pressure is 50 Torr and the temperature is 1100 °C.

[0102] S16, growing p-type GaN cap layer 7 on p-type AlGaN layer 6, please refer to Figure 2f .

[0103] Specifically, a 2 nm thick p-type GaN cap layer 7 is grown on the p-type AlGaN layer 6 using MOCVD process under the condition that the reaction chamber pressure is 40 Torr and the temperature is 1100 °C.

[0104] Next, the mesa isolation of the device is formed on the sample after the growth of the p-type GaN cap layer 7 using photolithography and etching process.

[0105] S2, etching the p-type GaN cap layer 7 of the gate region to expose the p-type AlGaN layer 6, please refer to Figure 2g .

[0106] Specifically, the p-type GaN cap layer 7 of the gate region is etched completely to expose the p-type AlGaN layer 6.

[0107] S3, selectively oxidizing the exposed p-type AlGaN layer 6 and p-type GaN cap layer 7, so that the p-type AlGaN layer 6 forms an oxidized AlGaN layer 6', please refer to Figure 2h .

[0108] Specifically, the etched sample is placed in an environment with a temperature of 650℃ and an oxygen flow rate of 4L / min for high-temperature oxidation for 50min, so that the p-type AlGaN layer 6 forms the oxidized AlGaN layer 6'.

[0109] S4, etching the oxidized AlGaN layer 6' with an etching solution to expose the GaN channel layer 5 to form a gate recess structure 11', please refer to Figure 2i .

[0110] Specifically, the high-temperature oxidized sample is placed in a 70℃ KOH solution for etching for 60min to etch away the oxidized AlGaN layer 6' to form the gate recess structure 11'.

[0111] S5, preparing a source electrode 9 on the p-type GaN cap layer 7 on one side of the gate recess structure 11' and a drain electrode 10 on the p-type GaN cap layer 7 on the other side, please refer to Figure 2j .

[0112] Specifically, the sample with the etched gate recess structure 11' is used to sputter Ni / Au in the source and drain electrode regions by using photolithography and magnetron sputtering process, and an ohmic contact electrode is formed by annealing at a high temperature of 550℃ to obtain the source electrode 9 and the drain electrode 10, wherein the source electrode 9 is located on the p-type GaN cap layer 7 on one side of the gate recess structure 11', and the drain electrode 10 is located on the p-type GaN cap layer 7 on the other side of the gate recess structure 11'.

[0113] S6, preparing a dielectric layer 8 on the surfaces of the source electrode 9, the drain electrode 10, the p-type GaN cap layer 7 and the gate recess structure 11', please refer to Figure 2k .

[0114] Specifically, a 10nm-thick SiN x dielectric layer 8 is deposited on the surfaces of the source electrode 9, the drain electrode 10, the p-type GaN cap layer 7 and the gate recess structure 11' by using PECVD process on the sample with the deposited ohmic electrode.

[0115] S7, preparing a gate electrode 11 on the dielectric layer 8 so that the gate electrode 11 is located in the gate recess structure 11', please refer to Figure 2l.

[0116] Specifically, the metal Ni / Au is sputtered in the gate region by using photolithography and magnetron sputtering process to form the gate 11; wherein the gate 11 is a T-shaped gate, the gate leg is located in the gate groove structure 11', and the gate cap is located on the gate leg and the dielectric layer 8.

[0117] Then, the SiN x The dielectric layer 8 is formed, and the fabrication of the enhanced GaN PMOS device is completed.

[0118] Example Four

[0119] On the basis of the example one, the enhanced GaN PMOS device with the AlN nucleation layer 2 of 100 nm in thickness, the GaN buffer layer 3 of 4 μm in thickness, the AlGaN back barrier layer 4 of 20 nm in thickness, the GaN channel layer 5 of 5 nm, the p-type AlGaN layer 6 of 60 nm, the p-type GaN cap layer 7 of 3 nm, and the dielectric layer 8 of 20 nm SiO2 on the silicon substrate is taken as an example to illustrate the preparation method thereof.

[0120] The preparation method comprises the following steps:

[0121] S1, sequentially growing the nucleation layer 2, the GaN buffer layer 3, the AlGaN back barrier layer 4, the GaN channel layer 5, the p-type AlGaN layer 6, and the p-type GaN cap layer 7 on the substrate 1.

[0122] S11, growing the nucleation layer 2 on the substrate 1, please refer to Figure 2a .

[0123] Firstly, the substrate 1 is cleaned. The silicon substrate 1 is put into hydrofluoric acid for ultrasonic cleaning for 5 min, then put into acetone solution for ultrasonic cleaning for 5 min, then use anhydrous ethanol solution for ultrasonic cleaning for 5 min, then use deionized water for ultrasonic cleaning for 5 min, and finally dry with nitrogen.

[0124] Then, the substrate 1 is heat treated. First, the cleaned silicon substrate 1 is placed in a metal organic chemical vapor deposition (MOCVD) reaction chamber, the vacuum degree of the reaction chamber is reduced to less than 2×10 -2 Torr; then the mixed gas of hydrogen and ammonia is introduced into the reaction chamber, the substrate is heated to a temperature of 1200℃ under the condition that the pressure of the MOCVD reaction chamber reaches 500 Torr, and the heat treatment of the silicon substrate 1 is completed.

[0125] After that, the growth of the AlN nucleation layer 2 is performed. The heat-treated silicon substrate 1 is put into the MOCVD reaction chamber, the pressure of the reaction chamber is adjusted to 40 Torr, and the temperature is 800℃, and the 100 nm thick AlN nucleation layer 2 is grown on the silicon substrate 1.

[0126] S12, growing GaN buffer layer 3 on nucleation layer 2, please see Figure 2b .

[0127] Specifically, 4 μm thick GaN buffer layer 3 is grown on AlN nucleation layer 2 using MOCVD process under the conditions of 60 Torr reaction chamber pressure and 1000 °C temperature.

[0128] S13, growing AlGaN back barrier layer 4 on GaN buffer layer 3, please see Figure 2c .

[0129] Specifically, 20 nm thick AlGaN back barrier layer 4 is grown on GaN buffer layer 3 using MOCVD process under the conditions of 40 Torr reaction chamber pressure and 1200 °C temperature.

[0130] S14, growing GaN channel layer 5 on AlGaN back barrier layer 4, please see Figure 2d .

[0131] Specifically, 5 nm thick GaN channel layer 5 is grown on AlGaN back barrier layer 4 using MOCVD process under the conditions of 50 Torr reaction chamber pressure and 1100 °C temperature.

[0132] S15, growing p-type AlGaN layer 6 on GaN channel layer 5, please see Figure 2e .

[0133] Specifically, 60 nm thick p-type AlGaN layer 6 is grown on GaN channel layer 5 using MOCVD process under the conditions of 60 Torr reaction chamber pressure and 1200 °C temperature.

[0134] S16, growing p-type GaN cap layer 7 on p-type AlGaN layer 6, please see Figure 2f .

[0135] Specifically, 3 nm thick p-type GaN cap layer 7 is grown on p-type AlGaN layer 6 using MOCVD process under the conditions of 50 Torr reaction chamber pressure and 1200 °C temperature.

[0136] Next, mesa isolation of the device is formed on the sample after growing p-type GaN cap layer 7 using photolithography and etching process.

[0137] S2, etching away p-type GaN cap layer 7 in the gate region to expose p-type AlGaN layer 6, please see Figure 2g .

[0138] Specifically, p-type GaN cap layer 7 in the gate region is completely etched away, and p-type AlGaN layer 6 is exposed.

[0139] S3. Selectively oxidize the exposed p-type AlGaN layer 6 and p-type GaN cap layer 7 to form an oxidized AlGaN layer 6'. Please refer to [link to relevant documentation]. Figure 2h .

[0140] Specifically, the etched sample was placed in an environment with a temperature of 600℃ and an oxygen flow rate of 3L / min for high-temperature oxidation for 70 minutes, so that the p-type AlGaN layer 6 was formed into an oxidized AlGaN layer 6'.

[0141] S4. The AlGaN layer 6' is etched using a wet etching solution to expose the GaN channel layer 5, forming the gate groove structure 11'. Please refer to [link to relevant documentation]. Figure 2i .

[0142] Specifically, the high-temperature oxidized sample was placed in an 80°C KOH solution for 50 minutes to etch away the oxidized AlGaN layer 6', forming a gate groove structure 11'.

[0143] S5. A source electrode 9 is fabricated on the p-type GaN cap layer 7 on one side of the gate groove structure 11', and a drain electrode 10 is fabricated on the p-type GaN cap layer 7 on the other side. (See [link to relevant documentation]). Figure 2j .

[0144] Specifically, Ni / Au was sputtered in the source and drain regions of the sample with the etched gate groove structure 11' using photolithography and magnetron sputtering, and then annealed at a high temperature of 550°C to form ohmic contact electrodes, thus obtaining source 9 and drain 10. The source 9 is located on the p-type GaN cap layer 7 on one side of the gate groove structure 11', and the drain 10 is located on the p-type GaN cap layer 7 on the other side of the gate groove structure 11'.

[0145] S6. A dielectric layer 8 is fabricated on the surface of the source 9, drain 10, p-type GaN cap layer 7, and gate groove structure 11'. Please refer to [link to documentation]. Figure 2k .

[0146] Specifically, a 20 nm thick SiO2 dielectric layer 8 was deposited on the surface of the source electrode 9, drain electrode 10, p-type GaN cap layer 7 and gate groove structure 11' using PECVD process on the sample with deposited ohmic electrodes.

[0147] S7. Fold a gate 11 on the dielectric layer 8, such that the gate 11 is located in the gate recess structure 11'. Please refer to [link to relevant documentation]. Figure 2l .

[0148] Specifically, metal Ni / Pt / Au is sputtered in the gate region using photolithography and magnetron sputtering processes to form gate 11; wherein gate 11 is a T-shaped gate, its gate foot is located in the gate groove structure 11', and the gate cap is located on the gate foot and on the dielectric layer 8.

[0149] Afterwards, the SiO2 dielectric layer 8 on the source 9 and the drain 10 is etched away by photoetching, and the fabrication of the enhancement-mode GaN PMOS device is completed.

[0150] Example Five

[0151] On the basis of Example One, this example describes the preparation method of an enhancement-mode GaN PMOS device with a GaN nucleation layer thickness of 30 nm, a GaN buffer layer thickness of 2 μm, an AlGaN back barrier layer thickness of 30 nm, a GaN channel layer of 4 nm, a p-type AlGaN layer of 70 nm, a p-type GaN cap layer of 1 nm, and a dielectric layer of 30 nm Al2O3 on a GaN substrate.

[0152] The preparation method comprises the following steps:

[0153] S1, sequentially growing a nucleation layer 2, a GaN buffer layer 3, an AlGaN back barrier layer 4, a GaN channel layer 5, a p-type AlGaN layer 6, and a p-type GaN cap layer 7 on a substrate 1.

[0154] S11, growing a nucleation layer 2 on a substrate 1, please refer to Figure 2a .

[0155] First, the substrate 1 is cleaned. The GaN substrate is placed in hydrofluoric acid for ultrasonic cleaning for 5 min, then placed in an acetone solution for ultrasonic cleaning for 5 min, then placed in anhydrous ethanol solution for ultrasonic cleaning for 5 min, then placed in deionized water for ultrasonic cleaning for 5 min, and finally dried with nitrogen.

[0156] Then, the substrate 1 is heat treated. First, the cleaned GaN substrate 1 is placed in a metal organic chemical vapor deposition (MOCVD) reaction chamber, the vacuum degree of the reaction chamber is reduced to less than 2 x 10 -2 Torr; then a mixed gas of hydrogen and ammonia is introduced into the reaction chamber, the substrate is heated to a temperature of 900°C under the condition that the pressure of the MOCVD reaction chamber reaches 760 Torr, and the heat treatment of the GaN substrate 1 is completed.

[0157] Afterwards, the GaN nucleation layer 2 is grown. The heat-treated GaN substrate 1 is placed in the MOCVD reaction chamber, the pressure of the reaction chamber is adjusted to 60 Torr, and the temperature is adjusted to 520°C, and a 30 nm thick GaN nucleation layer 2 is grown on the substrate 1.

[0158] S12, growing a GaN buffer layer 3 on the nucleation layer 2, please refer to Figure 2b .

[0159] Specifically, the GaN buffer layer 3 is grown on the GaN nucleation layer 2 by MOCVD process under the conditions of a reaction chamber pressure of 20 Torr and a temperature of 1100°C.

[0160] S13, growing the AlGaN back barrier layer 4 on the GaN buffer layer 3, please refer to Figure 2c .

[0161] Specifically, the AlGaN back barrier layer 4 is grown on the GaN buffer layer 3 by MOCVD process under the conditions of a reaction chamber pressure of 20 Torr and a temperature of 1100°C.

[0162] S14, growing the GaN channel layer 5 on the AlGaN back barrier layer 4, please refer to Figure 2d .

[0163] Specifically, the GaN channel layer 5 is grown on the AlGaN back barrier layer 4 by MOCVD process under the conditions of a reaction chamber pressure of 60 Torr and a temperature of 1000°C.

[0164] S15, growing the p-type AlGaN layer 6 on the GaN channel layer 5, please refer to Figure 2e .

[0165] Specifically, the p-type AlGaN layer 6 is grown on the GaN channel layer 5 by MOCVD process under the conditions of a reaction chamber pressure of 30 Torr and a temperature of 1000°C.

[0166] S16, growing the p-type GaN cap layer 7 on the p-type AlGaN layer 6, please refer to Figure 2f .

[0167] Specifically, the p-type GaN cap layer 7 is grown on the p-type AlGaN layer 6 by MOCVD process under the conditions of a reaction chamber pressure of 20 Torr and a temperature of 1000°C.

[0168] Next, the mesa isolation of the device is formed on the sample after the growth of the p-type GaN cap layer 7 by using photolithography and etching process.

[0169] S2, etching off the p-type GaN cap layer 7 in the gate region to expose the p-type AlGaN layer 6, please refer to Figure 2g .

[0170] Specifically, the p-type GaN cap layer 7 in the gate region is etched off completely and the p-type AlGaN layer 6 is exposed.

[0171] S3, selectively oxidizing the exposed p-type AlGaN layer 6 and p-type GaN cap layer 7 so that the p-type AlGaN layer 6 forms the oxidized AlGaN layer 6', please refer to Figure 2h.

[0172] Specifically, the etched sample is put into an environment with a temperature of 700℃ and an oxygen flow of 5L / min for high-temperature oxidation for 60min, so that the p-type AlGaN layer 6 forms an oxidized AlGaN layer 6'.

[0173] S4, the oxidized AlGaN layer 6' is etched by a wet etching solution to expose the GaN channel layer 5, forming a gate recess structure 11', see Figure 2i .

[0174] Specifically, the high-temperature oxidized sample is etched in a 75℃ KOH solution for 40min, and the oxidized AlGaN layer 6' is etched to form the gate recess structure 11'.

[0175] S5, the source 9 is prepared on the p-type GaN cap layer 7 on one side of the gate recess structure 11', and the drain 10 is prepared on the p-type GaN cap layer 7 on the other side, see Figure 2j .

[0176] Specifically, the sample with the etched gate recess structure 11' is sputtered with Ni / Au in the source and drain regions by photolithography and magnetron sputtering process, and is annealed at a high temperature of 550℃ to form an ohmic contact electrode, thereby obtaining the source 9 and the drain 10, wherein the source 9 is located on the p-type GaN cap layer 7 on one side of the gate recess structure 11', and the drain 10 is located on the p-type GaN cap layer 7 on the other side of the gate recess structure 11'.

[0177] S6, the dielectric layer 8 is prepared on the surfaces of the source 9, the drain 10, the p-type GaN cap layer 7 and the gate recess structure 11', see Figure 2k .

[0178] Specifically, the sample with the ohmic electrode is deposited with a 30nm-thick Al2O3 dielectric layer 8 on the surfaces of the source 9, the drain 10, the p-type GaN cap layer 7 and the gate recess structure 11' by PECVD process.

[0179] S7, the gate 11 is prepared on the dielectric layer 8, so that the gate 11 is located in the gate recess structure 11', see Figure 2l .

[0180] Specifically, the gate 11 is formed by sputtering metal Ni / Au in the gate region by photolithography and magnetron sputtering process; wherein the gate 11 is a T-shaped gate, the gate leg of which is located in the gate recess structure 11', and the gate cap is located on the gate leg and the dielectric layer 8.

[0181] Then, the Al2O3 dielectric layer 8 on the source 9 and the drain 10 is etched by opening holes by photolithography, and the preparation of the enhancement-mode GaN PMOS device is completed.

[0182] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be deemed as falling within the protection scope of the present application.

Claims

1. A method for fabricating an enhanced GaN PMOS device based on oxidic etching, characterized in that, Including the following steps: S1. A core layer, a GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, a p-type AlGaN layer, and a p-type GaN cap layer are sequentially grown on a substrate; the p-type AlGaN layer is made of magnesium-doped AlGaN, and the p-type GaN cap layer is made of magnesium-doped GaN; the thickness of the GaN channel layer is 3-5 nm, and the thickness of the p-type GaN cap layer is 1-3 nm. S2. Etch away the p-type GaN cap layer in the gate region to expose the p-type AlGaN layer; S3. Under the conditions of a temperature of 600-700℃ and an oxygen flow rate of 3-5L / min, the exposed p-type AlGaN layer and the p-type GaN cap layer are selectively oxidized for 50-70min, so that the p-type AlGaN layer forms an oxidized AlGaN layer. S4. The AlGaN oxide layer is etched using a wet etching solution to expose the GaN channel layer, forming a gate trench structure; the etching solution includes one or more of KOH solution, NaOH solution, and TMAH solution. S5. A source electrode is fabricated on the p-type GaN cap layer on one side of the gate groove structure, and a drain electrode is fabricated on the p-type GaN cap layer on the other side. S6. A dielectric layer is prepared on the surface of the source, the drain, the p-type GaN cap layer and the gate groove structure; S7. A gate is fabricated on the dielectric layer such that the gate is located in the gate recess structure.

2. The method of fabricating an enhanced GaN PMOS device based on oxidic corrosion according to claim 1, wherein The substrate material includes one or more of sapphire, silicon carbide, silicon, and gallium nitride.

3. The method of fabricating an enhanced GaN PMOS device based on oxidic corrosion according to claim 1, wherein The nucleation layer, the GaN buffer layer, the AlGaN back barrier layer, the GaN channel layer, the p-type AlGaN layer, and the p-type GaN cap layer are sequentially grown on the substrate using a metal-organic chemical vapor deposition process.

4. The method of fabricating an enhanced GaN PMOS device based on oxidic corrosion according to claim 1, wherein The material of the nucleation layer includes one or more of AlN and GaN.

5. The method of fabricating an enhanced GaN PMOS device based on oxidic corrosion according to claim 1, wherein The thickness of the nucleation layer is 10-100 nm, and the thickness of the GaN buffer layer is 2-4 μm; The thickness of the AlGaN back barrier layer is 10-30 nm; the thickness of the p-type AlGaN layer is 50-70 nm.

6. The method of fabricating an oxidatively etched enhanced GaN PMOS device according to claim 1, wherein Step S4 includes: The sample was placed in a KOH solution at a temperature of 70-80℃ to etch the AlGaN oxide layer for 40-60 minutes to expose the GaN channel layer.

7. The method of fabricating an oxidatively etched enhanced GaN PMOS device according to claim 1, wherein The material of the medium layer includes one or more of SiN x , SiO2, Al2O3, HfO2, and has a thickness of 10-30 nm.

8. An enhanced GaN PMOS device based on oxidic corrosion, characterized in that The material is prepared by the preparation method according to any one of claims 1 to 7, comprising a substrate, a nucleation layer, a GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, a p-type AlGaN layer, a p-type GaN cap layer, a dielectric layer, a source, a drain, and a gate, wherein the p-type AlGaN layer is made of magnesium-doped AlGaN, and the p-type GaN cap layer is made of magnesium-doped GaN; the thickness of the GaN channel layer is 3-5 nm, and the thickness of the p-type GaN cap layer is 1-3 nm; The substrate, the nucleation layer, the GaN buffer layer, the AlGaN back barrier layer, the GaN channel layer, the p-type AlGaN layer and the p-type GaN cap layer are stacked in sequence; The p-type AlGaN layer and the p-type GaN cap layer form a gate recess structure in the middle part; The source electrode is located on the p-type GaN cap layer on one side of the gate recess structure, and the drain electrode is located on the p-type GaN cap layer on the other side of the gate recess structure; The dielectric layer is located on the surface of the source electrode, the drain electrode, the p-type GaN cap layer and the gate recess structure; The gate electrode is located on the dielectric layer and in the gate recess structure.

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