Semiconductor silicon wafer with SOI structure and preparation method thereof

Abstract

The present invention provides a semiconductor silicon wafer of SOI structure and a preparation method thereof, which belongs to the field of semiconductor manufacturing, and specifically includes step 1, placing the semiconductor silicon wafer in a first vertical furnace tube for long-term heat treatment; step 2, placing the semiconductor silicon wafer after long-term heat treatment in a second vertical furnace tube for oxidation thinning treatment; step 3, performing rapid thermal annealing treatment on the semiconductor silicon wafer after oxidation thinning, wherein, in the long-term heat treatment, the semiconductor silicon wafer is first placed in a pure argon atmosphere for protection, and then heated to a target temperature in a mixed atmosphere of 1-n% argon + n% hydrogen before an annealing stage is performed, and in the annealing stage, the atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon, and n is a value not greater than 10. Through the processing scheme of the present application, the surface roughness of the semiconductor silicon wafer is less than 5 angstroms, and there is no slip line on the edge.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor silicon wafer with an SOI structure and a preparation method thereof. Background Art

[0002] As the post-Moore era continues to advance, people have put forward more stringent requirements on semiconductor silicon wafers, especially silicon wafers in terms of structure, thickness uniformity and surface flatness. At present, silicon structure silicon wafer silicon on insulator SOI (Silicon on Insulator) has been widely used in microelectronics, optics and optoelectronics, and correspondingly, more challenges have been added in terms of materials.

[0003] Now SOI devices require the top silicon to be thinner and thinner, but the traditional mechanical chemical polishing method has the disadvantages of uneven thickness, excessive roughness, and easy introduction of additional surface defects. In order to replace the traditional mechanical chemical polishing, rapid thermal annealing and other methods are often used to process silicon wafers. However, by scanning the surface of the silicon wafer with AFM (Atomic Force Microscope) to obtain a scan image and performing a fast Fourier transform on it, the power spectral density (PSD: power Spectral Density) can be obtained, which shows that the low-frequency intensity of the silicon wafer is too large, that is, the long-range fluctuation of the surface is too large, which is not conducive to the subsequent processing of the silicon wafer. If the silicon wafer is processed by long-term heat treatment, there will be residual thermal stress in the top silicon of SOI, which is easy to cause slip lines in the subsequent heat treatment, which is also not conducive to the subsequent processing of the silicon wafer. Summary of the invention

[0004] Therefore, in order to overcome the above-mentioned shortcomings of the prior art, the present invention provides a semiconductor silicon wafer with a SOI structure and a preparation method thereof, which can make the surface roughness of the semiconductor silicon wafer less than 5 angstroms and have no slip line on the edge.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a method for preparing a semiconductor silicon wafer with an SOI structure, comprising: step one, placing a semiconductor silicon wafer in a first vertical furnace tube for long-term heat treatment; step two, placing the semiconductor silicon wafer after the long-term heat treatment in a second vertical furnace tube for oxidation thinning treatment; step three, performing rapid thermal annealing treatment on the semiconductor silicon wafer after oxidation thinning, wherein, during the long-term heat treatment, the semiconductor silicon wafer is first placed in a pure argon atmosphere for protection, and then heated to a target temperature in a mixed atmosphere of 1-n% argon + n% hydrogen and then an annealing stage is performed, and in the annealing stage, the atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon, and n is a value not greater than 10.

[0006] In one embodiment, the first vertical furnace tube and the second vertical furnace tube are the same vertical furnace tube.

[0007] In one embodiment, in the step one, the long-term heat treatment includes: loading the semiconductor silicon wafer into the first vertical furnace tube, the loading temperature range is 500℃-800℃, the atmosphere is argon, and it is maintained for 1min-10min; switching the atmosphere to a 1-n% argon + n% hydrogen mixed atmosphere and starting to heat up, and the heating rate range is 0.5-20℃ / min; after heating to the target temperature, starting the annealing stage, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere or pure argon, the target temperature range is 1050℃-1250℃, and the annealing time range is 1min-120min.

[0008] In one embodiment, in the step one, the long-term heat treatment includes: loading the semiconductor silicon wafer into the first vertical furnace tube, the loading temperature is 650°C, the atmosphere is argon, and maintained for 5 minutes; switching the atmosphere to a 1-n% argon + n% hydrogen mixed atmosphere and starting to heat up, the heating rate range is 0.5-20°C / min, n is less than 3; heating to the target temperature to start the annealing stage, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere or pure argon, the target temperature range is 1100°C-1200°C, and the annealing time range is 30min-60min.

[0009] In one embodiment, in the step 2, the oxidation thinning treatment includes: oxidizing the semiconductor silicon wafer after long-term heat treatment according to a preset oxidation thinning thickness, the oxidation temperature range is 800°C-1000°C, the time is determined according to the preset oxidation thinning thickness, and the oxidation form is dry oxygen oxidation or water vapor oxidation or wet oxygen oxidation; removing the surface oxide layer of the oxidized semiconductor silicon wafer in an HF solution, and the HF concentration is less than 20%.

[0010] In one of the embodiments, in the step three, the rapid thermal annealing treatment includes: treating the semiconductor silicon wafer after oxidation thinning treatment at normal pressure or low pressure, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere, and the heating rate range is 30-100°C / s; heating to the target temperature to start the annealing stage, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere or pure argon, the target temperature range is 1100°C-1300°C, the cooling rate range is 30-100°C / s, and the annealing time range is 1s-120s.

[0011] In one embodiment, when the gas pressure of the rapid thermal annealing process is low pressure, the pressure range is 1 mbar-1010 mbar.

[0012] In one of the embodiments, the method further includes step four, performing a second oxidation thinning treatment on the semiconductor silicon wafer after the rapid thermal annealing treatment.

[0013] In one embodiment, the step four includes the following processing: after the rapid thermal annealing treatment stage is completed, the silicon wafer after the rapid thermal treatment is loaded into the second vertical furnace tube, and oxidized according to the target thickness, the oxidation temperature range is 800°C-1000°C, the time is determined according to the target thickness, and the oxidation form is dry oxygen oxidation or water vapor oxidation or wet oxygen oxidation; the surface oxide layer of the oxidized semiconductor silicon wafer is removed in an HF solution, and the HF concentration is less than 20%.

[0014] The present invention also provides a semiconductor silicon wafer with an SOI structure, wherein the surface roughness of the top silicon layer is less than 5 angstroms and the thickness uniformity is within ±1%.

[0015] In one of the embodiments, the semiconductor silicon wafer is prepared by the above method.

[0016] Compared with the prior art, the advantages of the present invention are: the long-range fluctuation (low frequency) of the silicon wafer is flattened by long-term thermal annealing; and after the long-term thermal annealing, the thermal stress remaining after the long-term thermal annealing process is released by oxidation thinning treatment to avoid the occurrence of slip lines in subsequent processing; the short-range fluctuation (high frequency) of the silicon wafer is flattened by rapid thermal annealing, so that the prepared silicon wafer is flattened both at high frequency and low frequency, and without using traditional mechanical chemical polishing, the semiconductor silicon wafer is optimized, the surface roughness of the silicon wafer is reduced, and it is ensured that there is no slip line in the subsequent manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a non-contact scan of an embodiment of the present invention at different processing stages of the method;

[0019] Figure 2 1 is a PSD curve diagram of Example 1 and Comparative Example 2 at different stages of the present invention;

[0020] Figure 3 This is a surface grayscale map (HazeMap) of the comparative example 1 of the present invention after long-term thermal annealing + rapid thermal annealing;

[0021] Figure 4 This is a surface grayscale image after long-term thermal annealing + oxidation thinning + rapid thermal annealing in Example 1 of the embodiment of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0023] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0024] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0026] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0027] The present application provides a method for preparing a semiconductor silicon wafer with an SOI structure, which is particularly suitable for preparing silicon on insulator, and includes the following steps:

[0028] Step 1: placing the semiconductor silicon wafer in a first vertical furnace tube for long-term heat treatment.

[0029] To use Smart-cut TM Taking the wafer with SOI structure obtained by the process as an example, its surface roughness after peeling is >10 angstroms. During the long-term heat treatment, the semiconductor silicon wafer is first placed in a pure argon atmosphere for protection, and then heated to the target temperature in a mixed atmosphere of 1-n% argon + n% hydrogen before the annealing stage. In the annealing stage, the atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon, where n is a value not greater than 10. The mixed atmosphere of 1-n% argon + n% hydrogen can not only protect the semiconductor silicon wafer from oxidation, but also reduce the silicon oxide on the silicon wafer in the previous process to elemental silicon, further improving the quality of the semiconductor silicon wafer.

[0030] Step 2: performing oxidation thinning treatment on the semiconductor silicon wafer in the second vertical furnace tube.

[0031] The semiconductor silicon wafer can be oxidized in a dry oxygen or wet oxygen atmosphere or a combination of dry oxygen and wet oxygen according to a preset oxidation thinning thickness. The oxidation temperature can be any temperature that can achieve oxidation of the silicon wafer, and the time is determined according to the preset oxidation thinning thickness.

[0032] Step three, performing rapid thermal annealing on the semiconductor silicon wafer after oxidation thinning.

[0033] The semiconductor silicon wafer can be subjected to rapid thermal annealing at normal pressure or low pressure. The atmosphere of the rapid thermal annealing can be consistent or inconsistent with that of the long thermal annealing, but the heating rate and cooling rate are much higher than those of the long thermal annealing. The heating rate and cooling rate of the rapid thermal annealing can exceed those of the long thermal annealing by dozens or even thousands of times. The surface roughness of the semiconductor silicon wafer obtained by the above steps is less than 5 angstroms.

[0034] The above-mentioned silicon wafer preparation method flattens the long-range fluctuations (low frequency) of the silicon wafer by long-term thermal annealing; and after the long-term thermal annealing, it releases the thermal stress remaining after the long-term thermal annealing process by oxidation thinning treatment to avoid the occurrence of slip lines in subsequent processing; the short-range fluctuations (high frequency) of the silicon wafer are flattened by rapid thermal annealing, so that the prepared silicon wafer is flattened both at high frequency and low frequency, and without using traditional mechanical chemical polishing, the semiconductor silicon wafer is optimized to reduce the surface roughness of the silicon wafer and ensure that there are no slip lines in the subsequent manufacturing process.

[0035] In one embodiment, the first vertical furnace tube and the second vertical furnace tube are the same vertical furnace tube.

[0036] When step one and step two are performed successively in the same vertical furnace tube, that is, the long thermal annealing stage is integrated with the thinning process, that is, the atmosphere environment can be set to pure Ar in the annealing stage, and the atmosphere environment is set to an oxidizing atmosphere after the vertical furnace tube is cooled to the oxidation temperature. The time is determined according to the preset oxidation thinning thickness, and the oxidizing atmosphere can be dry oxygen or wet oxygen or a combination of dry oxygen and wet oxygen.

[0037] The specific execution steps can be:

[0038] After the thermal annealing stage, the atmosphere is set to pure argon, and the temperature is lowered to the oxidation temperature, and the cooling rate range is 0.5-20°C / min; directly lower the temperature to the oxidation temperature, and the oxidation temperature range is 800°C-1000°C;

[0039] The silicon wafer is oxidized in a dry oxygen or wet oxygen atmosphere or a combination of dry oxygen and wet oxygen according to a preset oxidation thinning thickness, and the time is determined according to the preset oxidation thinning thickness.

[0040] In one embodiment, in step 1, the long-term heat treatment comprises the following steps:

[0041] Loading the semiconductor silicon wafer into the first vertical furnace tube, the loading temperature range is 500°C-800°C, the atmosphere is argon, and the temperature is maintained for 1 min-10 min;

[0042] The atmosphere was switched to a 1-n% argon + n% hydrogen mixed atmosphere and the temperature was raised at a rate of 0.5-20°C / min.

[0043] After the temperature is raised to the target temperature, the annealing stage begins. The atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon. The target temperature range is 1050° C.-1250° C., and the annealing time range is 1 min-120 min.

[0044] In one embodiment, in step 1, the long-term heat treatment comprises the following steps:

[0045] The semiconductor silicon wafer is loaded into the first vertical furnace tube at a loading temperature of 650° C. and an argon atmosphere for 5 minutes;

[0046] The atmosphere is switched to a 1-n% Ar + n% H2 mixed atmosphere and the temperature is raised at a rate of 0.5-20°C / min, where n is less than 3;

[0047] The temperature is raised to the target temperature to start the annealing stage. The atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon. The target temperature range is 1100°C-1200°C, and the annealing time range is 30min-60min.

[0048] In one embodiment, in step 2, the oxidation thinning treatment includes: oxidizing the semiconductor silicon wafer according to a preset oxidation thinning thickness, the oxidation temperature range is 800°C-1000°C, the time is determined according to the preset oxidation thinning thickness, and the oxidation form is dry oxygen oxidation or water vapor oxidation or wet oxygen oxidation; removing the surface oxide layer of the semiconductor silicon wafer in an HF solution, and the HF concentration is less than 20%.

[0049] Dry oxygen oxidation uses dry pure oxygen as the oxidation atmosphere; water vapor oxidation uses high-purity water vapor as the oxidation atmosphere; wet oxygen oxidation is essentially a mixture of dry oxygen oxidation and water vapor oxidation, where the ratio of oxygen to water vapor ranges from (1 to 3). The preset oxidation thinning thickness value can be a value greater than 300 angstroms.

[0050] In one embodiment, the oxidation temperature is preferably 900° C.-950° C. After the oxidation thinning is completed, the atmosphere is switched to pure argon and the temperature is slowly lowered to 500° C.-800° C., preferably 650° C., with a cooling rate ranging from 0.5° C. / min to 20° C. / min. After thinning, the surface oxide layer can be removed in an HF solution, and the HF concentration is less than 20%, preferably 5%.

[0051] In one of the embodiments, in step three, the rapid thermal annealing treatment includes: treating the semiconductor silicon wafer at normal pressure or low pressure, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere, and the heating rate range is 30-100°C / s; heating to the target temperature to start the annealing stage, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere or pure argon, the target temperature range is 1100°C-1300°C, the cooling rate range is 30-100°C / s, and the annealing time range is 1s-120s.

[0052] In one of the embodiments, in step three, the rapid thermal annealing treatment includes: treating the semiconductor silicon wafer at normal pressure or low pressure, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere, and the heating rate range is 50-70°C / s; heating to the target temperature to start the annealing stage, the atmosphere is a 1-n% argon + n% hydrogen mixed atmosphere or pure argon, the target temperature range is 1150°C-1250°C, the cooling rate range is 50-70°C / s, and the annealing time range is 10s-60s.

[0053] In one embodiment, when the gas pressure of the rapid thermal annealing process is low pressure, the pressure ranges from 1 mbar to 1010 mbar.

[0054] In one embodiment, the method further includes step 4, performing a second oxidation thinning process on the semiconductor silicon wafer that has been subjected to the rapid thermal annealing process.

[0055] The purpose of the second oxidation thinning process in step 4 is to control the thickness of the top silicon layer on the semiconductor silicon wafer to reach the final target thickness requirement value.

[0056] In one embodiment, step four includes the following processing: after the rapid thermal annealing treatment stage is completed, the semiconductor silicon wafer is loaded into a second vertical furnace tube to start an oxidation thinning process, oxidation is performed according to the target thickness, the oxidation temperature range is 800°C-1000°C, the time is determined according to the target thickness, and the oxidation form is dry oxygen oxidation or water vapor oxidation or wet oxygen oxidation; the surface oxide layer of the semiconductor silicon wafer is removed in an HF solution, and the HF concentration is less than 20%.

[0057] The semiconductor silicon wafer of the SOI structure produced in the above embodiment has a top silicon surface roughness of less than 5 angstroms and a thickness uniformity within ±1%, thereby avoiding the occurrence of obvious slip lines on the edge of the silicon wafer surface in subsequent processes.

[0058] Embodiment 1

[0059] Three pieces are cut by the same Smart-cut TM The non-contact scanning image of the 300 mm SOI wafer obtained by the process (Example 1, Comparative Example 1, Comparative Example 2) is first obtained. Figure 1 a) is a surface AFM 10μm×10μm non-contact scanning image, from which it can be seen that the surface roughness of all silicon wafers is about 25.7 angstroms.

[0060] Two SOI wafers of Example 1 and Comparative Example 1 were simultaneously loaded into a vertical furnace for long-term thermal annealing. During the long-term thermal annealing process, the initial loading temperature was 650°C, the atmosphere was pure Ar, and it was maintained for 5 minutes; then the atmosphere was switched to 95% Ar + 5% H2, and the heating rate was 5°C / min; the temperature was raised to the target temperature to start the annealing phase, and the atmosphere was switched to pure argon atmosphere at a temperature of 1100°C; the annealing time was 40 minutes; after the annealing phase, the atmosphere was set to pure Ar, and the temperature was cooled to 650°C, and the cooling rate was 1-10°C / min.

[0061] Figure 1 b) The figure is a non-contact AFM 10μm×10μm scan of the surface of Example 1 and Comparative Example 1 after long-term annealing. From the figure, it can be seen that the surface roughness of the silicon wafer after long-term heat treatment is 4.8 angstroms.

[0062] After the long-term thermal annealing, wafer Example 1 is subjected to oxidation thinning treatment in a wet oxygen atmosphere according to the target thickness, the oxidation temperature is 950° C., and the oxidation thinning thickness is 1000 angstroms.

[0063] After thinning, the surface oxide layer is removed in an HF solution with an HF concentration of 5%.

[0064] Figure 1 c) The figure shows an AFM 10μm×10μm non-contact scan of the SOI wafer surface after thinning in Example 1. The surface roughness of the silicon wafer after oxidation thinning is 5.6 angstroms.

[0065] Then, Example 1, Comparative Example 1 and Comparative Example 2 were subjected to rapid thermal annealing treatment, and the temperature of the 95% Ar+5% H2 mixed atmosphere was increased; during the annealing process, the atmosphere was switched to pure argon, the annealing temperature was 1200° C., and the annealing time was 30 s.

[0066] Figure 1 d) The figure is a 10 μm×10 μm non-contact scanning image of the surface of the SOI wafer after rapid thermal annealing in Example 1, and the surface roughness is 4.0 angstroms.

[0067] Figure 1 e) The figure shows an AFM 10μm×10μm non-contact scanning image of the surface of the SOI wafer after rapid thermal annealing in comparative example 2, and its surface roughness is 4.0 angstroms.

[0068] Figure 2 The PSD curves of Example 1 and Comparative Example 2 at different stages are shown in Figure 1. The before curve represents the initial PSD curves of the three samples; the comparative example 2 is the PSD curve obtained by rapid thermal processing test on silicon wafers. Figure 2 It can be clearly seen that the overall PSD intensity of Example 1 is lower, especially the effect in the low-frequency area is more obvious. The PSD in the low-frequency area is even one order of magnitude lower than that of Control Example 2, and the sample surface is flatter. Therefore, the overall product performance of Example 1 is better than that of Control Example 2.

[0069] Figure 3 This is the surface grayscale image of the control example 1 after long-term thermal annealing + rapid thermal annealing, showing that an obvious slip line appears on its edge;

[0070] Figure 4 This is a grayscale image of the surface of Example 1 after long-term thermal annealing + oxidation thinning + rapid thermal annealing, showing that there is no slipline at its edge.

[0071] Will Figure 3 and Figure 4 By comparison, it can be determined that oxidation thinning can be used after long-term thermal annealing to release the residual thermal stress after the long-term thermal annealing process and avoid the occurrence of slip lines in subsequent treatments.

[0072] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor silicon wafer with a SOI structure, characterized in that: include: Step 1, placing the semiconductor silicon wafer in a first vertical furnace tube for long-term heat treatment; Step 2, placing the semiconductor silicon wafer after long-term heat treatment into a second vertical furnace tube for oxidation thinning treatment; Step 3: Performing a rapid thermal annealing treatment on the semiconductor silicon wafer after oxidation thinning. In the long-term heat treatment, the semiconductor silicon wafer is first placed in a pure argon atmosphere for protection, and then the annealing stage is performed after the temperature is raised to the target temperature in a mixed atmosphere of 1-n% argon + n% hydrogen. In the annealing stage, the atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon, where n is a value not greater than 10. In the step 1, the long-term heat treatment comprises: Loading the semiconductor silicon wafer into the first vertical furnace tube, with the loading temperature ranging from 500° C. to 800° C. and the atmosphere being argon, and maintaining for 1 min to 10 min; Switch the atmosphere to a 1-n% argon + n% hydrogen mixed atmosphere and start heating at a rate of 0.5-20 °C / min; After heating to the target temperature, the annealing stage begins. The atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon. The target temperature range is 1050℃-1250℃, and the annealing time range is 1 min-120 min. In the step three, the rapid thermal annealing process includes: Treating the semiconductor silicon wafer after oxidation thinning at normal pressure or low pressure, in an atmosphere of 1-m% argon + m% hydrogen mixed atmosphere, m is less than 3, and a heating rate range is 30-100 °C / s; The annealing stage begins when the temperature is raised to the target temperature. The atmosphere is maintained as a mixed atmosphere of 1-m% argon + m% hydrogen in the heating stage or switched to pure argon. The target temperature range is 1100 ℃-1300 ℃, the cooling rate range is 30-100 ℃ / s, and the annealing time range is 1 s-120 s.

2. The method for preparing a semiconductor silicon wafer according to claim 1, characterized in that: The first vertical furnace tube and the second vertical furnace tube are the same vertical furnace tube.

3. The method for preparing a semiconductor silicon wafer according to claim 1, characterized in that: In the step 1, the long-term heat treatment comprises: Loading the semiconductor silicon wafer into the first vertical furnace tube at a loading temperature of 650° C. in an argon atmosphere for 5 minutes; Switch the atmosphere to a 1-n% argon + n% hydrogen mixed atmosphere and start heating at a heating rate of 0.5-20 °C / min, with n less than 3; The temperature is raised to the target temperature to start the annealing stage. The atmosphere is a mixed atmosphere of 1-n% argon + n% hydrogen or pure argon. The target temperature range is 1100℃-1200℃, and the annealing time range is 30 min-60 min.

4. The method for preparing a semiconductor silicon wafer according to claim 1, characterized in that: In the step 2, the oxidation thinning process includes: The semiconductor silicon wafer after long-term heat treatment is oxidized according to a preset oxidation thinning thickness, the oxidation temperature range is 800° C.-1000° C., the time is determined according to the preset oxidation thinning thickness, and the oxidation form is dry oxygen oxidation, water vapor oxidation or wet oxygen oxidation; The surface oxide layer of the oxidized semiconductor silicon wafer is removed in an HF solution, wherein the HF concentration is less than 20%.

5. The method for preparing a semiconductor silicon wafer according to claim 1, characterized in that: When the gas pressure of the rapid thermal annealing process is low pressure, the pressure range is 1 mbar-1010 mbar.

6. The method for preparing a semiconductor silicon wafer according to claim 1, characterized in that: The method further comprises a fourth step of performing a second oxidation thinning treatment on the semiconductor silicon wafer after the rapid thermal annealing treatment.

7. The method for preparing a semiconductor silicon wafer according to claim 6, characterized in that: The step 4 includes the following processing: After the rapid thermal annealing treatment stage is completed, the semiconductor silicon wafer after the rapid thermal treatment is loaded into the second vertical furnace tube, and oxidized according to the target thickness, the oxidation temperature range is 800° C.-1000° C., the time is determined according to the target thickness, and the oxidation form is dry oxygen oxidation, water vapor oxidation, or wet oxygen oxidation; The surface oxide layer of the oxidized semiconductor silicon wafer is removed in an HF solution, wherein the HF concentration is less than 20%.

8. A semiconductor silicon wafer with an SOI structure, characterized in that: The top silicon surface roughness of the semiconductor silicon wafer is less than 5 angstroms, and the thickness uniformity is within ±1%. The semiconductor silicon wafer is prepared by the method described in any one of claims 1 to 7.

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