SOI wafer and preparation method thereof

Abstract

The invention provides an SOI wafer and a preparation method thereof, and the method comprises the steps: providing a first silicon wafer, and injecting ions into the first silicon wafer to form an embrittlement layer; a second silicon wafer with an oxide layer formed on the surface is provided, the first silicon wafer and the second silicon wafer are bonded, the first silicon wafer and the second silicon wafer are isolated through the oxide layer, the first silicon wafer is stripped along the embrittlement layer through thermal reaction to form top silicon, and an SOI wafer is obtained; and performing rapid thermal annealing treatment on the SOI wafer, and when the rapid thermal annealing treatment is performed on the SOI wafer, adjusting the temperature of the rapid thermal annealing treatment according to the ion implantation energy when the embrittlement layer is formed. According to the preparation method of the SOI wafer provided by the invention, the temperature when the SOI wafer is subjected to rapid thermal annealing treatment is adjusted according to the injection energy of the ions, and abnormal particles at a specific position on the surface of the top silicon of the SOI wafer can be eliminated or reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an SOI wafer and a preparation method thereof. Background Art

[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. The core feature of this special silicon-based semiconductor manufacturing technology is to form a thin top layer of silicon on the insulator. This structure makes SOI devices perform well in many aspects, such as low power consumption, radiation resistance, and high speed.

[0003] There are three main technologies for preparing SOI wafers: the first is Separation by Implanted Oxygen (SIMOX), the second is Bond and Etch-back SOI (BESOI), and the third is Smart-Cut. Currently, the most commonly used are BESOI and Smart-Cut. BESOI technology uses bonding technology to tightly bond two wafers together. The silicon dioxide layer formed between the wafers is used as an oxide buried layer, and then the thickness of one side of the wafer is thinned to the required thickness using etching technology to form an SOI wafer. Smart-Cut technology is derived from BESOI technology. First, two silicon wafers are prepared, and an insulating layer is generated on one wafer using thermal oxidation. Then, hydrogen ions are implanted into the silicon wafer through ion implantation, and then the two silicon wafers are bonded, and the silicon wafer implanted with hydrogen ions is peeled off through thermal reaction to form a top silicon film.

[0004] In Smart-Cut technology, peeling will cause the top silicon surface to be uneven and rough. Subsequent processes use processes such as rapid annealing to achieve non-contact flattening of the silicon wafer surface, reduce the surface roughness of the silicon wafer, and achieve better particle performance. However, although the rapid annealing process can optimize the pits on the silicon wafer surface, due to the particularity of the peeling surface, defects such as particle aggregation will appear at the edge of a specific position on the silicon wafer surface. This defect appears as a rough surface under a high-power microscope and cannot be improved by cleaning. Summary of the invention

[0005] The object of the present invention is to provide a SOI wafer and a method for preparing the same, so as to solve one or more problems in the prior art.

[0006] In order to solve the above problems, the present invention provides a method for preparing an SOI wafer, comprising:

[0007] Providing a first silicon wafer, and implanting ions into the first silicon wafer to form an embrittled layer, wherein the ion implantation energy when forming the embrittled layer is X;

[0008] Providing a second silicon wafer with an oxide layer formed on the surface, bonding the first silicon wafer to the second silicon wafer, isolating the first silicon wafer and the second silicon wafer by the oxide layer, and peeling the first silicon wafer along the embrittled layer by thermal reaction to form a top layer of silicon, so as to obtain an SOI wafer; and,

[0009] The SOI wafer is subjected to a rapid thermal annealing treatment. When the SOI wafer is subjected to the rapid thermal annealing treatment, a maximum temperature T of the rapid thermal annealing treatment is adjusted according to the value of X.

[0010] Optionally, in the method for preparing the SOI wafer, the value range of X is 50 to 80 keV.

[0011] Optionally, in the method for preparing the SOI wafer, the maximum temperature T of the rapid thermal annealing treatment is adjusted according to the following formula:

[0012] T=A*X+B,2.8 <A<4.9,(1166-52A)<B<(1307-81A)。

[0013] Optionally, in the method for preparing the SOI wafer, the step of performing rapid thermal annealing on the SOI wafer includes:

[0014] Loading the SOI wafer into an annealing furnace chamber and heating the chamber to the maximum temperature T at a set heating rate;

[0015] Maintaining the temperature in the annealing furnace chamber at the maximum temperature T for a set time; and,

[0016] After the annealing furnace chamber is cooled at a set cooling rate, the SOI wafer is moved out of the annealing furnace chamber.

[0017] Optionally, in the method for preparing the SOI wafer, when the SOI wafer is loaded into the annealing furnace chamber, the temperature inside the tube of the annealing furnace chamber is 500-700°C.

[0018] Optionally, in the method for preparing the SOI wafer, when the SOI wafer is moved out of the annealing furnace chamber, the temperature inside the tube of the annealing furnace chamber is 500-700°C.

[0019] Optionally, in the method for preparing the SOI wafer, the heating rate is 5 to 30° C. / S.

[0020] Optionally, in the method for preparing the SOI wafer, the cooling rate is 5 to 30°C / S.

[0021] Optionally, in the method for preparing the SOI wafer, the setting time is 10 to 50 seconds.

[0022] The present invention also provides an SOI wafer, which is prepared by using the preparation method as described in any of the above items.

[0023] In summary, the SOI wafer and its preparation method provided by the present invention include: providing a first silicon wafer, and injecting ions into the first silicon wafer to form an embrittled layer, and the ion injection energy when forming the embrittled layer is X; providing a second silicon wafer with an oxide layer formed on the surface, bonding the first silicon wafer to the second silicon wafer, the first silicon wafer and the second silicon wafer are isolated by the oxide layer, and using thermal reaction to peel off the first silicon wafer along the embrittled layer to form a top layer of silicon, so as to obtain an SOI wafer; and performing rapid thermal annealing on the SOI wafer, and when performing the rapid thermal annealing on the SOI wafer, adjusting the temperature T of the rapid thermal annealing according to the value of X. The preparation method of the SOI wafer provided by the present invention adjusts the temperature of the SOI wafer during the rapid thermal annealing according to the hydrogen ion injection energy, which can eliminate or reduce abnormal particles at specific positions on the top silicon surface of the SOI wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flow chart of a method for preparing an SOI wafer provided in an embodiment of the present invention;

[0025] Figure 2 to Figure 4 for Figure 1 Schematic diagram of the structure corresponding to each step;

[0026] Figure 5 This is a graph showing the particle inspection results of Comparative Example 1 in an embodiment of the present invention;

[0027] Figure 6 This is a graph showing the particle inspection results of Comparative Example 1 in an embodiment of the present invention;

[0028] Figure 7 This is a graph showing the particle inspection results of Comparative Example 1 in an embodiment of the present invention;

[0029] Figure 8 This is a graph showing the particle inspection results of Comparative Example 1 in an embodiment of the present invention;

[0030] Fig. 9 A schematic diagram of defect conditions corresponding to setting the maximum temperature T of the rapid thermal treatment according to the ion implantation energy X in an embodiment of the present invention;

[0031] The descriptions of the reference numerals are as follows:

[0032] 10 - first silicon wafer; 20 - oxide layer; 30 - embrittlement layer; 40 - second silicon wafer; 101 - top silicon wafer. DETAILED DESCRIPTION

[0033] The following is a further detailed description of the SOI wafer and the method for preparing the same proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0034] like Figure 1 As shown, an embodiment of the present invention provides a method for preparing an SOI wafer, comprising the following steps:

[0035] S1, providing a first silicon wafer, and implanting ions into the first silicon wafer to form an embrittled layer, wherein the ion implantation energy when forming the embrittled layer is X;

[0036] S2, providing a second silicon wafer with an oxide layer formed on the surface, bonding the first silicon wafer to the second silicon wafer, isolating the first silicon wafer and the second silicon wafer by the oxide layer, and peeling the first silicon wafer along the embrittled layer by thermal reaction to form a top layer of silicon, so as to obtain an SOI wafer;

[0037] S3, performing a rapid thermal annealing process on the SOI wafer. When performing the rapid thermal annealing process on the SOI wafer, adjusting a temperature T of the rapid thermal annealing process according to the value of X.

[0038] As mentioned above, when a rapid annealing process is performed on an SOI wafer, defects such as particle aggregation will appear at the edge of a specific position on the surface of the silicon wafer. The method for preparing an SOI wafer provided in an embodiment of the present invention adjusts the temperature of the SOI wafer during rapid thermal annealing according to the injection energy of hydrogen ions, thereby eliminating or reducing abnormal particles at a specific position on the top silicon surface of the SOI wafer.

[0039] The following combination Figure 2 to Figure 4 The method for preparing the SOI wafer provided in the embodiment of the present invention is further described in detail.

[0040] First, execute step S1, see Figure 2 , providing a first silicon wafer 10. The diameter of the first silicon wafer 10 may be 200 mm or 300 mm. And implanting ions into the first silicon wafer 10 to form an embrittlement layer 30, the implantation energy is X, and optionally, the ions implanted into the first silicon wafer 10 are hydrogen ions, or the ions implanted into the first silicon wafer 10 are hydrogen ions and helium ions.

[0041] The embrittlement layer 30 has an upper surface and a lower surface relative to each other. When the first silicon wafer 10 is peeled off by thermal reaction, the first silicon wafer 10 is divided into two along the lower surface of the embrittlement layer 30 , so that part of the thickness of the first silicon wafer 10 falls off to form the top silicon layer 101 .

[0042] In step S1, the ion implantation energy determines the ion implantation depth, thereby determining the thickness of the top silicon 101 formed by subsequent thermal reaction stripping of the first silicon wafer 10. That is, the ion implantation energy in step S1 is proportional to the thickness of the top silicon after stripping. The greater the implantation energy, the greater the implantation depth, and the greater the thickness of the top silicon after stripping.

[0043] Preferably, the ion implantation energy X is 50-80kev, for example, 50kev, 60kev, 70kev, 80kev, etc. Within this ion implantation energy range, a top layer of silicon 101 within a target thickness range can be obtained.

[0044] Next, execute step S2, see Figure 3 , providing a second silicon wafer 40, the surface of which is formed with an oxide layer 20, the oxide layer 20 being used as a buried oxide layer and having an isolation and insulation effect, bonding the first silicon wafer 10 to the second silicon wafer 40, the first silicon wafer 10 and the second silicon wafer 40 being isolated by the oxide layer 20. After the first silicon wafer 10 and the second silicon wafer 40 are bonded, see Figure 4 The first silicon wafer 10 is peeled off by thermal reaction to form a top silicon 101, thereby obtaining an SOI wafer. The diameter of the first silicon wafer 10 can be 200 mm or 300 mm.

[0045] Next, step S3 is executed to perform rapid thermal annealing on the SOI wafer. Through rapid thermal annealing, on the one hand, the bonding strength between the first silicon wafer 10 and the second silicon wafer 40 can be enhanced, and on the other hand, the surface roughness can be reduced.

[0046] The inventors' research found that the reason for the defect of particle aggregation easily occurring at the edges of specific positions on the silicon wafer surface after rapid annealing is as follows: In physics, the electron activation energy is related to the atomic mobility, the electron activation energy is related to the non-contact planarization effect of the thin film material, and the melting point is related to the evaporation and reduction of the material during the planarization process.

[0047] In view of the above findings, during the planarization process using the rapid annealing process in step S3, according to the thickness of the top silicon 101, a suitable temperature T is selected to perform planarization on the top silicon 101. In this way, both the planarization effect can be ensured and the generation of additional defects can be reduced or avoided. Preferably, when the ion implantation energy is in the range of 50 - 80 kev, the maximum temperature T of the rapid thermal annealing treatment is adjusted according to the following formula:

[0048] T = A*X + B, where 2.8 < A < 4.9, (1166 - 52A) < B < (1307 - 81A).

[0049] The above formula {T = A*X + B, 2.8 < A < 4.9, (1166 - 52A) < B < (1307 - 81A)} can be represented by the region between the two linear relationships as shown in Fig. 9 The experiment shows that: Fig. 9 Among them, when the maximum temperature T of the rapid heat treatment is set based on any coordinate data (example of gray coordinate points) between the two linear relationships, the corresponding defect detection result is OK, that is, it means that there are no abnormal particles. And when the maximum temperature T of the rapid heat treatment is set based on any coordinate data (example of red coordinate points) outside the two linear relationships, the corresponding defect detection result is NG, that is, it means that there are abnormal particles. From this, it shows that when performing rapid thermal annealing treatment, adjusting the maximum temperature T of the rapid thermal annealing treatment based on the above formula can avoid the generation of additional abnormal particles at specific positions on the surface of the top silicon 101 of the SOI wafer while ensuring the planarization effect.

[0050] In step S3, the steps of performing rapid thermal annealing on the SOI wafer specifically may include:

[0051] S31, load the SOI wafer into the annealing furnace cavity and heat it up to the maximum temperature T calculated by the value of X at the set heating rate;

[0052] S32, maintaining the temperature in the annealing furnace chamber at the highest temperature T for a set time; and

[0053] S33, after cooling the annealing furnace chamber at a set cooling rate, the SOI wafer is moved out of the annealing furnace chamber.

[0054] Preferably, when the SOI wafer is loaded into the annealing furnace chamber, the temperature inside the tube of the annealing furnace chamber is 500-700°C, and when the SOI wafer is moved out of the annealing furnace chamber, the temperature inside the tube of the annealing furnace chamber is 500-700°C.

[0055] In addition, optionally, the heating rate is 5 to 30°C / S, and the cooling rate is 5 to 30°C / S.

[0056] In addition, an embodiment of the present invention further provides an SOI wafer, and the SOI wafer is prepared using the preparation method provided by the embodiment of the present invention.

[0057] The following is a further description of the method for preparing the SOI wafer provided by the embodiment of the present invention in conjunction with four comparative examples. In the following four comparative examples, the thickness and diameter of the silicon wafers forming the SOI wafer are the same, and when describing the four comparative examples, only the specific process of ion implantation energy and rapid thermal annealing is described.

[0058] [Comparative Example 1]

[0059] The ion implantation energy is 54kev, and the maximum temperature of rapid thermal annealing is set to: 1200℃. The SOI wafer is loaded into the annealing furnace chamber when the standby temperature of the annealing furnace chamber is 600℃. Step-by-step temperature increase oxidation begins, and the temperature in the annealing furnace chamber begins to increase at a heating rate of 10℃ / S. After the temperature in the annealing furnace chamber reaches 1200℃, the temperature is kept constant for 30S, and then the temperature in the annealing furnace chamber begins to decrease at a cooling rate of 10℃ / S in the temperature range of 1200℃ to 600℃. The SOI wafer is removed from the annealing furnace chamber when the temperature in the annealing furnace chamber is 600℃.

[0060] [Comparative Example 2]

[0061] The ion implantation energy is 56kev, and the maximum temperature of rapid thermal annealing is set to: 1235℃. The SOI wafer is loaded into the annealing furnace chamber when the standby temperature of the annealing furnace chamber is 600℃. Step-by-step temperature increase oxidation begins, and the temperature in the furnace begins to increase at a heating rate of 10℃ / S. After the temperature in the annealing furnace chamber reaches 1235℃, the temperature is kept constant for 30S, and then the temperature in the annealing furnace chamber begins to decrease at a cooling rate of 10℃ / S in the temperature range of 1235℃ to 600℃. The SOI wafer is removed from the annealing furnace chamber when the temperature in the annealing furnace chamber is 600℃.

[0062] [Comparative Example 3]

[0063] The ion implantation energy is 74 keV, and the maximum temperature of rapid thermal annealing is set at: 1200 °C. The SOI wafer is loaded into the annealing furnace cavity at a standby temperature of 600 °C in the annealing furnace cavity. Start stepwise temperature-rising oxidation, and start increasing the temperature in the furnace at a rate of 10 °C / S. After the temperature in the annealing furnace cavity reaches 1200 °C, keep it at a constant temperature for 30 s. Then, start decreasing the temperature in the annealing furnace cavity at a rate of 10 °C / S in the temperature range of 1200 °C to 600 °C, and take out the SOI wafer outside the annealing furnace cavity when the temperature in the annealing furnace cavity is 600 °C.

[0064]

Comparative Example 4

[0065] The ion implantation energy is 74 keV, and the maximum temperature of rapid thermal annealing is set at: 1260 °C. The SOI wafer is loaded into the annealing furnace cavity at a standby temperature of 600 °C in the annealing furnace cavity. Start stepwise temperature-rising oxidation, and start increasing the temperature in the annealing furnace cavity at a rate of 10 °C / S. After the temperature in the annealing furnace cavity reaches 1260 °C, keep it at a constant temperature for 30 s. Then, start decreasing the temperature in the annealing furnace cavity at a rate of 10 °C / S in the temperature range of 1260 °C to 600 °C, and take out the SOI wafer outside the annealing furnace cavity when the temperature in the annealing furnace cavity is 600 °C.

[0066] The comparison results of the above four comparative examples are shown in Table 1:

[0067] Table 1

[0068]

[0069] Figures 5 to 8 They are respectively the surface particle junction detection result diagrams of Comparative Example 1 to Comparative Example 4 under the 65 nm light scattering channel. From Table 1 and in combination with Figures 5 to 8 It can be seen that the actual maximum temperatures in the annealing furnace cavity during rapid heat treatment in Comparative Example 1, Comparative Example 2, and Comparative Example 4 are all within the temperature range calculated by using the formula {T = A*X + B, 2.8 < A < 4.9, (1166 - 52A) < B < (1307 - 81A)}. After rapid heat treatment, no particle aggregation defects will appear at specific positions (near the 12 o'clock direction in the figure) on the surface of the top silicon layer. However, the actual maximum temperature in the annealing furnace cavity during rapid heat treatment in Comparative Example 3 is not within the temperature range calculated by using the formula {T = A*X + B, 2.8 < A < 4.9, (1166 - 52A) < B < (1307 - 81A)}. After rapid heat treatment, particle aggregation defects appear at specific positions on the surface of the top silicon layer. Thus, it can be seen that the SOI wafer preparation method provided by this embodiment can solve the problem of particle aggregation defects on the surface of the top silicon layer after rapid heat treatment.

[0070] In summary, the method for preparing an SOI wafer provided in an embodiment of the present invention includes: providing a first silicon wafer, and injecting ions into the first silicon wafer to form an embrittled layer, wherein the ion injection energy when forming the embrittled layer is X; providing a second silicon wafer with an oxide layer formed on the surface, bonding the first silicon wafer to the second silicon wafer, isolating the first silicon wafer and the second silicon wafer by the oxide layer, and utilizing a thermal reaction to peel off the first silicon wafer along the embrittled layer to form a top layer of silicon, so as to obtain an SOI wafer; and performing a rapid thermal annealing treatment on the SOI wafer, and when performing the rapid thermal annealing treatment on the SOI wafer, adjusting the temperature T of the rapid thermal annealing treatment according to the value of X. The method for preparing an SOI wafer provided by the present invention adjusts the temperature of the SOI wafer during the rapid thermal annealing treatment according to the injection energy of hydrogen ions, and can eliminate or reduce abnormal particles at specific positions on the top silicon surface of the SOI wafer.

[0071] It should be noted that, although the present invention has been disclosed as a preferred embodiment, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the technical content disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a SOI wafer, characterized in that: include: Providing a first silicon wafer, and implanting ions into the first silicon wafer to form an embrittled layer, wherein the ion implantation energy when forming the embrittled layer is X; Providing a second silicon wafer with an oxide layer formed on the surface, bonding the first silicon wafer to the second silicon wafer, isolating the first silicon wafer and the second silicon wafer by the oxide layer, and peeling the first silicon wafer along the embrittled layer by thermal reaction to form a top layer of silicon, so as to obtain an SOI wafer; and, The SOI wafer is subjected to a rapid thermal annealing treatment. When the SOI wafer is subjected to the rapid thermal annealing treatment, a maximum temperature T of the rapid thermal annealing treatment is adjusted according to the value of X.

2. The method for preparing an SOI wafer according to claim 1, wherein: The value range of X is 50~80keV.

3. The method for preparing an SOI wafer according to claim 2, wherein: The maximum temperature T of the rapid thermal annealing treatment is adjusted according to the following formula: T=A*X+B,2.8 <A<4.9,(1166-52A)<B<(1307-81A)。 4. The method for preparing an SOI wafer according to claim 1, wherein: The step of performing rapid thermal annealing on the SOI wafer comprises: Loading the SOI wafer into a rapid annealing furnace chamber, and heating the temperature to the maximum temperature T at a set heating rate; Maintaining the temperature in the annealing furnace chamber at the maximum temperature T for a set time; and, After the annealing furnace chamber is cooled at a set cooling rate, the SOI wafer is moved out of the annealing furnace chamber.

5. The method for preparing an SOI wafer according to claim 4, characterized in that: When the SOI wafer is loaded into the annealing furnace chamber, the temperature in the annealing furnace chamber is 500-700°C.

6. The method for preparing an SOI wafer according to claim 4, characterized in that: When the SOI wafer is moved out of the annealing furnace chamber, the temperature inside the annealing furnace chamber is 500-700°C.

7. The method for preparing an SOI wafer according to claim 4, wherein: The heating rate is 5-30°C / S.

8. The method for preparing an SOI wafer according to claim 4, wherein: The cooling rate is 5-30°C / S.

9. The method for preparing an SOI wafer according to claim 4, wherein: The setting time is 10 to 50 seconds.

10. An SOI wafer, characterized in that: The SOI wafer is prepared by using the preparation method according to any one of claims 1 to 9.

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