Super junction IGBT with low turn-off current tail and manufacturing method thereof

Abstract

The present invention discloses a superjunction IGBT with low turn-off current tail and a method for manufacturing the same. The superjunction IGBT comprises a collector region, a drift region, an epitaxial layer, and a well region; a superjunction structure is distributed within the drift region, the superjunction structure including a columnar structure; an emitter is formed above the well region, and gates are distributed within the epitaxial layer and the well region. Each emitter is electrically isolated from the upper portion of a corresponding gate, and the lower portion of each gate extends into the epitaxial layer; the lower end of the collector region is electrically coupled to the collector; the collector region, well region, and columnar structure are all of a first conductivity type, and the drift region, epitaxial layer, and emitter are all of a second conductivity type; the lower end of the columnar structure is also electrically in contact with a highly doped region of the second conductivity type, which is distributed within the drift region and has no contact with the collector region. The superjunction IGBT provided by the present invention reduces turn-off current tail, thereby reducing turn-off energy loss.

Description

Technical Field

[0001] The present invention relates to the technical field of surface modification, and in particular to a super junction IGBT with low off-current tailing and a manufacturing method thereof. Background Art

[0002] IGBT stands for Insulated Gate Bipolar Transistor. Functionally, an IGBT is a circuit switch. Its advantages lie in its voltage control, low saturation voltage drop, and high withstand voltage. It can be used in high-voltage applications with voltages ranging from tens to hundreds of volts and currents from tens to hundreds of amperes. Furthermore, IGBTs do not require mechanical switches; they are controlled by computers.

[0003] As a new generation of high-speed IGBT design technology, the excellent electrical performance of super junction IGBT has been verified experimentally. For example, the device structure of a super junction IGBT is as follows: Figure 1 As shown, 1 is the P-collector region, 2 is the N-drift region, 3 is the columnar structure of the P-type super junction, 4 is the epitaxial layer, 5 is the gate oxide layer, 6 is the gate, 7 is the P-well region, 8 is the N+ emitter, 9 is the dielectric layer, 10 is the emitter metal, 11 is the P+ collector, and 12 is the collector metal.

[0004] The excellent forward conduction capability of an IGBT device is due to the conductivity modulation mechanism in the device's drift region. This physical mechanism accumulates a large number of minority carriers in the device's drift region 2. When the IGBT is turned off, the minority carriers in drift region 2 gradually disappear, forming a tail current. This tail current significantly prolongs the IGBT's turn-off process, thereby increasing turn-off losses. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present invention aims to provide a super junction IGBT with low turn-off current tail and a method for manufacturing the same, so as to reduce the current tail during the turn-off process of the super junction IGBT and ultimately achieve the purpose of reducing turn-off losses.

[0006] To achieve the aforementioned object of the invention, the technical solutions adopted by the present invention include:

[0007] In the first aspect, the present invention provides a super junction IGBT with low turn-off current tail, comprising a collector region, a drift region, an epitaxial layer and a well region arranged in sequence from bottom to top; a plurality of super junction structures are distributed in the drift region, and the super junction structure includes a columnar structure, which extends from the upper end of the drift region to the inside of the drift region but has no direct contact with the collector region; a plurality of emitters are formed on the upper part of the well region, and a plurality of gates are distributed in the epitaxial layer and the well region, each emitter is arranged around the upper part of a corresponding gate and is electrically isolated from the gate, and the lower part of each gate enters the epitaxial layer but has no direct contact with the drift region; the lower end of the collector region is electrically combined with the collector; the collector region, the well region and the columnar structure are all of the first conductivity type, and the drift region, the epitaxial layer and the emitter are all of the second conductivity type; the lower end of the columnar structure is also electrically contacted with a highly doped region of the second conductivity type, and the highly doped region is distributed in the drift region and has no direct contact with the collector region.

[0008] In a second aspect, the present invention further provides a method for manufacturing the super junction IGBT, comprising:

[0009] growing a drift region on an upper surface of a substrate, wherein the substrate is of a first conductivity type;

[0010] A plurality of deep trenches are formed on the upper end surface of the drift region, and a high-doping region and a columnar structure are sequentially formed in each deep trench along the direction from the bottom end to the opening;

[0011] growing an epitaxial layer on the drift region;

[0012] A plurality of gate grooves are formed on the upper end surface of the epitaxial layer, and a gate oxide layer is formed on the inner wall of each gate groove, and then each gate groove is filled with polysilicon of the second conductivity type to form a gate;

[0013] converting at least an upper portion of the epitaxial layer into a well region;

[0014] Converting multiple regions above the well region into multiple emitters, and placing each emitter around the upper portion of the gate;

[0015] A plurality of insulating dielectric layers are provided on the upper end surface of the well region, wherein each insulating dielectric layer completely covers the upper end surface of a corresponding gate;

[0016] Disposing an emitter metal on the upper end surface of the well region and electrically combining the emitter metal with the emitter; and

[0017] A collector electrode and a collector metal are sequentially arranged on the lower end surface of the substrate.

[0018] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention include at least:

[0019] The super junction IGBT with low turn-off current tail provided by the present invention utilizes a highly doped region arranged at the lower end of the columnar structure of the super junction to accelerate the carrier recombination rate during the device shutdown process, thereby achieving the effect of reducing the current tail when the super junction device is turned off, thereby achieving the purpose of reducing the turn-off energy loss.

[0020] The above description is only an overview of the technical solution of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of this application and implement them according to the contents of the specification, the following is an explanation of the preferred embodiments of the present invention with detailed drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic structural diagram of a super junction IGBT in the prior art provided by a typical embodiment of the present invention;

[0022] Figure 2 This is a schematic structural diagram of a super junction IGBT provided by a typical embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the overall process of the production method provided by a typical embodiment of the present invention;

[0024] Figure 4 1 is a schematic diagram of the structure of a super junction IGBT device in a step of a manufacturing method provided in a typical embodiment of the present invention;

[0025] Figure 5 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0026] Figure 6 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0027] Figure 7 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0028] Figure 8 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0029] Figure 9 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0030] Figure 10 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0031] Figure 11 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0032] Figure 12 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0033] Figure 13 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0034] Figure 14 1 is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention;

[0035] Figure 15 This is a schematic diagram of the structure of a super junction IGBT device in another step of the manufacturing method provided in a typical embodiment of the present invention.

[0036] Explanation of reference numerals: 1. collector region; 2. drift region; 3. columnar structure; 4. epitaxial layer; 5. gate oxide layer; 6. gate; 7. well region; 8. emitter; 9. insulating dielectric layer; 10. emitter metal; 11. collector; 12. collector metal; 13. highly doped region;

[0037] 101, first photoresist layer; 102, deep trench; 103, gate trench; 104, second photoresist layer. DETAILED DESCRIPTION

[0038] In view of the shortcomings of the prior art, the inventors of this case, after long-term research and extensive practice, have proposed the technical solution of the present invention. The following will further explain this technical solution, its implementation process and principles.

[0039] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0040] Moreover, relational terms such as “first” and “second” are merely used to distinguish one component or method step from another with the same name, but do not necessarily require or imply any actual relationship or order between these components or method steps.

[0041] like Figure 2As shown, an embodiment of the present invention provides a super junction IGBT with low turn-off current tail, comprising a collector region 1, a drift region 2, an epitaxial layer 4 and a well region 7 arranged in sequence from bottom to top; a plurality of super junction structures are distributed in the drift region 2, and the super junction structure includes a columnar structure 3, which extends from the upper end of the drift region 2 to the inside of the drift region 2 but has no direct contact with the collector region 1; a plurality of emitters 8 are formed on the upper part of the well region 7, and a plurality of gates 6 are distributed in the epitaxial layer 4 and the well region 7, and each emitter 8 surrounds the corresponding The upper part of a gate 6 is arranged and electrically isolated from the gate 6, and the lower part of each gate 6 enters the epitaxial layer 4 but has no direct contact with the drift region 2; the lower end of the collector region 1 is electrically combined with the collector electrode 11; the collector region 1, the well region 7, and the columnar structure 3 are all of the first conductivity type, and the drift region 2, the epitaxial layer 4, and the emitter 8 are all of the second conductivity type; the lower end of the columnar structure 3 is also electrically contacted with a highly doped region 13 of the second conductivity type, and the highly doped region 13 is distributed in the drift region 2 and has no direct contact with the collector region 1.

[0042] In the above technical solution, the direction from bottom to top refers to the direction from the collector region 1 to the well region 7, and does not represent the top and bottom in the spatial sense. During the manufacturing and use process, depending on the placement position and placement direction of the super junction IGBT or its semi-finished product, the direction from the collector region 1 to the well region 7 can also be understood as the direction from top to bottom, or from left to right, or from right to left, or tilted, etc. in the spatial sense.

[0043] The highly doped region 13 can form a P-N+ structure with the columnar structure 3. The above structure can effectively reduce the degree of conductivity modulation in the drift region at the bottom of the super junction, thereby reducing the number of minority carriers in this region. This structure can complete the recombination of minority carriers in a shorter time when the IGBT is turned off, thereby accelerating the IGBT current drop rate, thereby reducing the current tail time when the IGBT is turned off, and thus reducing the turn-off energy loss.

[0044] The first conductivity type may be, for example, P-type, and the second conductivity type may be, for example, N-type. In some typical application examples, the superjunction IGBT includes a P-collector region 1, an N-drift region 2, a P-type pillar structure 3, an epitaxial layer 4, a gate oxide layer 5, a gate 6, a P-well region 7, an N+ emitter 8, an insulating dielectric layer 9, an emitter metal 10, a P+ collector 11, a collector metal 12, and an N-type highly doped region 13. In other application examples, the first conductivity type may also be N-type, and the second conductivity type may be P-type.

[0045] In some embodiments, a plurality of deep trenches 102 are provided on the upper end surface of the drift region 2 , and each deep trench 102 is filled with a high-doped region 13 and a columnar structure 3 in sequence from bottom to top. The high-doped region 13 and the columnar structure 3 are both in electrical contact with the drift region 2 .

[0046] In some embodiments, a plurality of gate grooves 103 are provided on the upper end surface of the well region 7, the lower end of each gate groove 103 extends into the epitaxial layer 4, and each gate groove 103 is filled with polysilicon of the second conductive type, and the polysilicon is electrically isolated from the well region 7 and the epitaxial layer 4 by the gate oxide layer 5.

[0047] In some embodiments, the well region 7 is formed by converting at least the upper region of the epitaxial layer 4 .

[0048] In some embodiments, a collector metal 12 is further provided on the upper end surface of the well region 7 . The collector metal 12 is electrically coupled to the collector 11 , and the collector metal 12 is electrically isolated from the gate 6 via an insulating dielectric layer 9 .

[0049] In some embodiments, the doping concentration of the highly doped region 13 is 2-10 times that of the columnar structure.

[0050] In some embodiments, the thickness of the highly doped region 13 along the axial direction of the columnar structure 3 is 1 / 30-1 / 10 of the length of the columnar structure 3 .

[0051] See also Figure 3-Figure 13 , an embodiment of the present invention provides a method for manufacturing a super junction IGBT in any of the above embodiments, comprising the following steps:

[0052] S1: growing a drift region 2 on the upper end surface of a substrate, wherein the substrate is of a first conductivity type. Figure 4 In step S1, chemical vapor deposition or physical vapor deposition and ion implantation can be used to form the drift region 2 of the second conductivity type on one side of the substrate.

[0053] S2: A plurality of deep trenches 102 are formed on the upper surface of the drift region 2, and a high-doping region 13 and a columnar structure 3 are sequentially formed in each deep trench 102 along the direction from the bottom to the opening. Figure 5 The deep trench 102 can be opened by the following method: forming a first photoresist layer 101 on the upper surface of the drift region 2, the first photoresist layer 101 having a first photoresist opening of a specific size, and then etching the drift region 2 through the first photoresist opening to form the deep trench 102 at a selected position of the drift region 2.

[0054] S3: growing an epitaxial layer 4 on the drift region 2. Figure 8 In step S3, epitaxial growth and ion implantation may be continued on the side of the drift region 2 away from the substrate to form an epitaxial layer 4 of the second conductivity type.

[0055] S4: A plurality of gate trenches 103 are formed on the upper end surface of the epitaxial layer 4, and a gate oxide layer 5 is formed on the inner wall of each gate trench 103. Then, each gate trench 103 is filled with polysilicon of the second conductivity type to form a gate 6. Figure 9-10 After forming the epitaxial layer 4 of the second conductivity type, a second photoresist layer 104 can be deposited on a side of the epitaxial layer 4 away from the drift region 2. The second photoresist layer 104 has a specific second photoresist opening. Then, the epitaxial layer 4 is etched from the second photoresist opening by dry etching or wet etching to form a gate trench 103. After forming the gate trench 103, a gate oxide layer 5 can be formed on the inner wall and bottom of the gate trench 103 by CVD or PVD. Then, polycrystalline silicon dioxide is continued to be grown in the gate trench 103 to form a gate 6.

[0056] S5: At least the upper portion of the epitaxial layer 4 is converted into the well region 7. Figure 11 In step S5 , ion implantation may be performed on the upper portion of the epitaxial layer 4 so that the upper portion of the epitaxial layer 4 is converted into a well region 7 of the first conductivity type.

[0057] S6: converting the multiple regions above the well region 7 into multiple emitters 8, and making each emitter 8 surround the upper portion of the gate 6. Figure 12 The emitter electrodes 8 that are spaced around and surround the gate 6 can be formed in a portion of the well region 7 by using a method of ion implantation plus high-temperature diffusion.

[0058] S7: A plurality of insulating dielectric layers 9 are provided on the upper end surface of the well region 7, wherein each insulating dielectric layer 9 completely covers the upper end surface of a corresponding gate 6. Figure 13 The insulating dielectric layer 9 can be formed by laying a mask pattern and performing chemical vapor deposition or physical vapor deposition.

[0059] S8: an emitter metal 10 is provided on the upper end surface of the well region 7, and the emitter metal 10 is electrically connected to the emitter 8. Figure 13 The emitter metal 10 can be formed by evaporation, atomic layer deposition or magnetron sputtering.

[0060] And S9: a collector electrode 11 and a collector metal 12 are sequentially provided on the lower end surface of the substrate. Figure 14-15 The lower half of the collector region 1 can be converted into a collector electrode 11 by ion implantation, and then the collector metal 12 can be covered on the surface of the collector electrode 11 by evaporation, atomic layer deposition or magnetron sputtering.

[0061] In some embodiments, step S2 may specifically include: forming the highly doped region 13 by adopting an ion implantation method or a chemical vapor deposition method.

[0062] In some embodiments, in step S7 , the insulating dielectric layer 9 also covers a portion of the emitter 8 .

[0063] Several embodiments are provided below to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0064] Example 1

[0065] This embodiment provides a structure of a super junction IGBT, such as Figure 2 As shown, it includes a P-collector region 1, an N-drift region 2, an epitaxial layer 4, and a P-well region 7 that are electrically contacted in sequence. A plurality of superjunction P-type columnar structures 3 are distributed in the N-drift region 2. The upper end of the P-type columnar structure 3 is electrically contacted with the P-well region 7, and the lower end is electrically contacted with one end of the N-type highly doped region 13. The other end of the N-type highly doped region 13 is electrically contacted with the N-drift region 2, and the sidewalls of the P-type columnar structure 3 and the highly doped region 13 are both electrically contacted with the N-drift region 2; the P-well region 7 is provided with a gate 6 that penetrates into the epitaxial layer 4 The sidewalls of the gate 6 are covered with an insulating gate oxide layer 5, and an N+ emitter 8 surrounding the gate 6 is provided in the upper half of the well region 7 and around the gate 6. Part of the surface of the N+ emitter 8 is covered with an insulating dielectric layer 9, and the dielectric layer completely covers the gate 6; the upper and lower surfaces of the super junction IGBT are also respectively provided with an emitter metal 10 and a collector metal 12, the emitter metal 10 is electrically contacted with the well region 7 and the emitter 8, and the collector metal 12 is electrically contacted with the P- collector region 1 through the P+ collector 11.

[0066] Furthermore, this embodiment also provides a method for manufacturing the super junction IGBT, comprising the following steps:

[0067] (1) Figure 4 As shown, a substrate with a P-collector region 1 is provided, and an N-drift region 2 is formed on a first surface of the substrate by CVD epitaxial growth;

[0068] (2) Figure 5 As shown, a photoresist is coated on the upper surface of the N-drift region 2, and after baking, exposure, and development, a first photoresist layer 101 is formed. The N-drift region 2 is etched using the first photoresist opening of the first photoresist layer 101 to form a deep trench 102;

[0069] (3) Figure 6As shown, the surface structure at the bottom of the deep trench 102 is directly transformed into an N-type highly doped region 13 by ion implantation.

[0070] (4) Figure 7 As shown, using the CVD growth method, the deep trench 102 with the N-type high-doped region 13 formed at the bottom is further filled with P-type doped silicon to form a columnar structure 3;

[0071] (5) Figure 8 As shown, secondary epitaxial growth is performed on the upper surface of the N-drift region 2 to form an N-type epitaxial layer 4;

[0072] (6) Figure 9 As shown, a photoresist is coated on the upper surface of the epitaxial layer 4, and after baking, exposure, and development, a second photoresist layer 104 is formed. The epitaxial layer 4 is etched through the opening of the second photoresist layer 104 to form a gate groove 103;

[0073] (7) Figure 10 As shown, an oxide layer is formed on the inner wall of the gate trench 103 and the surface of the epitaxial layer 4, and then the oxide layer on the surface of the epitaxial layer 4 is etched away to form a gate oxide layer 5;

[0074] (8) Figure 11 As shown, a P-type well region 7 is formed in the upper half of the epitaxial layer 4 by using ion implantation and high-temperature diffusion;

[0075] (9) Figure 12 As shown, an N+ emitter 8 is formed in the well region 7 near the gate 6 by ion implantation and high-temperature diffusion.

[0076] (10) Figure 13 As shown, a mask pattern plus CVD deposition method is used to deposit an insulating dielectric layer on the surface of the well region 7 that completely covers the gate 6 and partially covers the N+ emitter 8, and an emitter metal 10 is deposited on the surface of the dielectric layer and the surface of the well region 7 by evaporation;

[0077] (11) The substrate (i.e., the P- collector region 1) is thinned and ion implanted and high-temperature diffused to form a P+ collector electrode 11 in the lower half of the collector region 1, and a collector metal 12 is evaporated on the lower surface of the P+ collector electrode 11, as shown in FIG. Figure 14-15 shown.

[0078] Comparative Example 1

[0079] The structure of a super junction IGBT provided in this comparative example is as follows Figure 1 As shown, the manufacturing method is basically the same as that of embodiment 1, but the operation of directly converting the surface structure at the bottom of the first trench into the N-type highly doped region 13 by ion implantation is omitted.

[0080] Detection method

[0081] The super junction IGBTs provided in Example 1 and Comparative Example 1 were tested for on-state voltage drop, tail current time, and turn-off loss, and the results are as follows:

[0082] The super junction IGBT provided in Example 1 has a turn-on voltage drop of 1.62V, a tail current time of 100ns, and a turn-off loss of 1.02mJ.

[0083] The super junction IGBT provided in Comparative Example 1 has a turn-on voltage drop of 1.60 V, a tail current time of 150 ns, and a turn-off loss of 1.26 mJ.

[0084] Result Analysis

[0085] Based on the above test results, it is clear that compared with the prior art, the super junction IGBT provided by the embodiment of the present invention significantly reduces the tail current time while having little impact on the on-state voltage drop, thereby significantly reducing the turn-off energy loss.

[0086] It should be understood that the above embodiments are merely illustrative of the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent variations or modifications made in accordance with the spirit and substance of the present invention are intended to be encompassed within the scope of protection of the present invention.

Claims

1. A superjunction IGBT with low turn-off current tail, comprising a collector region, a drift region, an epitaxial layer, and a well region arranged in sequence from bottom to top; a plurality of superjunction structures are distributed in the drift region, the superjunction structures including columnar structures, the columnar structures extending from the upper end of the drift region into the interior of the drift region but not in direct contact with the collector region; a plurality of emitters are formed at the upper portion of the well region, a plurality of gates are distributed in the epitaxial layer and the well region, each emitter is arranged around the upper portion of a corresponding gate and is electrically isolated from the gate, and the lower portion of each gate extends into the epitaxial layer but not in direct contact with the drift region; the lower end of the collector region is electrically coupled to the collector; the collector region, well region, and columnar structures are all of a first conductivity type, and the drift region, epitaxial layer, and emitter are all of a second conductivity type; and the invention is characterized in that: The lower end of the columnar structure is also in electrical contact with a highly doped region of the second conductivity type. The highly doped region is distributed in the drift region and has no direct contact with the collector region.

2. The super junction IGBT according to claim 1, wherein: A plurality of deep grooves are opened on the upper end surface of the drift region, and each deep groove is filled with a high-doped region and a columnar structure in sequence from bottom to top. The high-doped region and the columnar structure are both in electrical contact with the drift region.

3. The super junction IGBT according to claim 1, wherein: A plurality of gate grooves are opened on the upper end surface of the well region, the lower end of each gate groove extends into the epitaxial layer, and each gate groove is filled with polysilicon of the second conductivity type. The polysilicon is electrically isolated from the well region and the epitaxial layer by a gate oxide layer.

4. The super junction IGBT according to claim 1, wherein: The well region is formed by transforming at least an upper region of the epitaxial layer.

5. The super junction IGBT according to claim 1, wherein: A collector metal is also provided on the upper end surface of the well region. The collector metal is electrically combined with the collector, and the collector metal is electrically isolated from the gate via an insulating dielectric layer.

6. The super junction IGBT according to claim 1, wherein: The doping concentration of the high-doping region is 2-10 times that of the columnar structure.

7. The super junction IGBT according to claim 6, wherein: The thickness of the highly doped region along the axial direction of the columnar structure is 1 / 30-1 / 10 of the length of the columnar structure.

8. The method for manufacturing a super junction IGBT according to any one of claims 1 to 7, characterized in that: include: growing a drift region on an upper surface of a substrate, wherein the substrate is of a first conductivity type; A plurality of deep trenches are formed on the upper end surface of the drift region, and a high-doping region and a columnar structure are sequentially formed in each deep trench along the direction from the bottom end to the opening; growing an epitaxial layer on the drift region; A plurality of gate grooves are formed on the upper end surface of the epitaxial layer, and a gate oxide layer is formed on the inner wall of each gate groove, and then each gate groove is filled with polysilicon of the second conductivity type to form a gate; converting at least an upper portion of the epitaxial layer into a well region; Converting multiple regions above the well region into multiple emitters, and placing each emitter around the upper portion of the gate; A plurality of insulating dielectric layers are provided on the upper end surface of the well region, wherein each insulating dielectric layer completely covers the upper end surface of a corresponding gate; Disposing an emitter metal on the upper end surface of the well region and electrically combining the emitter metal with the emitter; and A collector electrode and a collector metal are sequentially arranged on the lower end surface of the substrate.

9. The production method according to claim 8, characterized in that: Specifically include: The highly doped region is formed by ion implantation or chemical vapor deposition.

10. The manufacturing method according to claim 9, characterized in that: The insulating dielectric layer also covers a portion of the emitter.

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