Control chip and built-in MOS tube driving speed control method thereof

Abstract

The present invention discloses a control chip and a method for controlling the driving speed of a built-in MOS tube thereof. The control chip is provided with a programmable current input pin, which is connected to the input voltage of a flyback converter through a resistor. The current value input to the programmable current input pin is controlled by adjusting the resistance value of the resistor. The current value increases with the increase of the input voltage of the flyback converter and decreases with the decrease of the input voltage. The control chip has a built-in MOS tube, and the opening and closing speed of the built-in MOS tube is controlled by controlling the current of the programmable current input pin. When the current of the programmable current input pin increases, the opening and closing speed of the built-in power MOS slows down, and when the current of the programmable current input pin decreases, the opening and closing speed of the built-in power MOS tube speeds up. The switching speed of the MOS tube of the present invention is adaptive to the change of the input voltage of the flyback converter, and meets the required indicators under different input voltages.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS tube driving circuits, and in particular to a built-in MOS tube driving speed adaptive control chip and a flyback converter. Background Art

[0002] In the decades of development of silicon semiconductor integrated circuit technology, especially the special technology suitable for power chip design, the first-generation Biporlar process that originally only included bipolar transistors has developed into the CMOS process with higher integration of insulated gate MOS tubes, and then the BCD process that includes bipolar devices, CMOS devices and DMOS devices has been developed. With each generation of semiconductor technology advancement, the corresponding power chip integration and performance have followed the advancement of the generation. For example, decades ago, TI (Texas Instruments) launched a series of first-generation classic power control chips such as UCC3843, UCC3842, and UCC6840. They are power control chips designed based on mature Bipolar processes. They are a process from scratch. Due to their long history and simple and easy-to-learn functions, some process designs have been written into textbooks, making them chips familiar to generations of power engineers. Even today when various advanced semiconductor processes have matured, these chips are also widely used in power design in various fields. The second generation CMOS process is characterized by high integration. The power chip based on this process naturally has more functions and lower power consumption, such as LM5020 and LM5021 launched by TI, NCP12700 of NCP (ON Semiconductor), etc. In recent years, the rapid development of the characteristic process of analog integrated circuit semiconductors has made the third generation BCD process have significant advantages over the previous two generations. The most basic advantage is that circuit designers can freely choose between high-precision analog bipolar devices, highly integrated CMOS devices and DMOS devices as power output stages. In particular, the resistivity of LDMOS tubes drops significantly while maintaining the same withstand voltage, making the intelligent power integrated circuit (SPIC) of integrated circuit technology that integrates high-voltage power devices and low-voltage signal processing circuits and peripheral interface, detection, protection and other functional circuits on a single chip a trend. LT (Linear Technology Corporation) launched the LT8302 series of products relatively early, and TI has also launched the LM5181 series of products in the past two years.

[0003] like Figure 1 As shown in the figure, it is a simple schematic diagram of the first and second generation power control chip. It forms a flyback converter with the peripheral flyback transformer, resistor, capacitor, etc. Its working principle is: P 、N S 、N AThey are the primary winding, secondary winding and auxiliary winding of the flyback transformer. When the power MOS tube NM0 is turned on, the primary winding NP passes the current, the transformer is excited and stores energy, at this time the secondary winding and the auxiliary winding are both cut off; when the MOS tube NM0 is turned off, the primary winding voltage is reversed and cut off, and the secondary winding N S and N A demagnetization, and N A With N S The voltage of the windings is proportional to the number of turns in their coils, and the energy is mainly passed through N S Passed to the flyback converter output V OUT When V OUT When the voltage is high, the negative input terminal of the differential amplifier EA is greater than the reference voltage V ref , its output voltage V C decreases, then the current sampling resistor R CS The current passing through decreases, and the energy stored in the flyback transformer during excitation decreases, and correspondingly released to V during demagnetization. OUT The energy of V OUT voltage decreases; conversely, when V OUT When the voltage is low, the negative input terminal of the differential amplifier is less than the reference voltage V ref , its output voltage V C Increase, under the control of this voltage, more energy is transferred to the output terminal V through the flyback transformer OUT This can be repeated to continuously adjust the target output voltage V OUT The output voltage of the error amplifier EA reaches a stable value. C It is called pulse width modulation voltage. The excitation current of the flyback transformer is in the sampling resistor R CS The generated voltage is the same as V C Comparison determines the pulse time width of the MOS tube NM0 and the excitation current of the transformer, so by modulating the voltage V C The size of the flyback converter load can be determined by the size of Figure 2 In this case, the secondary side V is sensed by the auxiliary winding of the flyback transformer which shares the same ground with the control chip. OUT This feedback method is often called primary side feedback PSR (Primary Side Feedback). As the name suggests, there is also a corresponding secondary side feedback SSR (Secondary Side Feedback), such as Figure 2 As shown, TL431, optocoupler and other resistors and capacitors form an isolated transconductance amplifier, which works with the pull-up resistor at the chip feedback pin FB to generate a pulse width modulation voltage V C , so it plays the same role as the differential amplifier EA in the PSR feedback mode, except that the voltage divider resistor RFB1 and R FB2 Directly sense V on the secondary side of the isolated flyback converter OUT , hence the name secondary side feedback.

[0004] When the flyback converter turns off the power tube, the transformer leakage inductance will generate a spike voltage. The faster the turn-off speed, the greater the spike voltage. At the same time, it causes excessive dv / dt and generates electromagnetic interference EMI problems. The advantage is that the turn-off loss is small. Their common feature is that the drive circuit and MOS tube are built on the periphery of the chip. Figure 2 Middle drive resistor R G1 Used to adjust the opening speed and drive the resistor R G2 Used to adjust the turn-off speed, resistor R sn , capacitor C sn 、Diode D sn The commonly used RCD absorption can absorb the leakage inductance spike to a certain extent, avoid exceeding the breakdown voltage of the MOS tube and improve EMI. Because the specification requirements of the flyback converter and the specifications and processing technology of the transformer are diverse, it is difficult to meet all applications with a set of circuit parameters. Therefore, when designing a flyback converter, it is often necessary to compromise the performance of switching loss, leakage inductance spike, and EMI by debugging the drive resistance and RCD absorption. The advantage of this external MOS tube solution is that engineers can adjust the drive speed and RCD absorption capacity according to actual applications. The disadvantage is that the flyback converter has the same turn-off speed at low input voltage and high input voltage. In fact, the peak voltage of the power MOS tube is only likely to exceed its breakdown voltage at high input voltage. In order to reduce the peak voltage of the high-voltage input, the switching speed of the low-voltage input is also slowed down, and the switching loss increases.

[0005] like Figure 3 As shown in the figure, it is the third generation of power integrated power control chip. Its low voltage signal processing circuit and peripheral interface, detection, protection and other functional circuits and high voltage power MOS tube are integrated on one wafer. The advantage of this integrated solution is that the periphery is extremely simple, easy to layout PCB, and no additional series resistor (R senseGenerally, the wiring of the source of the built-in MOS tube (which exists by itself, not an additional series resistor) is used to sense the current of the power MOS tube, which improves the sampling efficiency. The disadvantage is that the internal resistance of the built-in MOS tube is not as advantageous as that of the external MOS tube. In order to obtain the smallest internal resistance possible, the breakdown voltage of the built-in MOS tube will not leave too much margin, so it is particularly important to prevent the leakage inductance spike from being too large. TVS tubes are often used to absorb the leakage inductance spike voltage, and even RC is combined to fully absorb the high-frequency and low-frequency components of the spike voltage. It can be seen that although the third-generation single-chip power integrated power chip solution has new and unique advantages, it still has the same shortcomings as the previous two generations of solutions in the driving circuit. In addition, since the power MOS tube is integrated inside the chip, engineers cannot debug the switching speed according to the actual needs of the power converter, and it is not universally applicable. Summary of the invention

[0006] The purpose of the present invention is to provide a control chip and a method for controlling the driving speed of a built-in MOS tube thereof, which can solve the problem in the prior art that the requirements of the adaptive flyback converter for the MOS tube turn-off speed under high input voltage and low input voltage are different, and can also solve the problem in the prior art that R&D personnel cannot debug the switching speed of the internal MOS tube according to actual needs.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] In a first aspect, the present invention provides a method for controlling the driving speed of a built-in MOS tube of a control chip, comprising the following steps: the control chip is provided with a programmable current input pin, the programmable current input pin is connected to the input voltage of a flyback converter through a resistor, and the current value input to the programmable current input pin is controlled by adjusting the resistance value of the resistor, wherein the current value increases as the input voltage of the flyback converter increases, and decreases as the input voltage decreases; the control chip has a built-in MOS tube, and the on and off speed of the built-in MOS tube is controlled by controlling the current of the programmable current input pin; a programmable drive current generating circuit senses the current value of the programmable current input pin, and outputs a programmable on drive current and a programmable off drive current from its two output ports to a controllable drive circuit of the control chip, and when the current of the programmable current input pin increases, the programmable on drive current and the programmable off drive current decrease, and the controllable drive circuit controls the on and off speed of the built-in power MOS to slow down, and when the current of the programmable current input pin increases, the programmable on drive current and the programmable off drive current decrease, and the controllable drive circuit controls the on and off speed of the built-in power MOS to slow down. When the current decreases, the programmable turn-on drive current and the programmable turn-off drive current increase, and the controllable drive circuit controls the turn-on and turn-off speeds of the built-in power MOS tube to accelerate. The built-in MOS tube drive speed control method is applied to a control chip, and the control chip includes a differential amplifier, a comparator, a frequency control circuit, an RS trigger and a proportional amplifier; a current sampling resistor is connected in series between the source and the ground of the built-in MOS tube; the negative input end of the differential amplifier receives a signal reflecting the output voltage of the external flyback converter, and performs differential amplification with the reference voltage of its positive input end to generate a pulse width modulation voltage; the pulse width modulation voltage is used as an input signal of the frequency control circuit to adjust the operating frequency according to the load condition of the flyback converter, and the pulse width modulation voltage is also used as a positive input signal of the comparator, and is compared with the voltage signal at both ends of the current sampling resistor sampled by the proportional amplifier to generate a turn-off timing of the built-in MOS tube; the RS trigger receives the turn-on timing provided by the frequency control circuit and the turn-off timing generated by the comparator, generates a switch timing of the built-in MOS tube, and provides it to the controllable drive circuit.

[0009] Furthermore, the programmable current input pin is an independent pin that is set separately, or is the same pin as other functional pins of the control chip.

[0010] Furthermore, the built-in MOS tube refers to a single-chip integration method in which the MOS tube and the control circuit of the control chip are integrated on the same wafer, or refers to a multi-chip packaging method in which separate MOS tube grains and control circuit grains are sealed together.

[0011] In a second aspect, the present invention provides a control chip for implementing the above-mentioned built-in MOS tube driving speed control method. The first solution thereof includes a differential amplifier, a comparator, a proportional amplifier, a MOS tube NM0, a current sampling resistor, a frequency control circuit and an RS trigger, and also includes a programmable driving current generating circuit and a controllable driving circuit; the negative input terminal of the differential amplifier is connected to the output voltage feedback pin of the control chip, and the positive input terminal of the differential amplifier is input with a reference voltage V ref , the output end of the differential amplifier is connected to the positive input end of the comparator and the input end of the frequency control circuit; the output end of the frequency control circuit is connected to one input end of the RS trigger, and the output end of the comparator is connected to the other input end of the RS trigger; the output end of the RS trigger is connected to the second input port of the controllable drive circuit; the drain of the MOS tube NM0 is connected to the MOS tube drain pin of the control chip, the source of the MOS tube NM0 is connected to the positive input end of the proportional amplifier, and the gate of the MOS tube NM0 is connected to the fourth port of the controllable drive circuit; the negative input end of the proportional amplifier is grounded; the current sampling A resistor is connected between the positive input terminal and the negative input terminal of the proportional amplifier; the output terminal of the proportional amplifier is connected to the negative input terminal of the comparator; the first port of the programmable drive current generating circuit is connected to the programmable current input pin of the control chip, the third port of the programmable drive current generating circuit is connected to the first port of the controllable drive circuit, and the fourth port of the programmable drive current generating circuit is connected to the sixth port of the controllable drive circuit; the fifth port of the programmable drive current generating circuit and the fifth port of the controllable drive circuit are connected to the power supply voltage, and the second port of the programmable drive current generating circuit and the third port of the controllable drive circuit are grounded.

[0012] The second solution of the control chip, based on the first solution, further includes a hysteresis comparator and a MOS transistor PM0; the source of the MOS transistor PM0 is connected to the programmable current input pin and the negative input port of the hysteresis comparator, and the gate of the MOS transistor PM0 is connected to the high positive input port of the hysteresis comparator and the reference voltage V H The drain of the MOS tube PM0 is connected to the first port of the programmable drive current generating circuit; the low positive input port of the hysteresis comparator is connected to the reference voltage V L connect.

[0013] Further, the programmable drive current generating circuit includes MOS tube NM1, MOS tube NM2, MOS tube NM3, MOS tube NM4, MOS tube NM5, MOS tube PM1, MOS tube PM2 and resistor R1; the drain and gate of the MOS tube NM1 and the gate of the MOS tube NM2 are connected to the first port of the programmable drive current generating circuit; the drain of the MOS tube NM2 is respectively connected to the drain and gate of the MOS tube NM3, the gate of the MOS tube NM4, the gate of the NM5, and the second port of the resistor R1; the drain and gate of the MOS tube PM1 are connected to the drain and gate of the MOS tube NM4, the gate of the MOS tube ... gate of the MOS tube NM5. The gate of the MOS tube PM2 is connected; the first port of the resistor R1 is connected to the source of the MOS tube PM1, the source of the MOS tube PM2, and the fifth port of the programmable drive current generating circuit; the source of the MOS tube NM1, the source of the MOS tube NM2, the source of the MOS tube NM3, the source of the MOS tube NM4, and the source of the MOS tube NM5 are connected to the second port of the programmable drive current generating circuit; the drain of the MOS tube PM2 is connected to the fourth port of the programmable drive current generating circuit; the drain of the MOS tube NM5 is connected to the third port of the programmable drive current generating circuit.

[0014] Further, the controllable drive circuit includes MOS tube NM11, MOS tube NM12, MOS tube NM13, MOS tube NM14, MOS tube NM15, MOS tube PM11, MOS tube PM12, MOS tube PM13, MOS tube PM14, MOS tube PM15, resistor R2 and resistor R3; the gate of the MOS tube NM11 and the gate of the MOS tube PM11 are connected to the second port of the controllable drive circuit; the drain of the MOS tube NM11 is respectively connected to the drain of the MOS tube PM11, the gate of the MOS tube NM12, and the gate of the MOS tube PM12; the drain of the MOS tube NM12 is respectively connected to the drain of the MOS tube PM12, the gate of the MOS tube NM13, and the gate of the MOS tube PM13; the drain of the MOS tube NM13 is respectively connected to the drain of the MOS tube PM13, the gate of the MOS tube NM14, the gate of the MOS tube PM14, and the gate of the MOS tube NM15 , the gate of the MOS tube PM15 is connected; the drain of the MOS tube PM14 is connected to the first port of the resistor R3; the drain of the MOS tube NM14 is connected to the second port of the resistor R2; the second port of the resistor R3, the first port of the resistor R2, the drain of the MOS tube NM15, and the drain of the MOS tube PM15 are respectively connected to the fourth port of the controllable drive circuit; the source of the MOS tube NM15 is connected to the first port of the controllable drive circuit; the source of the MOS tube PM15 is connected to the sixth port of the controllable drive circuit; the source of the MOS tube NM11, the source of the MOS tube NM12, the source of the MOS tube NM13, and the source of the MOS tube NM14 are respectively connected to the third port of the controllable drive circuit; the source of the MOS tube PM11, the source of the MOS tube PM12, the source of the MOS tube PM13, and the source of the MOS tube PM14 are respectively connected to the fifth port of the controllable drive circuit.

[0015] Furthermore, the reference voltage V H is greater than the reference voltage V L .

[0016] In a third aspect, the present invention provides a flyback converter, comprising the control chip of the first solution described above.

[0017] Furthermore, the flyback converter further includes a capacitor C IN , resistor R in , clamping absorption circuit, transformer, diode D OUT , capacitor C OUT , resistor R FB1 and resistor R FB2 , the capacitor CIN One end is connected to the input voltage V IN , the other end is grounded; the resistor R in One end of the transformer primary winding is connected to the input voltage V IN , the resistor R in The other end of the transformer is connected to the programmable current input pin of the control chip; the same-name end of the primary winding of the transformer is connected to the drain pin of the MOS tube of the control chip; the clamping absorption circuit is connected between the same-name end and the opposite-name end of the primary winding of the transformer; the same-name end of the auxiliary winding of the transformer is connected to the resistor R FB2 One end of the resistor R FB2 The other end and the resistor R FB1 One end of the resistor R is connected to the output voltage feedback pin of the control chip; FB1 The other end of the transformer secondary winding is connected to the diode D OUT The positive terminal of the diode D OUT The negative output voltage V OUT +, the output voltage of the opposite end of the secondary winding of the transformer V OUT -, the capacitor C OUT Connect the diode D OUT Between the negative pole and the opposite end of the secondary winding of the transformer.

[0018] In a fourth aspect, the present invention provides a flyback converter, comprising the control chip of the second solution described above.

[0019] Furthermore, the flyback converter further includes a capacitor C IN , resistor R in , clamping absorption circuit, transformer, diode D OUT , capacitor C OUT , resistor R FB1 , resistor R FB2 and resistor R UNP , the capacitor C IN One end is connected to the flyback converter input voltage V IN , the other end is grounded; the resistor R in One end of the transformer primary winding is connected to the input voltage V IN , the resistor R in The other end and the resistor R UVP The first port is connected to the programmable current input pin of the control chip; the resistor R UVPThe second port of is grounded; the same-name end of the primary winding of the transformer is connected to the drain pin of the MOS tube of the control chip; the clamping absorption circuit is connected between the same-name end and the opposite-name end of the primary winding of the transformer; the same-name end of the auxiliary winding of the transformer is connected to the resistor R FB2 One end of the resistor R FB2 The other end and the resistor R FB1 One end of the resistor R is connected to the output voltage feedback pin of the control chip; FB1 The other end of the transformer secondary winding is connected to the diode D OUT The positive terminal of the diode D OUT The negative output voltage V OUT +, the output voltage of the opposite end of the secondary winding of the transformer V OUT -, the capacitor C OUT Connect the diode D OUT Between the negative pole and the opposite end of the secondary winding of the transformer.

[0020] The built-in MOS tube drive speed adaptive control chip and flyback converter of the present invention suppress the peak voltage generated by the transformer in the flyback converter at the drain of the MOS tube and the voltage stress of the output diode when the high voltage input is applied, thereby reducing the risk of damage thereof, while not affecting or even improving the overall efficiency of the flyback converter. When the voltage input is low, the switching loss is reduced and the overall efficiency is increased. The switching speed of the MOS tube adapts to the change of the input voltage and meets the required indicators under different input voltages. The R&D personnel can adjust the resistance outside the control chip and design the switching speed of the power tube according to the requirements, which has universal applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is the control chip of the first and second generation external MOS tube in the prior art and its PSR feedback application diagram;

[0022] Figure 2 It is the control chip of the first and second generation external MOS tube and its SSR feedback application diagram in the prior art;

[0023] Figure 3 This is a control chip of the third generation built-in MOS tube in the prior art and its PSR feedback application diagram;

[0024] Figure 4 This is a diagram of the built-in MOS tube control chip and its PSR feedback application proposed by the present invention;

[0025] Figure 5 A specific implementation circuit diagram of a programmable drive current generating circuit is provided for the present invention;

[0026] Figure 6A specific implementation circuit diagram of the controllable driving circuit proposed by the present invention;

[0027] Figure 7 The present invention proposes a control chip for multiplexing functional pins and a PSR feedback application diagram thereof. DETAILED DESCRIPTION

[0028] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0029] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0030] Embodiment 1

[0031] The method for controlling the driving speed of a built-in MOS tube of a control chip of the present invention comprises the following steps: the control chip is provided with a programmable current input pin, the programmable current input pin is connected to the input voltage of a flyback converter via a resistor, the current value input to the programmable current input pin is controlled by adjusting the resistance value of the resistor, the current value of the programmable current input pin increases as the input voltage of the flyback converter increases, and decreases as the input voltage decreases; the control chip has a built-in MOS tube, and the on and off speed of the built-in MOS tube is controlled by controlling the current of the programmable current input pin; when the current of the programmable current input pin increases, the on and off speed of the built-in power MOS slows down, and when the current of the programmable current input pin decreases, the on and off speed of the built-in power MOS tube speeds up.

[0032] The programmable current input pin is an independent pin that is set separately, or is multiplexed with other pins of the control chip.

[0033] The built-in MOS tube refers to a single-chip integration method in which the MOS tube and the control circuit of the control chip are integrated on the same wafer, or refers to a multi-chip packaging method in which separate MOS tube crystals and control circuit crystals are sealed together.

[0034] In order to better illustrate the built-in MOS tube driving speed control method of the present invention, this embodiment provides a control chip. It should be noted that the control chip that implements the built-in MOS tube driving speed control method of the present invention is not limited to the circuit structure specified in this embodiment. Any control chip that slightly modifies the circuit structure on the basis of the built-in MOS tube driving speed control method of the present invention and can achieve the purpose of the present invention falls within the protection scope of the present invention.

[0035] A control chip with built-in MOS tube drive speed adaptation, such as Figure 4 As shown, it includes the basic functional modules of a voltage-stabilized power supply control chip: differential amplifier EA, comparator, proportional amplifier, power MOS tube NM0, current sampling resistor R sense , frequency control circuit and RS trigger, and also includes a programmable drive current generating circuit 100 and a controllable drive circuit 200 unique to the present invention. The programmable drive current generating circuit 100 at least includes a first port 101, a second port 102, a third port 103, a fourth port 104, and a fifth port 105, and the second port 102 and the fifth port 105 are respectively the negative power input and the positive power input of the programmable drive current generating circuit. The controllable drive circuit 200 at least includes a first port 201, a second port 202, a third port 203, a fourth port 204, a fifth port 205 and a sixth port 206, and the third port 203 and the fifth port 205 are respectively the negative power input and the positive power input of the controllable drive circuit. The control chip at least includes an output voltage feedback pin FB, a programmable current input pin RIN and a MOS tube drain pin DRN. The negative input terminal of the differential amplifier EA is connected to the output voltage feedback pin FB, and the positive input terminal of the differential amplifier EA is input with a reference voltage V ref , the output of the differential amplifier EA is connected to the positive input of the comparator and the input of the frequency control circuit. The output of the frequency control circuit is connected to one input of the RS trigger, and the output of the comparator is connected to the other input of the RS trigger. The output of the RS trigger is connected to the second input port 202 of the controllable drive circuit. The drain of the MOS tube NM0 is connected to the MOS tube drain pin DRN, the source is connected to the positive input of the proportional amplifier, and the gate is connected to the fourth port 204 of the controllable drive circuit. The negative input of the proportional amplifier is grounded. The current sampling resistor R senseConnected between the positive input terminal and the negative input terminal of the proportional amplifier. The output terminal of the proportional amplifier is connected to the negative input terminal of the comparator. The first port 101 of the programmable drive current generating circuit is connected to the programmable current input pin RIN, the third port 103 of the programmable drive current generating circuit is connected to the first port 201 of the controllable drive circuit, and the fourth port 104 of the programmable drive current generating circuit is connected to the sixth port 206 of the controllable drive circuit. The fifth port 105 of the programmable drive current generating circuit and the fifth port 205 of the controllable drive circuit are connected to the power supply voltage VCC, and the second port 102 of the programmable drive current generating circuit and the third port 203 of the controllable drive circuit are grounded.

[0036] Figure 4 The working principle of the control chip shown is as follows: the negative input terminal of the differential amplifier EA receives the output voltage V of the flyback converter through the output voltage feedback pin FB. OUT The signal is connected to the reference voltage V ref Differential amplification is performed to generate a pulse width modulated voltage V C . Pulse width modulation voltage V c As the input signal of the frequency control circuit, the pulse width modulation voltage V c It also serves as the positive input signal of the comparator and the proportional amplifier from the current sampling resistor R sense The sampled voltage signal is compared to generate the NMO shutdown timing. The RS trigger receives the opening timing provided by the frequency control circuit and the NMO shutdown timing generated by the comparator, and generates the NM0 switch timing under their joint action, and provides it to the controllable drive circuit. The current detection port 101 (i.e., the first port 101) of the programmable drive current generating circuit 100 senses the current input pin RIN of the control chip that is the same as the flyback converter input voltage V IN The controllable drive circuit 200 is proportional to the programmable input current, and outputs a programmable turn-on drive current and a programmable turn-off drive current at ports 104 and 103 respectively. Both currents decrease as the programmable input current increases. Ports 105 and 102 are respectively the positive power input and the negative power input. Ports 201 and 206 of the controllable drive circuit 200 receive the programmable turn-off drive current and the programmable turn-on drive current from the programmable drive current generating circuit 100 respectively. Port 202 receives the NM0 switch timing output from the RS trigger, and turns on and off the MOS tube NM0 at the output port 204 according to the timing.

[0037] Figure 4 The flyback converter circuit diagram includes the control chip of the present embodiment, which includes a capacitor C in addition to the control chip of the present embodiment. IN , resistor R in, clamping absorption circuit, transformer, diode D OUT , capacitor C OUT , resistor R FB1 and resistor R FB2 , capacitor C IN is the input filter capacitor, one end of which is connected to the input voltage V of the flyback converter IN , the other end is grounded. in One end of the transformer primary winding N P The opposite end is connected to the input voltage V IN , resistor R in The other end is connected to the programmable current input pin RIN of the control chip. P The same-name end is connected to the MOS tube drain pin DRN of the control chip. The clamping absorption circuit is connected to the primary winding N of the transformer. P The transformer auxiliary winding N A Connect the same-name terminal of the resistor R FB2 One end of the resistor R FB2 The other end and resistor R FB1 One end of the resistor R is connected to the output voltage feedback pin FB of the control chip. FB1 The other end of the transformer secondary winding is connected to the diode D OUT The positive pole of diode D OUT The negative output voltage V OUT +, the output voltage V at the opposite end of the secondary winding of the transformer OUT -, capacitor C OUT Connect the diode D OUT Between the negative pole and the opposite end of the secondary winding of the transformer.

[0038] Pin RIN is connected through resistor R in Connect the flyback converter input voltage V IN , as the input voltage V IN The increase of in The programmable input current increases, the programmable turn-on drive current and the programmable turn-off drive current generated by port 104 and port 103 respectively decrease, so the turn-on and turn-off speeds of MOS tube NM0 slow down. When the flyback converter is at high voltage input, the voltage spike generated by the flyback transformer at the drain of NM0 and the output diode D OUT The voltage of MOS tube NM0 and output diode D OUT Although the reduction in switching speed increases the switching loss, the overall efficiency does not necessarily decrease because the input voltage of the flyback converter is high and the current is small, and the conduction loss becomes smaller. On the contrary, due to the output diode D OUTThe voltage stress of the flyback converter is suppressed, and a diode with lower withstand voltage can be selected, which has a lower internal resistance and improves the overall efficiency of the converter; when the flyback converter is at low voltage input, the increase in the switching speed of NMO reduces the switching loss and improves the energy transmission efficiency of the flyback converter. Although the increase in switching speed will increase the voltage spike generated by the flyback transformer at the drain of NMO and the output diode D OUT However, the input voltage of the flyback converter is low at this time, so it is not easy to damage the power tube NMO and the output diode D OUT By changing the external resistor R in The size of V IN Under the input voltage, different programmable turn-on drive currents and programmable turn-off drive currents are generated, so that NM0 has different switching speeds.

[0039] From the above principles, it can be seen that the beneficial effects of the power control chip provided by the present invention are: 1. When the flyback converter is at high voltage input, the peak voltage generated by the transformer at the drain of the power tube and the voltage stress of the output diode are suppressed, reducing the risk of damage, while not affecting or even improving the overall efficiency of the converter; when the input voltage is low, the switching loss is reduced and the overall efficiency is increased. In other words, the switching speed of the power tube adapts to the change of the input voltage and meets the required indicators under different input voltages. 2. Engineers can adjust the resistance outside the chip and design the switching speed of the power tube according to the requirements, which has universal applicability.

[0040] Furthermore, the programmable driving current generating circuit 100 of this embodiment is specifically implemented as follows: Figure 5As shown, it includes: N-type channel MOS transistor NM1, N-type channel MOS transistor NM2, N-type channel MOS transistor NM3, N-type channel MOS transistor NM4, N-type channel MOS transistor NM5, P-type channel MOS transistor PM1, P-type channel MOS transistor PM2 and resistor R1. The drain and gate of MOS transistor NM1 and the gate of MOS transistor NM2 are connected to the first port 101 of the programmable drive current generating circuit; the drain of MOS transistor NM2 is respectively connected to the drain and gate of MOS transistor NM3, the gate of MOS transistor NM4, the gate of NM5, and the second port of resistor R1. The drain and gate of MOS transistor PM1 are connected to the drain of MOS transistor NM4 and the gate of MOS transistor PM2. The first port of resistor R1 is connected to the source of MOS transistor PM1, the source of MOS transistor PM2, and the fifth port 105 of the programmable drive current generating circuit. The source of MOS transistor NM1, the source of MOS transistor NM2, the source of MOS transistor NM3, the source of MOS transistor NM4, and the source of MOS transistor NM5 are connected to the second port 102 of the programmable drive current generating circuit. The drain of MOS transistor PM2 is connected to the fourth port 104 of the programmable drive current generating circuit; the drain of MOS transistor NM5 is connected to the third port 103 of the programmable drive current generating circuit.

[0041] For the convenience of calculation, the width-to-length ratio of MOS tube NM1 and MOS tube NM2 is set to NM1:NM2=1:1, NM3:NM4:NM5=1:1:m, PM1:PM2=1:n. In order to save power consumption, the resistor R in The programmable current is at uA level, generally tens to more than one hundred microamperes, while the programmable on-drive current and programmable off-drive current provided by port 104 and port 103 are at the level of tens of mA, so the proportional coefficients m and n are hundreds to thousands of times.

[0042] It is easy to calculate:

[0043] ,when Time (1)

[0044] ， when Time (2)

[0045] ， when Time (3)

[0046] Where V THN It is the threshold voltage of the N-channel MOS tube, which is generally around 0.7V, depending on the semiconductor process used. GS1 and V GS3are the gate-source voltages of NM1 and NM3 respectively. By properly designing their width-to-length ratios in integrated circuit design, the gate-source voltage can be maintained at 0.7V~1.3V. From the above formula, it can be seen that when V IN ≥V IN0 When the current provided by the programmable drive current generating circuit is zero, the power tube works at the minimum switching speed; when V IN <V IN0 When the input voltage V IN The programmable drive current generating circuit provides a programmable turn-on drive current I PM2 and programmable shutdown drive current I NM5 As the switching speed of the power tube decreases gradually, the function of the programmable drive current generating circuit of the first embodiment of the present invention is realized.

[0047] Furthermore, the controllable driving circuit 200 of this embodiment is specifically implemented as follows Figure 6As shown, it includes N-type channel MOS transistor NM11, N-type channel MOS transistor NM12, N-type channel MOS transistor NM13, N-type channel MOS transistor NM14, N-type channel MOS transistor NM15, P-type channel MOS transistor PM11, P-type channel MOS transistor PM12, P-type channel MOS transistor PM13, P-type channel MOS transistor PM14, P-type channel MOS transistor PM15, driving resistor R2 and driving resistor R3. The gate of MOS transistor NM11 and the gate of MOS transistor PM11 are connected to the second port 202 of the controllable driving circuit. The drain of MOS transistor NM11 is respectively connected to the drain of MOS transistor PM11, the gate of MOS transistor NM12, and the gate of MOS transistor PM12. The drain of MOS transistor NM12 is respectively connected to the drain of MOS transistor PM12, the gate of MOS transistor NM13, and the gate of MOS transistor PM13. The drain of MOS transistor NM13 is connected to the drain of MOS transistor PM13, the gate of MOS transistor NM14, the gate of MOS transistor PM14, the gate of MOS transistor NM15, and the gate of MOS transistor PM15 respectively. The drain of MOS transistor PM14 is connected to the first port of driving resistor R3. The drain of MOS transistor NM14 is connected to the second port of driving resistor R2. The second port of driving resistor R3, the first port of driving resistor R2, the drain of MOS transistor NM15, and the drain of MOS transistor PM15 are respectively connected to the fourth port 204 of the controllable driving circuit. The source of the MOS transistor NM15 is connected to the first port 201 of the controllable drive circuit; the source of the MOS transistor PM15 is connected to the sixth port 206 of the controllable drive circuit; the source of the MOS transistor NM11, the source of the MOS transistor NM12, the source of the MOS transistor NM13, and the source of the MOS transistor NM14 are respectively connected to the third port 203 of the controllable drive circuit; the source of the MOS transistor PM11, the source of the MOS transistor PM12, the source of the MOS transistor PM13, and the source of the MOS transistor PM14 are respectively connected to the fifth port 205 of the controllable drive circuit.

[0048] The working principle of the controllable driving circuit is: MOS tube NM11 and MOS tube PM11 form a first-stage NOT gate, MOS tube NM12 and MOS tube PM12 form a second-stage NOT gate, MOS tube NM13 and MOS tube PM13 form a third-stage NOT gate, and the driving capabilities of these three-stage NOT gates are amplified step by step, with the purpose of amplifying the driving capabilities of the timing signal with weak driving capability received by port 202 step by step, so as to quickly drive the MOS tubes NM14, MOS tube NM15, MOS tube PM14, and MOS tube PM15 with larger areas. This is a driving method commonly used in CMOS technology. When the signal of port 202 changes from low level to high level, the gates of MOS transistors NM14, MOS transistor NM15, MOS transistor PM14 and MOS transistor PM15 change from high level to low level, MOS transistors NM14 and MOS transistor NM15 change to cut-off state, and MOS transistors PM14 and MOS transistor PM15 change to on state, then the current output from port 204 is the sum of the current of driving resistor R3 and the current received at port 206; conversely, when the signal of port 202 changes from high level to low level, the gates of MOS transistors NM14, MOS transistor NM15, MOS transistor PM14 and MOS transistor PM15 change from low level to high level, MOS transistors NM14 and MOS transistor NM15 change to on state, and MOS transistors PM14 and MOS transistor PM15 change to cut-off state, then the current drawn from port 204 is the sum of the current of driving resistor R2 and the current received at port 201. The current received by port 206 and port 201 is generated by the variable drive current generating circuit mentioned above, which is used to change the switching speed of MOS tube NM0. The principle has been described in detail above and will not be repeated here. The drive resistors R2 and R3 provide the minimum drive current, and ensure that the power tube is normally turned on and off when the variable drive current is zero.

[0049] Embodiment 2

[0050] The control chip of the present invention changes the driving speed by detecting the input voltage of the flyback converter and generating a driving current that varies with the input voltage. There are other functions in the flyback converter that also require detecting the input voltage, such as input undervoltage protection, input overvoltage protection, feedforward compensation function, etc. The driving speed adaptation function of the present invention can also reuse the same pin with the above functions, thereby reducing chip pins and peripheral devices.

[0051] like Figure 7 As shown in FIG. 1 , this is a pin multiplexing solution for the built-in power MOS tube drive speed adaptation function and the input undervoltage protection function proposed in the second embodiment. Figure 4In comparison, a hysteresis comparator 300 and a P-channel MOS transistor PM0 are added. The source of the MOS transistor PM0 is connected to the programmable current input pin RIN of the control chip and the negative input port of the hysteresis comparator, and the gate of the MOS transistor PM0 is connected to the high positive input port of the hysteresis comparator 300 and the reference voltage V H The drain of the MOS tube PM0 is connected to the first port 101 of the programmable drive current generating circuit 100; the low positive input port of the hysteresis comparator 300 is connected to the reference voltage V L Connection. Reference voltage V H Greater than the reference voltage V L The other connection relationships are the same as those in the first embodiment and will not be described in detail.

[0052] The input voltage of the flyback converter is V IN Through the external resistor R of the control chip in and resistor R UVP After voltage division, the RIN pin of the chip is connected, and the sampling voltage V RIN Size:

[0053] (4)

[0054] When V RIN Greater than the reference voltage V H When the comparator output UVP_L is high, it indicates that the flyback converter input voltage V IN There is no undervoltage, when V RIN Less than the reference voltage V L When the comparator output UVP_L is low, it indicates that the input voltage V IN It is undervoltage, and it is forbidden to open the MOS tube NM0. This is a commonly used input undervoltage protection function.

[0055] In order to ensure that the input undervoltage protection function is not affected, the V RIN Less than the reference V H Within the range, V RIN The above formula should be kept unchanged, so the first port 101 of the programmable drive current generating circuit 100 cannot absorb current. However, in order to realize the invention proposed by changing the resistor R in The size of the power MOS tube NM0 is used to change the switching speed, V RIN Greater than the reference voltage V H Finally, a programmable input current needs to be sensed. The role of the PMO is to meet both of these requirements:

[0056] 1. Voltage V at RIN pin RIN <V H +V THP (V THPWhen the threshold voltage of PMO is taken as the absolute value), the P-channel MOS tube PM0 is cut off, so it does not affect the input undervoltage protection function;

[0057] 2. Only when V RIN ≥V H +V THP PM0 will be turned on when PM0 is on. The programmable current entering the programmable drive current generating circuit 100 after passing through PM0 can be calculated as:

[0058] (5)

[0059] Where V SG0 is the voltage difference between the source and gate of the PMO. Combining formulas (4) and (5), it can be seen that by designing the resistor R in With R UVP The proportionality factor can be used to set V IN The voltage when entering undervoltage protection; by setting the resistor R in The size of the programmable current can be set, and thus the switching speed of the power MOS tube NM0 can be set. The input undervoltage protection function and the built-in MOS tube drive speed programmable and adaptive function are realized simultaneously through only one chip pin, and the parameters of the two functions can be designed by engineers according to requirements.

[0060] This embodiment provides a flyback converter, such as Figure 7 As shown, the flyback converter of the embodiment 2 includes the built-in MOS tube driving speed adaptive control chip. The difference between this embodiment and the embodiment 1 is that the peripheral circuit of the control chip adds a resistor R UNP , resistor R UVP The first port is connected to the programmable current input pin RIN of the control chip, and the resistor R UVP The second port is grounded.

[0061] The input voltage of the flyback converter is V IN Through the external resistor R of the control chip in and resistor R UVP After voltage division, it is connected to the RIN pin of the chip. The remaining connection relationship and working principle are the same as those in the first embodiment, and will not be repeated here.

[0062] The above is only for explaining the implementation mode of the present invention and is not intended to limit the present invention. For those skilled in the art, any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention without creative work should be included in the protection scope of the present invention.

Claims

1. A method for controlling the driving speed of a built-in MOS tube of a control chip, characterized in that: The invention comprises the following steps: the control chip is provided with a programmable current input pin, the programmable current input pin is connected to the input voltage of the flyback converter through a resistor, and the current value input to the programmable current input pin is controlled by adjusting the resistance value of the resistor, and the current value increases as the input voltage of the flyback converter increases, and decreases as the input voltage decreases; the control chip has a built-in MOS tube, and the on and off speed of the built-in MOS tube is controlled by controlling the current of the programmable current input pin; the programmable drive current generating circuit senses the current value of the programmable current input pin, and outputs a programmable on drive current and a programmable off drive current from its two output ports to a controllable drive circuit of the control chip, when the current of the programmable current input pin increases, the programmable on drive current and the programmable off drive current decrease, and the controllable drive circuit controls the on and off speed of the built-in power MOS to slow down, and when the current of the programmable current input pin decreases, the programmable on drive current and the programmable off drive current increase, and the controllable drive circuit controls the on and off speed of the built-in power MOS to speed up; The control chip comprises a differential amplifier, a comparator, a frequency control circuit, an RS trigger and a proportional amplifier; a current sampling resistor is connected in series between the source of the built-in MOS tube and the ground; the negative input end of the differential amplifier receives a signal reflecting the output voltage of the external flyback converter, and performs differential amplification with the reference voltage of its positive input end to generate a pulse width modulation voltage; the pulse width modulation voltage is used as an input signal of the frequency control circuit to adjust the working frequency according to the load condition of the flyback converter, and the pulse width modulation voltage is also used as a positive input signal of the comparator, and is compared with the voltage signal at both ends of the current sampling resistor sampled by the proportional amplifier to generate a shutdown timing of the built-in MOS tube; the RS trigger receives the opening timing provided by the frequency control circuit and the closing timing generated by the comparator, generates a switching timing of the built-in MOS tube, and provides it to a controllable drive circuit.

2. The method for controlling the driving speed of the built-in MOS tube of the control chip according to claim 1, characterized in that: The programmable current input pin is an independent pin that is set separately, or is the same pin as other functional pins of the control chip.

3. The method for controlling the driving speed of the built-in MOS tube of the control chip according to claim 1, characterized in that: The built-in MOS tube refers to a single-chip integration method in which the MOS tube and the control circuit of the control chip are integrated on the same wafer, or refers to a multi-chip packaging method in which separate MOS tube crystals and control circuit crystals are sealed together.

4. A control chip, characterized in that: The method for controlling the driving speed of a built-in MOS tube according to any one of claims 1 to 3 comprises a differential amplifier, a comparator, a proportional amplifier, a MOS tube NM0, a current sampling resistor, a frequency control circuit and an RS trigger, and also comprises a programmable driving current generating circuit and a controllable driving circuit; the negative input terminal of the differential amplifier is connected to the output voltage feedback pin of the control chip, and the positive input terminal of the differential amplifier is input with a reference voltage V ref , the output end of the differential amplifier is connected to the positive input end of the comparator and the input end of the frequency control circuit; the output end of the frequency control circuit is connected to one input end of the RS trigger, and the output end of the comparator is connected to the other input end of the RS trigger; the output end of the RS trigger is connected to the second input port of the controllable drive circuit; the drain of the MOS tube NM0 is connected to the MOS tube drain pin of the control chip, the source of the MOS tube NM0 is connected to the positive input end of the proportional amplifier, and the gate of the MOS tube NM0 is connected to the fourth port of the controllable drive circuit; the negative input end of the proportional amplifier is grounded; the current sampling resistor is connected between the positive input end and the negative input end of the proportional amplifier; the output end of the proportional amplifier is connected to the negative input end of the comparator; the first port of the programmable drive current generating circuit is connected to the programmable current input pin of the control chip, the third port of the programmable drive current generating circuit is connected to the first port of the controllable drive circuit, and the fourth port of the programmable drive current generating circuit is connected to the sixth port of the controllable drive circuit; The fifth port of the programmable drive current generating circuit and the fifth port of the controllable drive circuit are connected to the supply voltage, and the second port of the programmable drive current generating circuit and the third port of the controllable drive circuit are grounded.

5. The control chip according to claim 4, characterized in that: It also includes a hysteresis comparator and a MOS transistor PM0; the source of the MOS transistor PM0 is connected to the programmable current input pin and the negative input port of the hysteresis comparator, and the gate of the MOS transistor PM0 is connected to the high positive input port of the hysteresis comparator and the reference voltage V H The drain of the MOS tube PM0 is connected to the first port of the programmable drive current generating circuit; the low positive input port of the hysteresis comparator is connected to the reference voltage V L connect.

6. The control chip according to claim 4 or 5, characterized in that: The programmable drive current generating circuit comprises a MOS tube NM1, a MOS tube NM2, a MOS tube NM3, a MOS tube NM4, a MOS tube NM5, a MOS tube PM1, a MOS tube PM2 and a resistor R1; the drain and the gate of the MOS tube NM1 and the gate of the MOS tube NM2 are connected to the first port of the programmable drive current generating circuit; the drain of the MOS tube NM2 is respectively connected to the drain and the gate of the MOS tube NM3, the gate of the MOS tube NM4, the gate of the NM5 and the second port of the resistor R1; the drain and the gate of the MOS tube PM1 are respectively connected to the drain and the gate of the MOS tube NM4, the gate of the M The gate of the MOS tube PM2 is connected; the first port of the resistor R1 is connected to the source of the MOS tube PM1, the source of the MOS tube PM2, and the fifth port of the programmable drive current generating circuit; the source of the MOS tube NM1, the source of the MOS tube NM2, the source of the MOS tube NM3, the source of the MOS tube NM4, and the source of the MOS tube NM5 are connected to the second port of the programmable drive current generating circuit; the drain of the MOS tube PM2 is connected to the fourth port of the programmable drive current generating circuit; the drain of the MOS tube NM5 is connected to the third port of the programmable drive current generating circuit.

7. The control chip according to claim 4 or 5, characterized in that: The controllable driving circuit includes MOS tube NM11, MOS tube NM12, MOS tube NM13, MOS tube NM14, MOS tube NM15, MOS tube PM11, MOS tube PM12, MOS tube PM13, MOS tube PM14, MOS tube PM15, resistor R2 and resistor R3; the gate of the MOS tube NM11 and the gate of the MOS tube PM11 are connected to the second port of the controllable driving circuit; the drain of the MOS tube NM11 is respectively connected to the drain of the MOS tube PM11, the gate of the MOS tube NM12 and the gate of the MOS tube PM12; the drain of the MOS tube NM12 is respectively connected to the drain of the MOS tube PM12, the gate of the MOS tube NM13 and the gate of the MOS tube PM13; the drain of the MOS tube NM13 is respectively connected to the drain of the MOS tube PM13, the gate of the MOS tube NM14, the gate of the MOS tube PM14, the gate of the MOS tube NM15, the gate of the The gate of the MOS tube PM15 is connected; the drain of the MOS tube PM14 is connected to the first port of the resistor R3; the drain of the MOS tube NM14 is connected to the second port of the resistor R2; the second port of the resistor R3, the first port of the resistor R2, the drain of the MOS tube NM15, and the drain of the MOS tube PM15 are respectively connected to the fourth port of the controllable drive circuit; the source of the MOS tube NM15 is connected to the first port of the controllable drive circuit; the source of the MOS tube PM15 is connected to the sixth port of the controllable drive circuit; the source of the MOS tube NM11, the source of the MOS tube NM12, the source of the MOS tube NM13, and the source of the MOS tube NM14 are respectively connected to the third port of the controllable drive circuit; the source of the MOS tube PM11, the source of the MOS tube PM12, the source of the MOS tube PM13, and the source of the MOS tube PM14 are respectively connected to the fifth port of the controllable drive circuit.

8. The control chip according to claim 5, characterized in that: The reference voltage V H is greater than the reference voltage V L .

9. A flyback converter, characterized in that: Comprising the control chip described in claim 4, 6 or 7.

10. A flyback converter, characterized in that: Comprising the control chip according to any one of claims 5 to 7.

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