9-2 Line Positive and Negative Three-Valued Encoder Circuit Based on Memristor Basic Logic Gates

Abstract

The present invention discloses a 9-2 line positive and negative ternary encoder circuit based on memristor basic logic gates. The present invention includes a negative ternary 9-2 line encoder and a positive ternary 9-2 line encoder. The negative ternary encoder includes four ternary minimum gates (TMIN), two standard ternary inverters (STI), two negative polarity ternary inverters (NTI), and two ternary AND gates. The positive ternary encoder includes four ternary maximum gates (TMAN), two standard ternary inverters (STI), two positive polarity ternary inverters (PTI), and two ternary OR gates. The circuit model structure of the present invention is clear and simple, and is easy to implement, which is of great significance to the application research in many fields such as the design of multi-valued digital logic circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and relates to an unbalanced ternary digital logic circuit structure, specifically to the design and implementation of a physically realizable 9-2 line positive and negative ternary encoder circuit based on memristor basic logic gates. Background Art

[0002] Traditional digital circuit design widely uses binary logic. However, due to problems such as small single-line information capacity and increased wiring, binary logic can no longer meet the design requirements of some circuits. Multivalued logic (MVL) that can meet this requirement has become very powerful in modern very large scale integrated circuit (VLSI) applications. Among various types of MVL, ternary logic has received more attention than other logics due to advantages such as less estimated interconnection cost and simple circuit implementation.

[0003] In the design schemes of ternary logic circuits, many design schemes have been proposed based on different technologies. For example, MOSFETs, CNTFETs and other process technologies are used to design ternary logic circuits. Ternary logic requires more gates in circuit design. A large number of ternary logic circuits use conventional CMOS technology, which has a complex circuit structure and high power consumption. As a nanodevice, memristor has the characteristics of small volume, low power consumption, easy integration and compatibility with traditional CMOS technology. Currently, memristors are widely used in logic circuit design. In addition, the compatibility of memristors with CMOS technology provides a new direction for the development of ternary logic circuits.

[0004] Ternary logic can be divided into two types: balanced ternary and unbalanced ternary. Unbalanced ternary is specifically divided into positive ternary {0, 1, 2} and negative ternary {0, -1, -2}. Corresponding to traditional binary logic, positive ternary was first proposed and widely used in ternary logic. In subsequent research and development, related negative ternary digital logic circuit designs have been successively proposed. In digital logic systems, combinational logic circuits are particularly important. Some combinational logic circuits often appear in various complex digital logic circuits. To achieve more complex logic functions, basic combinational logic circuits are commonly used as the basis to establish more complex functional logic circuits, among which encoders have been widely used. Studying the design of ternary encoder circuits based on memristors is expected to further complete the design of more complex logic circuits, improve the information storage density of circuit systems, and play a certain role in promoting the further development of modern information circuits. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the present invention proposes a 9-2 line positive and negative ternary encoder circuit based on memristor basic logic gates.

[0006] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0007] The present invention includes a negative ternary 9-2 line encoder and a positive ternary 9-2 line encoder. The negative ternary encoder includes four ternary minimum gates (TMIN), two standard ternary inverters (STI), two negative polarity ternary inverters (NTI), and two ternary AND gates. The positive ternary encoder includes four ternary maximum gates (TMAN), two standard ternary inverters (STI), two positive polarity ternary inverters (PTI), and two ternary OR gates.

[0008] The standard ternary inverter (STI) is composed of two memristors and two MOS transistors. Both the negative polarity ternary inverter (NTI) and the positive polarity ternary inverter (PTI) are composed of one memristor and one MOS transistor, and the difference lies in the different threshold voltages of the MOS transistors. The negative ternary inverter uses a PMOS transistor, and the positive ternary inverter uses an NMOS transistor. For the negative ternary inverter, when the input is logic -2, the STI and NTI output logic 0; when the input is logic -1, the STI and NTI output logic -1 and logic -2 respectively; when the input is logic 0, the STI and NTI output logic -2 respectively.

[0009] Each ternary minimum gate and ternary maximum gate is composed of three memristors, and its function is to find the logical minimum and maximum of three input terminals, and the difference lies in the different connection directions of the memristors.

[0010] Both the two-input ternary AND gate and the ternary OR gate are composed of two memristors. The function of the AND gate is to find the minimum of two inputs, and the function of the OR gate is to find the maximum of two inputs.

[0011] Taking the negative ternary encoder circuit of the present invention as an example, the positive ternary encoder circuit only needs to replace the relevant logic gate circuits, and its circuit structure is exactly the same as that of the negative ternary encoder circuit. The positive ternary encoder circuit will not be given in detail in the present invention.

[0012] The beneficial effects of the present invention are as follows: The 9-2 line positive and negative ternary encoder circuit based on the basic logic gates of memristors has a clear and simple circuit model structure and is easy to implement, which has important significance for the application research in many fields such as the design of multi-valued digital logic circuits. Description of the Drawings

[0013] Figure 1 It is a block diagram of the 9-2 line negative ternary encoder circuit based on the basic logic gates of memristors of the present invention.

[0014] Figure 2 It is a schematic diagram of the 9-2 line negative ternary encoder circuit based on the basic logic gates of memristors of the present invention. Detailed Embodiment

[0015] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] The 9-2 line positive and negative ternary encoder circuit model based on the memristor basic logic gate designed by the present invention, and its negative ternary 9-2 line encoder circuit block diagram is as Figure 1 shown, which is composed of five TMINs, two STIs, two NTI and two ternary AND gates, and is realized by using the resistance switching characteristic and memory characteristic of the memristor.

[0017] The logical state in the 9-2 line ternary encoder circuit is the voltage value, where the voltage -V DD is defined as -3.3V, corresponding to the logic "-2"; -V DD / 2 is -1.65V, corresponding to the logic "-1"; GND is 0V, corresponding to the logic "0";.

[0018] The truth table of the 9-2 line negative ternary encoder designed by the present invention is shown in the following table:

[0019]

[0020] According to the truth table of the 9-2 line negative ternary encoder, it can be seen that different combinations of input signals "-1" and "0" can make the corresponding output terminals be logic "-2", "-1" and "0".

[0021] When the input X0 = -1 and the others are all logic 0, corresponding to Figure 1 the outputs of the ternary minimum gates U1, U2, U3, U4 in it are GND, that is, logic 0. Among them, the output logic values of U1 and U3 are output as S1 = 0, S3 = 0 through STI and NTI, and at the same time S2 = S4 = 0. Therefore, the outputs Y1 = 0, Y0 = 0 can be obtained through the ternary AND gate.

[0022] When the input X1 = -1 and the others are all logic 0, corresponding to Figure 1 the outputs of the ternary minimum gates U1, U2, U3 in it are GND, that is, logic 0; the output of U4 is -V DD / 2, that is, logic -1. Among them, the output logic values of U1 and U3 are output as S1 = 0, S3 = 0 through STI and NTI, and at the same time S2 = 0, S4 = -1. Therefore, the outputs Y1 = 0, Y0 = -1 can be obtained through a ternary AND gate.

[0023] When the input X2 = -1 and the others are all logic 0, corresponding to Figure 1 the outputs of the ternary minimum gates U1, U2, U4 in it are GND, that is, logic 0; the output of U3 is -V DD / 2, which is logic -1. Among them, the output logic value of U1 is output as S1 = 0 through STI and NTI, the output logic value of U3 is output as S3 = -2 through STI and NTI. At the same time, S2 = S4 = 0. Therefore, the output Y1 = 0 and Y0 = -2 can be obtained through a three-valued AND gate.

[0024] When the input X3 = -1 and the others are all logic 0, corresponding to Figure 1 In the three-valued minimum gate U1, U3, U4, the output is GND, that is, logic 0; the output of U2 is -V DD / 2, which is logic -1. Among them, the output logic values of U1 and U3 are output as S1 = 0 and S3 = 0 through STI and NTI. At the same time, S2 = -1 and S4 = 0. Therefore, the output Y1 = -1 and Y0 = 0 can be obtained through a three-valued AND gate.

[0025] When the input X4 = -1 and the others are all logic 0, corresponding to Figure 1 In the three-valued minimum gate U1, U3, the output is GND, that is, logic 0; the outputs of U2 and U4 are -V DD / 2, which is logic -1. Among them, the output logic values of U1 and U3 are output as S1 = 0 and S3 = 0 through STI and NTI. At the same time, S2 = -1 and S4 = -1. Therefore, the output Y1 = -1 and Y0 = -1 can be obtained through a three-valued AND gate.

[0026] When the input X5 = -1 and the others are all logic 0, corresponding to Figure 1 In the three-valued minimum gate U1, U4, the output is GND, that is, logic 0; the outputs of U2 and U3 are -V DD / 2, which is logic -1. Among them, the output logic value of U1 is output as S1 = 0 through STI and NTI, the output logic value of U3 is output as S3 = -2 through STI and NTI. At the same time, S2 = -1 and S4 = 0. Therefore, the output Y1 = -1 and Y0 = -2 can be obtained through a three-valued AND gate.

[0027] When the input X6 = -1 and the others are all logic 0, corresponding to Figure 1 In the three-valued minimum gate U2, U3, U4, the output is GND, that is, logic 0; the output of U1 is -V DD / 2, which is logic -1. Among them, the output logic value of U1 is output as S1 = -2 through STI and NTI, the output logic value of U3 is output as S3 = 0 through STI and NTI. At the same time, S2 = 0 and S4 = 0. Therefore, the output Y1 = -2 and Y0 = 0 can be obtained through a three-valued AND gate.

[0028] When the input X7 = -1 and the others are all logic 0, corresponding to Figure 1 In the three-valued minimum gate U2, U3, the output is GND, that is, logic 0; the outputs of U1 and U4 are -V DD / 2, i.e., logic -1. Among them, the output logic value of U1 is output as S1 = -2 through STI and NTI, the output logic value of U3 is output as S3 = 0 through STI and NTI, meanwhile S2 = 0, S4 = -1, so the output Y1 = -2 and Y0 = -1 can be obtained through a three - valued AND gate.

[0029] When the input X8 = -1 and the others are all logic 0, corresponding to Figure 1 in the three - valued minimum gate U1 and U3, the output is -V DD / 2, i.e., logic -1; the output of U2 and U4 is GND, i.e., logic 0. Among them, the output logic value of U1 is output as S1 = -2 through STI and NTI, the output logic value of U3 is output as S3 = -2 through STI and NTI, meanwhile S2 = 0, S4 = 0, so the output Y1 = -2 and Y0 = -2 can be obtained through a three - valued AND gate.

[0030] Similarly, for the positive three - valued 9 - 2 line encoder circuit, according to different combinations of input signals "0" and "1", the corresponding output terminals can be logic "0", "1" and "2", and its analysis process is the same as that of the negative three - valued.

[0031] When the input X0 = 1 and the others are all logic 0, the output Y1 = 0 and Y0 = 0 can be obtained.

[0032] When the input X1 = 1 and the others are all logic 0, the output Y1 = 0 and Y0 = 1 can be obtained.

[0033] When the input X2 = 1 and the others are all logic 0, the output Y1 = 0 and Y0 = 2 can be obtained.

[0034] When the input X3 = 1 and the others are all logic 0, the output Y1 = 1 and Y0 = 0 can be obtained.

[0035] When the input X4 = 1 and the others are all logic 0, the output Y1 = 1 and Y0 = 1 can be obtained.

[0036] When the input X5 = 1 and the others are all logic 0, the output Y1 = 1 and Y0 = 2 can be obtained.

[0037] When the input X6 = 1 and the others are all logic 0, the output Y1 = 2 and Y0 = 0 can be obtained.

[0038] When the input X7 = 1 and the others are all logic 0, the output Y1 = 2 and Y0 = 1 can be obtained.

[0039] When the input X8 = 1 and the others are all logic 0, the output Y1 = 2 and Y0 = 2 can be obtained.

[0040] According to the relationship between the input and output of the above - mentioned negative three - valued truth table, it can be constructed as Figure 1The detailed circuit structure of the 9-2 line negative ternary encoder circuit diagram shown is as follows: Figure 2 as shown.

[0041] For the 9-2 line negative ternary encoder circuit, the input terminal X8 is connected to the negative electrodes of the first memristor M1 and the seventh memristor M7; the input terminal X7 is connected to the negative electrodes of the second memristor M2 and the tenth memristor M 10 ; the input terminal X6 is connected to the negative electrode of the third memristor M3; the input terminal X5 is connected to the negative electrodes of the fourth memristor M4 and the eighth memristor M8; the input terminal X4 is connected to the negative electrodes of the fifth memristor M5 and the eleventh memristor M 11 ; the input terminal X3 is connected to the negative electrode of the sixth memristor M6; the input terminal X2 is connected to the negative electrode of the ninth memristor M9; the input terminal X1 is connected to the negative electrode of the twelfth memristor M 12 .

[0042] The positive electrodes of the first memristor M1, the second memristor M2, and the third memristor M3 are simultaneously connected to the gates of the first PMOS transistor P1 and the second PMOS transistor P2. The positive electrode of the thirteenth memristor M 13 is connected to the power supply -V DD , the negative electrode of the thirteenth memristor M 13 is connected to the drain of the first PMOS transistor P1 and the gate of the third PMOS transistor P3. The source of the first PMOS transistor P1 is connected to the positive electrode of the fourteenth memristor M 14 and the drain of the second PMOS transistor P2. The source of the second PMOS transistor P2 and the negative electrode of the fourteenth memristor M 14 are connected to GND. The positive electrode of the fifteenth memristor M 15 is connected to the power supply -V DD , the negative electrode of the fifteenth memristor M 15 is connected to the drain of the third PMOS transistor P3 and the negative electrode of the nineteenth memristor M 19 , and the source of the third PMOS transistor P3 is connected to GND.

[0043] The positive electrodes of the fourth memristor M4, the fifth memristor M5, and the sixth memristor M6 are connected to the negative electrode of the twentieth memristor M 20 . The positive electrodes of the nineteenth memristor M 19 and the twentieth memristor M 20 are connected to obtain the output terminal Y1.

[0044] The positive electrodes of the seventh memristor M7, the eighth memristor M8, and the ninth memristor M9 are simultaneously connected to the gates of the fourth PMOS transistor P4 and the fifth PMOS transistor P5. The positive electrode of the sixteenth memristor M 16 is connected to the power supply -V DD , the negative electrode of the sixteenth memristor M 16The negative electrode is connected to the drain of the fourth PMOS transistor P4 and the gate of the sixth PMOS transistor P6. The source of the fourth PMOS transistor P4 is connected to the positive electrode of the seventeenth memristor M 17 The positive electrode, the drain of the fifth PMOS transistor P5. The source of the fifth PMOS transistor P5 and the seventeenth memristor M 17 The negative electrode is connected to GND. The positive electrode of the eighteenth memristor M 18 Is connected to the power supply -V DD Connected. The negative electrode of the eighteenth memristor M 18 The negative electrode is connected to the drain of the sixth PMOS transistor P6 and the negative electrode of the twenty-first memristor M 21 Connected. The source of the sixth PMOS transistor P6 is connected to GND.

[0045] The tenth memristor M 10 , The eleventh memristor M 11 And the positive electrodes of the twelfth memristor M 12 Are connected to the negative electrode of the twenty-second memristor M 22 Connected. The positive electrodes of the twenty-first memristor M 21 And the twenty-second memristor M 22 Are connected to obtain the output terminal Y0.

[0046] For the 9-2 line positive ternary encoder circuit, replace Figure 1 The minimum value gate (TMIN) in the 9-2 line negative ternary encoder circuit U1, U2, U3 and U4 parts of with the maximum value gate (TMIN), replace the NTI gate with the PTI gate, and replace the ternary AND gate with the ternary OR gate. The connection method of the schematic diagram of its 9-2 line positive ternary encoder circuit is the same as that of the 9-2 line negative ternary encoder.

[0047] Those of ordinary skill in the art should recognize that the above embodiments are only used to verify the present invention, rather than as a limitation of the present invention. As long as it is within the scope of the present invention, changes and deformations of the above embodiments will fall within the protection scope of the present invention.

Claims

1. A 9-2 line positive and negative ternary encoder circuit based on a memristor basic logic gate, characterized in that It includes a negative ternary 9-2 line encoder and a positive ternary 9-2 line encoder. The negative ternary encoder includes four ternary minimum gates TMIN, two standard ternary inverters STI, two negative polarity ternary inverters NTI, and two ternary AND gates; the positive ternary encoder includes four ternary maximum gates TMAN, two standard ternary inverters STI, two positive polarity ternary inverters PTI, and two ternary OR gates; The standard ternary inverter STI is composed of two memristors and two MOS transistors. Both the negative polarity ternary inverter NTI and the positive polarity ternary inverter PTI are composed of one memristor and one MOS transistor. The negative ternary inverter uses PMOS transistors, and the positive ternary inverter uses NMOS transistors; for the negative ternary inverter, when the input is logic -2, the standard ternary inverter STI and the negative polarity ternary inverter NTI output logic 0; when the input is logic -1, the standard ternary inverter STI and the negative polarity ternary inverter NTI output logic -1 and logic -2 respectively; when the input is logic 0, the standard ternary inverter STI and the negative polarity ternary inverter NTI output logic -2 respectively; Each ternary minimum gate and ternary maximum gate is composed of three memristors, and its function is to find the logical minimum and maximum of three input terminals; Both the two-input ternary AND gate and the ternary OR gate are composed of two memristors. The function of the AND gate is to find the minimum of two inputs, and the function of the OR gate is to find the maximum of two inputs; The specific structure of the negative ternary encoder is as follows: The input terminal X8 is connected to the negative electrodes of the first memristor M1 and the seventh memristor M7; the input terminal X7 is connected to the negative electrodes of the second memristor M2 and the tenth memristor M 10 ; the input terminal X6 is connected to the negative electrode of the third memristor M3; the input terminal X5 is connected to the negative electrodes of the fourth memristor M4 and the eighth memristor M8; the input terminal X4 is connected to the negative electrodes of the fifth memristor M5 and the eleventh memristor M 11 ; the input terminal X3 is connected to the negative electrode of the sixth memristor M6; the input terminal X2 is connected to the negative electrode of the ninth memristor M9; the input terminal X1 is connected to the negative electrode of the twelfth memristor M 12 ; The positive electrodes of the first memristor M1, the second memristor M2, and the third memristor M3 are simultaneously connected to the gates of the first PMOS transistor P1 and the second PMOS transistor P2. The positive electrode of the thirteenth memristor M 13 is connected to the power supply -V DD The negative electrode of the thirteenth memristor M 13 is connected to the drain of the first PMOS transistor P1 and the gate of the third PMOS transistor P3. The source of the first PMOS transistor P1 is connected to the positive electrode of the fourteenth memristor M 14 and the drain of the second PMOS transistor P2. The source of the second PMOS transistor P2 and the negative electrode of the fourteenth memristor M 14 are connected to GND. The positive electrode of the fifteenth memristor M 15 is connected to the power supply -V DD The negative electrode of the fifteenth memristor M 15 is connected to the drain of the third PMOS transistor P3 and the negative electrode of the nineteenth memristor M 19 The source of the third PMOS transistor P3 is connected to GND; The positive electrodes of the fourth memristor M4, the fifth memristor M5, and the sixth memristor M6 are connected to the negative electrode of the twentieth memristor M 20 ; the nineteenth memristor M 19 is connected to the positive electrode of the twentieth memristor M 20 to obtain an output terminal Y1; The positive electrodes of the seventh memristor M7, the eighth memristor M8, and the ninth memristor M9 are simultaneously connected to the gates of the fourth PMOS transistor P4 and the fifth PMOS transistor P5. The positive electrode of the sixteenth memristor M 16 is connected to the power supply -V DD . The negative electrode of the sixteenth memristor M 16 is connected to the drain of the fourth PMOS transistor P4 and the gate of the sixth PMOS transistor P6. The source of the fourth PMOS transistor P4 is connected to the positive electrode of the seventeenth memristor M 17 and the drain of the fifth PMOS transistor P5. The source of the fifth PMOS transistor P5 and the negative electrode of the seventeenth memristor M 17 are connected to GND. The positive electrode of the eighteenth memristor M 18 is connected to the power supply -V DD . The negative electrode of the eighteenth memristor M 18 is connected to the drain of the sixth PMOS transistor P6 and the negative electrode of the twenty - first memristor M 21 . The source of the sixth PMOS transistor P6 is connected to GND; The tenth memristor M 10 , the eleventh memristor M 11 and the twelfth memristor M 12 have their positive electrodes connected to the negative electrode of the twenty-second memristor M 22 ; the positive electrodes of the twenty-first memristor M 21 and the twenty-second memristor M 22 are connected to obtain the output terminal Y0; The specific structure of the positive ternary encoder is as follows: replace the four ternary minimum gates TMIN in the negative ternary encoder circuit with ternary maximum gates TMAN, replace the negative polarity ternary inverter NTI with a positive polarity ternary inverter PTI, and replace the ternary AND gate with a ternary OR gate. Its connection method is the same as that of the negative ternary encoder.

Images