Filter device comprising two connected filter circuits

Abstract

A filter device having reduced sensitivity to manufacturing tolerances includes a multi-layered panel with integrated wiring, a piezoelectric substrate mounted to the panel. A first filter circuit (FC1) and a signal path (SP) including a second filter circuit are implemented on the substrate and connected to a common antenna terminal (AT) and a common node (CN) located on top of the piezoelectric substrate. A first matching circuit (MC1) and an additional matching circuit (MC2) are implemented by wiring in the multi-layered panel.

Description

TECHNICAL FIELD

[0001] The present invention relates to filter arrangements usable for mobile phone applications. According to a preferred embodiment, the filter arrangement comprises an ultra-wideband GPS extractor for 5G mobile phone applications. BACKGROUND

[0002] Modern filter arrangements comprise more than one filter circuit. Each filter circuit can be designed to filter out a desired frequency band and separate from signals having other frequencies. Preferably, as many filter circuits as possible are implemented on a common chip to save cost, shorten connection lines and improve insertion loss. Typically, these arrangements are named two-in-one, three-in-one or more highly integrated arrangements.

[0003] Examples of filter arrangements with two or more filter circuits connected together and to the same antenna are e.g. duplexers, multiplexers or extractors. Typically, at least one filter circuit needs to be matched to avoid problems when connecting these circuits to a common node to enable e.g. duplexing functionality. Further matching is needed to match both circuits to the antenna terminal.

[0004] Significant problems often occur at filter arrangements with two or more filter circuits connected, since it can prove unavoidable manufacturing tolerances to cause a too large spread in filter properties. It has been found that manufacturing tolerances can have a large impact on the values of the parasitic elements of the filter arrangement. One example is the parasitic inductance introduced by bump connections or other interconnection components at the arrangement. Small variations in e.g. the bump height can cause variations in its corresponding parasitic inductance, which in turn can cause undesired variations in filter performance.

[0005] A main problem when implementing a GPS extractor is to provide a wideband performance that is less sensitive to manufacturing tolerances, e.g. to the height of the solder bump connections between the carrier substrate and the filter chip.

[0006] It is therefore an object to improve the performance of filter arrangements by reducing their sensitivity to manufacturing tolerances. Another object is to provide an ultra-wideband GPS extractor for 5G mobile phone applications.

[0007] A main problem when implementing a GPS extractor is to provide a wideband performance that is less sensitive to manufacturing tolerances, e.g. to the height of the solder bump connections between the carrier substrate and the SAW chip. SUMMARY

[0008] This and other objects are achieved by a filter arrangement according to the invention. Advantageous further features and specific embodiments can be gathered from the following.

[0009] The filter arrangement comprises a carrier, for example a multi-layer panel with integrated wiring. A piezoelectric substrate is mounted onto the top surface of the panel. In a flip-chip arrangement, pads on the active surface side of the substrate are connected to corresponding contact areas on the panel.

[0010] On the substrate, a first filter circuit and a signal path are implemented and connected to a common node on the substrate surface. The common node is formed as a pad and is further connected to an antenna terminal on the panel. The signal path comprises at least a second filter circuit. The first filter circuit and the second filter circuit can be implemented in SAW technology.

[0011] A first matching circuit, which is circuit-connected between the common node and the signal path, is implemented by wiring in the multi-layer panel.

[0012] A key feature of the proposed filter arrangement is the implementation of the connection of the first filter circuit and the signal path. So far, it has been a design rule to place all wiring and all passive matching elements on a carrier, for example a multi-layer panel, and to connect the filter circuits to the panel in the shortest way, and now, the common node is placed on the substrate surface facing the panel. Since the first matching circuit, which is placed between the common node and the signal path, is implemented on the panel, the common node is first connected to a first end of the first matching circuit. A second end of the matching circuit is connected to a pad on the substrate surface via an interconnect. The pad connects the signal path on the substrate.

[0013] With such an arrangement, the sensitivity of the filter arrangement to manufacturing tolerances, which cause parasitic inductances, can be significantly reduced. Furthermore, the properties of the filter circuits, i.e. the position of the band edges, the insertion loss and the bandwidth, can be set more precisely.

[0014] Thus, the first matching circuit implemented by wiring in the multi-layer panel is circuit-connected as a series line between the signal path and the common node. A first section of the series line, which is arranged on the substrate, connects the common node and a first pad. A second section of the series line is arranged on the substrate and the second section of the series line connects a second pad and the signal path comprising the second filter circuit. A first interconnect connects the first pad to a first end of the first matching circuit and a second interconnect connects the second pad to a second end of the first matching circuit.

[0015] A second matching circuit can be circuit-connected between the antenna and the common node.

[0016] According to one embodiment, the at least one filter circuit comprises a SAW resonator.

[0017] The filter arrangement can be any of a diplexer, a multiplexer or an extractor.

[0018] According to one embodiment, the filter device is a diplexer, wherein the first filter circuit is a bandpass filter for GPS and / or GNSS signals. The signal path can then comprise one or more further filter circuits selected from a bandpass, a highpass, a lowpass, a bandstop, a duplexer or an antenna switch. Further, the filter device can be a front-end module with one or more antennas operating in multiple frequency bands. Switching components can be used to actively switch between different filter elements or other signal paths. The front-end module can connect the antennas to the required input or output terminals, i.e. Tx or Rx sections.

[0019] In a filter device comprising or being a diplexer, the first matching circuit is circuit-wise connected in series between the signal path and the common node and comprises a bandstop for GPS / GNSS frequencies.

[0020] Within the described diplexer, the signal path has a VWSR between 617 MHz and 4.2 GHz of less than 2, except for a region around the GPS / GNSS frequencies, which is blocked by the bandstop between the antenna and the common node.

[0021] In one variant, the filter device comprises a second matching circuit circuit-wise connected between the antenna terminal and the common node. The second matching circuit comprises a series coil to match the antenna with the first filter circuit and the signal path.

[0022] Each interconnect between any pad on the substrate and the corresponding contact area on the surface of the panel can comprise or be a bump.

[0023] It is advantageous to position the interconnects between the antenna terminal and the corresponding pads on the substrate close to the substrate corners.

[0024] The multilayer panel comprises one of a laminate, an HTCC and an LTCC. Structured metallized planes arranged between dielectric ceramic or laminate layers are electrically interconnected by vias and can form passive elements selected from resistors, capacitors and inductors. The matching circuits can be formed by appropriate circuit-wise connection of some of these integrated elements, such as the first and second matching circuits of the filter device. BRIEF DESCRIPTION OF DRAWINGS

[0025] The application will be explained in more detail below with reference to specific embodiments and to the attached drawings. The drawings are merely schematic and can not show all elements, as long as the skilled person can easily supplement them, as these omitted elements are known in the art. Moreover, the drawings are not drawn to scale and some details can be exaggerated for a better understanding.

[0026] Figure 1 A SAW filter device according to the prior art is shown in a schematic cross-section;

[0027] Figure 2 a schematic block diagram of a filter device according to the art is shown;

[0028] Figure 3 a schematic block diagram of a filter device according to the invention is shown;

[0029] Figure 4 an exemplary circuit of a multilayer panel and a piezoelectric substrate according to one embodiment of the invention is schematically shown;

[0030] Figure 5 the transfer curve between the antenna and the output terminal of a first filter circuit according to two embodiments of the invention is depicted in narrow band and a reference device according to the prior art, wherein the filter device is an extractor and the first filter circuit is a bandpass for GPS / GNSS;

[0031] Figure 6 the same transfer curve in wide band is shown;

[0032] Figure 7 the transfer curve between the antenna and the signal path in the same filter device is shown; Figure 5 and Figure 6 the transfer curve between the antenna and the signal path in the same filter device is shown;

[0033] Figure 8 the reflection curve between the antenna and the signal path in the same filter device is shown;

[0034] Figure 9 the transfer curve of the right band edge of Figure 6 the transfer curve of the right band edge of

[0035] Figure 10 the reflection curve between the antenna and the signal path of two different embodiments of the invention compared to the reference device is shown;

[0036] Figure 11 the influence of manufacturing tolerances on the transfer curve of the reference device is shown in the upper part of the figure for three different bump heights and in an enlarged sectional view in the lower part of the figure;

[0037] Figure 12 the influence of manufacturing tolerances on the transfer curve of the first embodiment of the filter device is shown in the upper part of the figure for three different bump heights and in an enlarged sectional view in the lower part of the figure;

[0038] Figure 13 the influence of manufacturing tolerances on the transfer curve of the improved second embodiment of the filter device is shown in the upper part of the figure for three different bump heights and in an enlarged sectional view in the lower part of the figure;

[0039] Figure 14A The influence of manufacturing tolerances on the reflection of the signal path of the reference device is shown in the upper part of the figure for three different bump heights and in the lower part of the figure in an enlarged cross-sectional view;

[0040] Figure 14B The influence of manufacturing tolerances on the reflection of the signal path of the first embodiment is shown in the upper part of the figure for three different bump heights and in the lower part of the figure in an enlarged cross-sectional view;

[0041] Figure 14C The influence of manufacturing tolerances on the reflection of the signal path of the improved second embodiment is shown in the upper part of the figure for three different bump heights and in the lower part of the figure in an enlarged cross-sectional view. DETAILED DESCRIPTION

[0042] Figure 1 A filter device according to the state of the art is shown in a schematic cross-section. The SAW filter circuit FC is realized on the surface of a piezoelectric substrate SU. The substrate is flip-chip mounted to the top surface of a multilayer panel MLP using bumps as interconnect components. Thus, pads on the bottom surface of the substrate are connected to contact areas on the top surface of the panel MLP. Wires are located on the panel surface and / or inside the panel. The wires consist of conductive lines, metallized areas and vias connecting different levels of the multilayer panel. The wires interconnect the contact areas on the top with terminal contacts at the bottom surface of the panel. At the same time, passive circuit elements are formed by the wires and connected to the filter circuit. The terminal contacts are used to connect the device to an external circuit device like a PCB.

[0043] Figure 2 A schematic block diagram of a filter device according to the state of the art is shown. The device represents a GPS / CELL extractor, where the signal path SP comprises a bandpass filter for the GPS band around 1585 MHz. The first filter circuit FC1 can pass all frequencies of the usual cell band except the GPS band.

[0044] According to the general design rules which have proven to be advantageous so far, the main filtering function of the signal path SP (CPS path) and the first filter circuit (cell) is realized as a SAW filter circuit within the substrate die SU, while all interconnects and matching circuits MC are realized inside the panel MLP, which is usually a laminate or LTCC.

[0045] In this figure, the two channels FC1, SP are connected together with a first common matching circuit MC1. A second matching circuit MC2 is arranged between the antenna AN and a common node CN to which both channels and the antenna are connected. At this common node CN, the connection line to the first filter circuit FC1 (cell path) can be very critical as it is very sensitive to form a large amount of parasitic inductance LP.

[0046] On the one hand, this parasitic inductance LP will typically cause a narrower passband and thus provide a worse nominal performance. On the other hand, variations in the inductance LP value due to manufacturing tolerances (bump height variations etc.) will cause typically deteriorating high performance variations.

[0047] The advantage of all interconnections inside the panel is that the connection lines in the laminate or LTCC typically have a larger line cross section and thus introduce less insertion loss.

[0048] The disadvantage of this known approach is an increased parasitic inductance which will cause a reduced passband and increased manufacturing tolerances.

[0049] Figure 2 The same block diagram is shown with the hypothetical minor difference that the common node CN which combines all paths is now arranged on the surface of the substrate SU. Thus, the wiring which was previously completely arranged on the panel MLP is now partly on the substrate on the piezoelectric die or chip.

[0050] Surprisingly, this minor change has a major impact on the sensitivity of the device to manufacturing tolerances. The parasitic inductance LP is still present in the circuit but is now much more stable and the impact on the filter device performance is significantly reduced. The filter device comprises a first matching circuit MC1 and a second matching circuit MC2 formed on and in a multilayer panel MLP. A first filter circuit FC1 and at least a signal path SP comprising a second filter circuit are formed and arranged on the surface of the substrate. However, the common node CN is connected to the signal path SP on the chip. Furthermore, the common node CN is directly connected to the first matching circuit MC1 and the second matching circuit MC2. The other end or terminal of the first matching circuit MC1 is connected to the first filter circuit. The second matching circuit which can only comprise a parallel coil is connected in series between the antenna AN and the common node CN.

[0051] All interconnection means ICM between the substrate SU and the panel MLP are realized as bumps. According to the above, the bumps are realized as solder bumps. The bumps are realized as solder bumps. Figure 2The common approach shown, for example, the common node CN is implemented within the laminate as connected with the first matching circuit and the second matching circuit. According to design requirements, the solder bumps to the signal path SP were previously located in the corners of the substrate SU. Thus, there are solder bumps and wires inside the substrate SU, which have introduced "parasitic" inductances into the circuit of the filter device and mainly into the signal path and its second or multiple filter circuits.

[0052] In a first step of the proposed design change, the solder bumps are moved towards the filter circuit, the filter circuit towards the first resonator of the filter circuit, thus reducing the length of the wires inside the substrate and neglecting the design requirements. Thus, there are no more bumps in the corners of the substrate. As a disadvantage, this can lead to negative quality issues.

[0053] A second step of the proposed design change again starts from the previous design shown schematically as Figure 2 The common node CN is moved from the substrate corner towards the inside of the substrate SU, thus eliminating the parasitic inductances of the solder bumps and the wiring inside the substrate. Since there are still bumps at the corners of the substrate, the violation of the design rules no longer occurs. However, additional bumps are required. With this change, the influence of manufacturing tolerances, for example, bump height tolerances, is minimized.

[0054] Figure 4 An exemplary circuit of a multilayer panel and a piezoelectric substrate according to one embodiment of the present application is shown schematically. In this figure, the panel MLP is depicted in a top view and the substrate SU in a view on its bottom surface. Although connected by bumps as interconnect components ICM, for better understanding, the connecting surfaces of the panel MLP and the substrate SU are depicted separately. Interconnects (depicted as lines) are formed between the contact areas CA on the panel and the pads PD on the substrate. For clarity, only some interconnects are shown. The device typically comprises a larger number of pads PD, contact areas CA and interconnect components ICM.

[0055] A second matching circuit MC2 for matching the antenna AN with the filter circuit FC is arranged between the antenna AN and the antenna terminal AT on top of the panel MLP. The antenna terminal AT is connected to the first pad PD1 on the substrate through an interconnect component ICM. The pad PD is connected to a second pad representing the common CN through a first section SLS of a signal line on the substrate surface. The first interconnect component ICM1 connects the common node to the panel and further to the first matching circuit MC1. The second interconnect component ICM2 connects the first matching circuit MC1 to the second pad PD2 on the substrate SU and further to the signal path SP and thus to the at least one second filter circuit FC. In comparison to the previously known design, the proposed filter arrangement requires an additional bump (interconnect component ICM) which is connected to the first pad PD1 or the common node CN depending on the perspective. As mentioned before, one bump / interconnect component connected with the first pad PD1 and the antenna terminal is arranged in or near the corner CRN of the substrate SU.

[0056] Figure 5 A simulation transfer curve between the antenna AN and the signal path SP around the GPS / GNSS band is shown.

[0057] Fig. 3 shows three curves comparing the previously used design with the improved design after the first step and further with the improved design. It can be easily seen that the GPS performance does not differ significantly and the three lines almost completely coincide.

[0058] Figure 6 A transfer curve between the antenna AN and the signal path around the GPS / GNSS band is shown in a wideband description. The three curves match very well and confirm that the GPS performance does not differ significantly.

[0059] Figure 7Three transfer curves are shown in the wideband description between the antenna AN and the first filter circuit FC1. It can be seen that there is no significant difference in the frequency range covering the signal path SP band. The frequency range of interest in the signal path is from 617 MHz (band N71) to 4.2 GHz (band N77). In the frequency bands below 3 GHz, there is no significant difference between the three curves. However, at frequencies above 3.5 GHz, there is a clear and substantial difference in performance. Here, the three curves are spreading out. Curve 1 is assigned to the previous design. Curve 2 corresponds to the design after the first change step, in which the bump to the antenna terminal is moved as close as possible to the signal path including the SAW resonator. Curve 3 corresponds to the design after the second change step, in which the common node CN is not on or in the substrate SU. The embodiment according to curve 3 is the design after the second step, and shows a further improvement over curve 2 according to the design after the first step. Curve 3 has the widest bandwidth, and shows an improved insertion loss near the right band edge of about 3.5 GHz.

[0060] Figure 8 This finding is confirmed, Figure 8 The reflection curve (VSWR) of the first filter circuit FC1 is shown in the wideband description of all the bands included. Here, the reflection is also significantly improved at frequencies above about 3 GHz. It can be seen that the three curves are also spreading out in this area.

[0061] Figure 9 is Figure 7 is an enlarged view and shows the amount of improvement that has been made for the respective transfer curve that has been simulated for the signal path (including the covered cell bands). A first comparison is made of those points on the curves that have a -1 dB attenuation value. These points occur at 3932 MHz (curve 1), 4023 MHz (curve 2) and 4057 MHz. A second comparison is made of the attenuation values at a given frequency. At 4.2 GHz, the attenuation is calculated to be -1.614 dB (curve 1), -1.359 dB (curve 2) and -1,267 dB (curve 3). It can be seen that curve 3 according to the design after the second step shows the best results in terms of bandwidth, respectively in terms of attenuation at a given frequency.

[0062] Figure 10An improvement amount is shown for the respective reflection curves that have been simulated for the first filter circuit (including the covered cell band). A first comparison is made for the point on the curve where the reflection coefficient is 2. A second comparison is made for the reflection value at a given frequency. At 4.2 GHz, the reflection coefficient reaches 2,232 (curve 1), 2.013 (curve 2) and 1.896 (curve 3). The calculated reflection value is 2.0, which occurs at 4108 MHz (curve 1), 4194 MHz (curve 2) and 4249 MHz (curve 3). It can be seen that according to the design after the second step, curve 3 shows the best results in terms of reflection at a given frequency and frequency position of a given reflection rate, respectively. Table 1 summarizes the results and findings:

[0063]

[0064] Table 1

[0065] Figures 11 to 13 The sensitivity of the different designs of the filter device to different bump heights is shown. As indicated by the dashed lines connecting the respective sections of the respective upper figures to the enlarged sections in the lower figures, the respective lower figures show an enlarged section of the upper figures.

[0066] Figure 11 The right part of the passband curve of the initial design before the step 1 variation is shown. Curve 4 is related to the results for a bump height of 60 pm, curve 5 is related to the results for a bump height of 55 pm and curve 6 is related to the results for a bump height of 50 pm. The enlarged section of the figure at the right band edge is depicted in the lower part of the figure to better see the differences. It can be seen that the widest bandwidth is achieved with the lowest bump height (50 pm height / curve 6). This is in line with the finding that a higher parasitic inductance resulting from a higher bump height has a detrimental effect on the filter performance.

[0067] Figure 12 The right part of the passband curve of the design after the step 1 variation is shown in a similar way. It can be seen that the three curves have approached each other, thereby reducing the differences.

[0068] Figure 13 The right part of the passband curve of the design after the step 2 variation is shown in a similar way. It can be seen that the three curves have further approached each other, almost coinciding with each other. Thus, such a design is very low sensitive to manufacturing tolerances (e.g. bump height).

[0069] Figures 14A to 14C The sensitivity of the different designs of the filter device is shown by considering the reflection rate (VSWR) of these designs at different bump heights.

[0070] With Figures 11 to 13The filter design after step 1 variation shows an increase / decrease in sensitivity to tolerances, as illustrated in the graph in Figure 1. The filter design after step 2 variation shows the lowest sensitivity. Curves 4, 5 and 6 are similar to curves 1, 2 and 3, respectively, but with a different bump height. The filter design after step 1 variation shows an increase / decrease in sensitivity to tolerances, as illustrated in the graph in Figure 2. The filter design after step 2 variation shows the lowest sensitivity. Curves 7, 8 and 9 are similar to curves 4, 5 and 6, respectively, but with a different bump height. Figures 11 to 13 The same bump height correlation is explained. It has been found (see Figure 14A ), that the known filter design before any variation shows a maximum frequency difference of 3330 ppm (about 14 MHz) related to the reflection coefficient of 2.0 of the reflection curve related to a different bump height. For the filter design after step 1 variation (see Figure 14B ), this difference is reduced to 1640 ppm (about 6.9 MHz) and is further reduced to 330 ppm (about 1.3 MHz) after step 2 variation. This is a significant stabilization to the unavoidable tolerances and at the same time helps to improve the device performance.

[0071] List of used terms and reference signs

[0072]

[0073]

Claims

1. A filter device, comprising: a multi-layer panel having integrated wiring; a piezoelectric substrate mounted to the multi-layer panel; a first filter circuit and a signal path including a second filter circuit, both filter circuits being implemented on a top surface of the piezoelectric substrate and connected to a common antenna terminal; a first matching circuit having a first end connected to the common antenna terminal and a second end connected to the signal path having the second filter circuit, the first matching circuit including the wiring in the multi-layer panel; and a common node to which the first filter circuit, the signal path, and the common antenna terminal are connected, the common node being a pad on the piezoelectric substrate facing the top surface of the multi-layer panel.

2. The filter device of claim 1, wherein the first matching circuit implemented by the wiring in the multi-layer panel is circuit connected in series between the signal path and the common node, wherein a first series line section disposed on the piezoelectric substrate connects the common node and a first pad, wherein a second series line section disposed on the piezoelectric substrate connects a second pad and the signal path including the second filter circuit, wherein a first interconnect connects the first pad to a first end of the first matching circuit, wherein a second interconnect connects the second pad to a second end of the first matching circuit.

3. The filter device of claim 1 or 2, wherein a second matching circuit is circuit connected between the common antenna terminal and the common node.

4. The filter device of claim 1 or 2, wherein at least one of the first filter circuit and the second filter circuit includes a SAW resonator.

5. The filter device of claim 1 or 2, the filter device is any of a duplexer, a multiplexer, or an extractor.

6. The filter device of claim 1 or 2, wherein the first filter circuit is a bandpass filter for GPS and / or GNSS signals.

7. The filter device of claim 6, wherein the first matching circuit is circuit connected in series between the signal path and the common node and includes a bandstop for GPS / GNSS frequencies.

8. The filter device of claim 7, wherein the signal path has a VWSR less than 2 between 617 MHz and 4.2 GHz except for a region around the GPS / GNSS frequencies.

9. The filter device of claim 1 or 2, wherein a second matching circuit is circuit connected between the common antenna terminal and the common node, wherein the second matching circuit includes a series coil to match an antenna to the first filter circuit and the signal path.

10. The filter device of claim 1 or 2, ​ wherein each interconnect between any pad on the piezoelectric substrate and a corresponding contact area on a surface of the multilayer panel comprises a bump, wherein the interconnect between the common antenna terminal and a corresponding pad on the piezoelectric substrate is located near a corner of the piezoelectric substrate.

11. The filter device of claim 1 or 2, wherein the multilayer panel comprises any of a laminate, an HTCC, and an LTCC.

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