Flash memory device with non-aligned storage structure and data storage method

Abstract

The embodiment of the present application relates to the application field of storage devices, and discloses a flash memory device with a non-aligned storage structure and a data storage method. The flash memory device with a non-aligned storage structure includes: a controller, connecting multiple chip packages through multiple channels, wherein each channel is connected to at least two types of chip package structures, each chip package structure includes at least one chip package, and each chip package includes at least one logic unit. By setting each channel to connect at least two types of chip packages, the flash memory device presents a non-aligned structure, thereby realizing flexible capacity requirements and diversified capacity specifications, and can also increase reserved space to improve the performance of the flash memory device and extend the life of the flash memory device.

Description

Technical Field

[0001] The present application relates to the field of storage device applications, and in particular to a flash memory device with a non-aligned storage structure and a data storage method. Background Art

[0002] Flash memory devices, such as solid state drives (SSDs), are hard disks made using solid-state electronic storage chip arrays. SSDs include a control unit and a storage unit (FLASH storage chip or DRAM storage chip).

[0003] At present, SSDs all have standard aligned storage structures, which are reflected in the capacity. The physical capacity is generally 1T, 2T, 4T, etc., and the corresponding logical capacity is generally 800G, 1600G, 3200G, etc. These standard capacity specifications are related to the internal storage structure of the SSD. The storage unit of the SSD is composed of many flash memory chips. Usually, the standard capacity of a flash memory chip is 256Gb, 512Gb, 1Tb, etc. Therefore, it is impossible to achieve non-standard capacity specifications. In addition, due to the fixed standard capacity, the reserved space is insufficient, which affects the life of the flash memory device.

[0004] Based on this, the existing technology needs to be improved urgently. Summary of the invention

[0005] The embodiments of the present application provide a flash memory device and a data storage method with a non-aligned storage structure, which can realize a flash memory device with non-standard capacity and increase the physical capacity of the flash memory device, increase the reserved space, thereby improving the performance of the flash memory device, and help to extend the life of the flash memory device.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a flash memory device with a non-aligned storage structure, the device comprising:

[0008] The controller is connected to a plurality of chip packages via a plurality of channels, wherein each channel is connected to at least two types of chip package structures, each chip package structure includes at least one chip package, and each chip package includes at least one logic unit.

[0009] In some embodiments, the chip package structures connected to each channel are of the same type, and / or the number of chip packages connected to each channel is the same;

[0010] or,

[0011] The chip packaging structures connected by at least two channels are of different types, and / or the numbers of chip packaging connected by at least two channels are different.

[0012] In some embodiments, each channel corresponds to at least one chip enable signal, and each chip enable signal corresponds to at least one logic unit.

[0013] In some embodiments, the storage capacity of each logical unit is fixed, and each logical unit includes a fixed number of physical blocks.

[0014] In some embodiments, the chip packaging structure includes a single chip package, a dual chip package, a quad chip package and an octal chip package, wherein the single chip package corresponds to one logic unit, the dual chip package corresponds to two logic units, the quad chip package corresponds to four logic units, and the quad chip package corresponds to eight logic units.

[0015] In a second aspect, an embodiment of the present application provides a flash memory device with a non-aligned storage structure, the device comprising:

[0016] A controller is provided, wherein a plurality of chip packages are connected via a plurality of channels, wherein each channel is connected to at least one type of chip package structure, wherein the types or quantities of chip package structures connected by at least two channels are different, each type of chip package structure includes at least one chip package, and each chip package includes at least one logic unit.

[0017] In some embodiments, the number of chip packages connected to each channel is the same;

[0018] or,

[0019] The number of die packages connected to at least two channels is different.

[0020] In a third aspect, an embodiment of the present application provides a flash memory device with a non-aligned storage structure, the device comprising:

[0021] The controller is connected to a plurality of chip packages through a plurality of channels, and the number of chip package structures corresponding to each channel is not equal to 2^n, where n is a positive integer.

[0022] In some embodiments, each channel is connected to the same type of chip package structure.

[0023] or,

[0024] Each channel is connected to a chip package structure of one type, and at least two channels are connected to chip package structures of different types.

[0025] In some embodiments, each channel connects at least two types of chip packaging structures, wherein:

[0026] The chip package structures connected to each channel are of the same type, and / or the number of chip packages connected to each channel is the same;

[0027] or,

[0028] The chip packaging structures connected by at least two channels are of different types, and / or the numbers of chip packaging connected by at least two channels are different.

[0029] In a fourth aspect, an embodiment of the present application provides a data storage method, which is applied to a flash memory device with a non-aligned storage structure as in the first aspect, the second aspect, or the third aspect, and the method includes:

[0030] When the flash memory device is first powered on, determining invalid logical units;

[0031] Mark all physical blocks in the invalid logical unit as bad blocks.

[0032] In some embodiments, the method further comprises:

[0033] All physical blocks in the flash memory device are scanned to determine all bad blocks in the flash memory device.

[0034] In some embodiments, scanning all physical blocks in the flash memory device to determine all bad blocks in the flash memory device includes:

[0035] sequentially scanning each physical block in the flash memory device;

[0036] When a physical block is scanned, it is determined whether the physical block belongs to an invalid logical unit;

[0037] If yes, mark the physical block as a bad block;

[0038] If not, further determine whether the physical block includes a bad block identifier;

[0039] If the physical block includes a bad block identifier, the physical block is confirmed to be a bad block;

[0040] Repeat the above operation to scan the next physical block until the last physical block of the flash memory device is scanned.

[0041] In some embodiments, the method further comprises:

[0042] The logical units in the flash memory device are initialized one by one, and if a certain logical unit is an invalid logical unit, the invalid logical unit is skipped.

[0043] In some embodiments, the method further comprises:

[0044] When accessing the flash device, all physical blocks in invalid logical units are skipped.

[0045] In a fifth aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a flash memory device to execute the data storage method of the second aspect.

[0046] The beneficial effect of the embodiment of the present application is that, different from the prior art, the embodiment of the present application provides a flash memory device and a data storage method with a non-aligned storage structure, wherein the flash memory device with a non-aligned storage structure comprises: a controller, connecting a plurality of chip packages through a plurality of channels, wherein each channel connects at least two types of chip packages, each chip package includes at least one chip package, and each chip package includes at least one logic unit. By setting each channel to connect at least two types of chip packages, the flash memory device presents a non-aligned structure, thereby increasing the reserved space, thereby reducing the write amplification index, and further improving the random write performance of the flash memory device, so as to extend the life of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0048] Figure 1 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0049] Figure 2 is a schematic diagram of a first storage structure of a flash memory device provided in an embodiment of the present application;

[0050] Figure 3 is a schematic diagram of a second storage structure of a flash memory device provided in an embodiment of the present application;

[0051] Figure 4 is a schematic diagram of a third storage structure of a flash memory device provided in an embodiment of the present application;

[0052] Figure 5 is a schematic diagram of a fourth storage structure of a flash memory device provided in an embodiment of the present application;

[0053] Figure 6 is a schematic diagram of a fifth storage structure of a flash memory device provided in an embodiment of the present application;

[0054] Figure 7 is a schematic diagram of a sixth storage structure of a flash memory device provided in an embodiment of the present application;

[0055] Figure 8It is a flowchart of a data storage method provided by an embodiment of the present application;

[0056] Fig. 9 yes Figure 4 A schematic diagram of the storage structure in the software perspective;

[0057] Fig.10 Yes Figure 4 A schematic diagram of invalidating some logical units in a storage structure;

[0058] Fig.11 It is a flowchart of a bad block scan provided by an embodiment of the present application;

[0059] Fig.12 It is a schematic diagram of a process of initializing a logic unit provided in an embodiment of the present application;

[0060] Fig.13 It is a structural schematic diagram of a flash memory device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0062] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0063] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0064] See also Figure 1 , Figure 1 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0065] like Figure 1As shown, the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110. The flash memory device 100 is connected to the host 200 in a wired or wireless manner to achieve data interaction.

[0066] Flash memory medium 110, as the storage medium of flash memory device 100, is also called flash memory, Flash, Flash memory or Flash particles. It is a type of storage device and a non-volatile memory. It can store data for a long time even without current supply. Its storage characteristics are equivalent to those of a hard disk, making flash memory medium 110 the basis of storage media for various portable digital devices.

[0067] The controller 120 includes a data converter 121 , a processor 122 , a buffer 123 , a flash controller 124 , and an interface 125 .

[0068] The data converter 121 is connected to the processor 122 and the flash controller 124 respectively, and the data converter 121 is used to convert binary data into hexadecimal data, and convert hexadecimal data into binary data. Specifically, when the flash controller 124 writes data to the flash medium 110, the binary data to be written is converted into hexadecimal data through the data converter 121, and then written into the flash medium 110. When the flash controller 124 reads data from the flash medium 110, the hexadecimal data stored in the flash medium 110 is converted into binary data through the data converter 121, and then the converted data is read from the binary data page register. Among them, the data converter 121 may include a binary data register and a hexadecimal data register. The binary data register can be used to save the data converted from hexadecimal to binary, and the hexadecimal data register can be used to save the data converted from binary to hexadecimal.

[0069] The processor 122 is connected to the data converter 121, the cache 123, the flash memory controller 124 and the interface 125, respectively. The processor 122 and the data converter 121, the cache 123, the flash memory controller 124 and the interface 125 can be connected via a bus or other means. The processor is used to run the non-volatile software programs, instructions and modules stored in the cache 123, so as to implement any method embodiment of the present application.

[0070] The buffer 123 is mainly used to buffer the read / write instructions sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read / write instructions sent by the host 200.

[0071] The flash memory controller 124 is connected to the flash memory medium 110, the data converter 121, the processor 122 and the cache 123, and is used to access the back-end flash memory medium 110 and manage various parameters and data I / O of the flash memory medium 110; or, it is used to provide an access interface and protocol, implement the corresponding SAS / SATA target protocol end or NVMe protocol end, obtain the I / O instructions issued by the host 200 and decode and generate internal private data results to wait for execution; or, it is responsible for the core processing of the flash translation layer (FTL).

[0072] Interface 125 connects the host 200 and the data converter 121, the processor 122 and the buffer 123, and is used to receive data sent by the host 200, or receive data sent by the processor 122 to realize data transmission between the host 200 and the processor 122. Interface 125 can be a SATA-2 interface, a SATA-3 interface, a SAS interface, an MSATA interface, a PCI-E interface, a NGFF interface, a CFast interface, an SFF-8639 interface and an M.2NVME / SATA protocol.

[0073] Please refer to Figure 2 , Figure 2 is a schematic diagram of a first storage structure of a flash memory device provided in an embodiment of the present application;

[0074] like Figure 2 As shown, the storage structure of the flash memory device is a standard aligned storage structure. The controller is connected to the flash memory through N channels, and the N channels are CH0, CH1, ..., CHN, wherein each channel is connected to a quad die per package (QDP), and the QDP includes four logical units (LUNs). Assuming that the capacity of a logical unit (LUN) is 128GB, one channel corresponds to one QDP, and the capacity of the QDP is 4*128GB. The capacity of 16 channels is 16*4*128GB=8192GB=1TB.

[0075] It is understandable that the above-mentioned connections, for example, the connection between the channel and the chip package, refer to logical connections, and the physical connection depends on the specific hardware implementation.

[0076] The capacity of a solid-state drive depends on how many flash memory chips it is made up of. The storage structure of a solid-state drive consists of channels, targets, and logical units (LUNs). The flash memory chip mentioned above can be understood as a LUN. In this storage structure, the number of targets connected to a channel is equal and is a power of 2. The number of LUNs contained in a target is also equal and is also a power of 2. For example, the number of LUNs included in a target is usually 1, 2, or 4, and the number of targets connected to a channel is usually 1, 2, 4, or 8. This standard-aligned storage structure determines that the capacity of the entire solid-state drive is usually also the capacity of 2 logical units (LUNs). For example, if the capacity of a logical unit (LUN) is 128Gb, ​​the capacity of the standard-aligned storage structure is 1T, 2T, 4T, etc. However, due to the fixed standard capacity, the reserved space is insufficient.

[0077] Based on this, an embodiment of the present application provides a flash memory device with a non-aligned storage structure to increase reserved space and improve the life of the flash memory device.

[0078] Embodiment 1

[0079] In an embodiment of the present application, at least two types of chip packaging structures are arranged in the same channel to realize a non-aligned storage structure in the channel.

[0080] For details, please refer to Figure 3 , Figure 3 is a schematic diagram of a second storage structure of a flash memory device provided in an embodiment of the present application;

[0081] like Figure 3 As shown, the controller is connected to the flash memory through N channels, the N channels are CH0, CH1, ..., CHN, wherein each channel is connected to at least two types of chip packaging structures, for example: each channel is connected to the first chip packaging structure, the second chip packaging structure, ..., the Nth chip package, wherein each chip packaging structure includes at least one chip package, and each chip package includes at least one logic unit (LogicUnit, LUN), for example: please refer to Figure 4 , Figure 4 is a schematic diagram of a third storage structure of a flash memory device provided in an embodiment of the present application;

[0082] like Figure 4As shown, the storage structure includes two types of chip packaging structures, namely a quad die per package (QDP) and a dual die per package (DDP), wherein the quad die packaging structure includes a quad die package, and the dual die packaging structure includes a dual die package.

[0083] It can be understood that each chip packaging structure in the embodiments of the present application may include one or more chip packages, for example: Figure 4 The package includes two quad-die packages (QDPs) and one dual-die package (DDP).

[0084] In the embodiments of the present application, the number of chip packages corresponding to each chip packaging structure can be flexibly adjusted according to the needs of physical capacity and structural connectivity to achieve various chip package combinations.

[0085] In the embodiment of the present application, the types of chip packaging structures connected to each channel are the same, and / or the number of chip packages connected to each channel is the same;

[0086] or,

[0087] The chip packaging structures connected by at least two channels are of different types, and / or the numbers of chip packaging connected by at least two channels are different.

[0088] The chip packaging structures connected to each channel are of the same type, for example, the chip packaging structures connected to channel CH0, channel CH1, ..., channel CHN are all the first chip packaging structure and the second chip packaging structure;

[0089] Among them, the number of chip packages connected to each channel is the same, for example: the number of chip packages connected to channel CH0, channel CH1, ..., channel CHN is 6, for example: the first chip packaging structure is a dual chip package (dual die per package, DDP), the second chip packaging structure is a quad chip package (quad die per package, QDP), each channel has only one dual chip package and quad chip package, then the number of chip packages connected to each channel is 2+4=6.

[0090] Among them, the chip packaging structures connected by at least two channels are of different types, for example, the chip packaging structures connected by channel CH0 are the first chip packaging structure and the second chip packaging structure, and the chip packaging structures connected by channel CH1 are the second chip packaging structure and the third chip packaging structure.

[0091] For details, please refer to Figure 5 , Figure 5is a schematic diagram of a fourth storage structure of a flash memory device provided in an embodiment of the present application;

[0092] like Figure 5 As shown, the N channels are CH0, CH1, ..., CHN, wherein channel CH0 is connected to one type of chip packaging structure, namely, the first chip packaging structure, and channel CH1 is connected to two types of chip packaging structures, namely, the first chip packaging structure and the second chip packaging structure, so that the chip packaging structure connected to at least one channel is different from the chip packaging structure connected to other channels, so that the chip packaging structures connected to different channels are not completely the same, and thus the chip packaging structures connected to different channels present a non-aligned structure.

[0093] The number of chip packages connected to at least two channels is different. For example, the number of chip packages connected to channel CH0 is 6, and the number of chip packages connected to channel CH1 is 8.

[0094] In the embodiments of the present application, the chip packaging structure includes but is not limited to: single die per package (SDP), dual die per package (DDP), quad die per package (QDP) and octal die per package (ODP), wherein the single die package corresponds to one logic unit (Logic Unit, LUN), the dual die package corresponds to two logic units, the quad die package corresponds to four logic units, and the quad die package corresponds to eight logic units.

[0095] In the embodiment of the present application, each channel (Channel) corresponds to at least one chip enable signal (ChipEnable, CE), and each chip enable signal (ChipEnable, CE) corresponds to at least one logic unit.

[0096] In the embodiment of the present application, the storage capacity of each logical unit is fixed, and each logical unit includes a fixed number of physical blocks.

[0097] Since the storage capacity of each logical unit is fixed and each logical unit includes a fixed number of physical blocks, the address management structure of the flash memory device with an unaligned storage structure can be adjusted based on the address management structure of the aligned storage structure, which is conducive to realizing the specifications of different physical capacities of the unaligned storage structure.

[0098] It is understandable that from the perspective of the flash memory controller, in order to meet performance requirements, multiple flash memory logical units (LUN) are required to be concurrent, and multiple channels are usually configured. The number of logical units (LUN) hanging on a channel depends on the SSD capacity and performance requirements. The more logical units on a channel, the more concurrent ones, and the better the performance.

[0099] Among them, the logical unit (LUN) is the smallest basic management unit of flash memory communication. If multiple logical units are connected to a channel, each logical unit shares a set of buses on each channel. At this time, the flash memory controller uses the chip enable signal (ChipEnable, CE) to identify the logical unit (LUN) for communication. For example: before the flash memory controller sends read and write commands and data to the logical unit with a specific address, it first selects the chip enable signal (CE) corresponding to the logical unit (LUN), and then sends the read and write commands and data.

[0100] Since the physical chip encapsulates many devices (Target), each Target is completely independent and may only share data signals. Therefore, the chip enable signal (Chip Enable, CE) is needed to select which Target is currently transmitting data. For example, CE_n corresponds to one Target.

[0101] Please refer to Figure 4 ,like Figure 4 As shown, the quad die package structure (QDP) includes four logic units, and the dual die package structure (DDP) includes two logic units.

[0102] Assume that the structure of QDP is 2 chip enable signals (CE), each chip enable signal (CE) corresponds to 2 logical units (LUN), that is, the structure of QDP is 2CE*2LUN.

[0103] Assume that the structure of DDP is 2 chip enable signals (CE), each chip enable signal (CE) corresponds to 1 logical unit (LUN), that is, the structure of QDP is 2CE*1LUN.

[0104] At this time, if a physical capacity of 1.5TB needs to be achieved, a quad-chip package (QDP) and a dual-chip package (DDP) are connected through each channel (Channel), with a total of 6 logical units (LUNs). The physical capacity of a logical unit (LUN) is 128GB, and the physical capacity corresponding to a channel (Channel) is 6*128GB. At this time, 16 channels (Channel) are designed, and the physical capacity of 16 channels (Channel) is 16*6*128Gb=12288Gb=1536GB=1.5T.

[0105] In an embodiment of the present application, a flash memory device with a non-aligned storage structure is provided, the device comprising: a controller, connecting a plurality of chip packages via a plurality of channels, wherein each channel is connected to at least two types of chip package structures, each chip package structure comprises at least one chip package, and each chip package comprises at least one logic unit.

[0106] Since at least two types of chip packaging structures are set in the same channel to realize a non-aligned storage structure in the channel, the physical capacity can be flexibly adjusted to realize diversified capacity specifications. Moreover, since at least two types of chip packaging structures are connected to each channel, the physical capacity is improved, the reserved space (Over-Provision, OP) is increased, thereby reducing the write amplification index, thereby further improving the random write performance of the flash memory device and extending the service life of the flash memory device.

[0107] Embodiment 2

[0108] Different from the above-mentioned first embodiment, in the embodiment of the present application, the chip packaging structure between different channels is also set to be different, so that the channels also present a non-aligned structure.

[0109] In an embodiment of the present application, a flash memory device with a non-aligned storage structure includes:

[0110] A controller is provided, wherein a plurality of chip packages are connected via a plurality of channels, wherein each channel is connected to at least one type of chip package structure, wherein the types or quantities of chip package structures connected by at least two channels are different, each type of chip package structure includes at least one chip package, and each chip package includes at least one logic unit.

[0111] Specifically, the chip packaging structures connected by at least two channels are of different types, that is, there is at least one channel connected chip packaging structure that is different from the chip packaging structures connected by other channels, so that the chip packaging structures connected by different channels present a non-aligned structure, wherein at least one channel connects one type of chip packaging structure.

[0112] For example: See Figure 6 , Figure 6 is a schematic diagram of a fifth storage structure of a flash memory device provided in an embodiment of the present application;

[0113] like Figure 6 As shown, the N channels are CH0, CH1, ..., CHN, wherein channels CH0-CHN are all connected to one type of chip packaging structure, namely QDP, and the number of chip packaging structures connected between at least two channels is different, for example: channel CH0 is connected to two QDPs, and channel CHN is connected to one QDP, so that at least the channels are not aligned, thereby realizing a non-aligned storage structure.

[0114] In the embodiment of the present application, the number of chip packages connected to each channel is the same;

[0115] or,

[0116] The number of die packages connected to at least two channels is different.

[0117] The number of chip packages connected to each channel is the same, for example, channel CH0 is connected to two QDPs, and channel CH1 is connected to four DDPs, so that the number of chip packages connected to channel CH0 and channel CH1 is the same, that is, 8 chip packages.

[0118] Among them, the number of chip packages connected to at least two channels is different, for example: channel CH0 connects two QDPs, the number of chip packages connected to it is 8, channel CHN connects 1 QDP, the number of chip packages connected to it is 4, so that the number of chip packages connected to channel CH0 and channel CHN is different.

[0119] In the embodiments of the present application, the chip packaging structure includes but is not limited to: single die per package (SDP), dual die per package (DDP), quad die per package (QDP) and octal die per package (ODP), wherein the single die package corresponds to one logic unit (Logic Unit, LUN), the dual die package corresponds to two logic units, the quad die package corresponds to four logic units, and the quad die package corresponds to eight logic units.

[0120] In the embodiment of the present application, each channel (Channel) corresponds to at least one chip enable signal (ChipEnable, CE), and each chip enable signal (ChipEnable, CE) corresponds to at least one logic unit.

[0121] In the embodiment of the present application, the storage capacity of each logical unit is fixed, and each logical unit includes a fixed number of physical blocks.

[0122] Since the storage capacity of each logical unit is fixed and each logical unit includes a fixed number of physical blocks, the address management structure of the flash memory device with an unaligned storage structure can be adjusted based on the address management structure of the aligned storage structure, which is conducive to realizing the specifications of different physical capacities of the unaligned storage structure.

[0123] It is understandable that from the perspective of the flash memory controller, in order to meet performance requirements, multiple flash memory logical units (LUN) are required to be concurrent, and multiple channels are usually configured. The number of logical units (LUN) hanging on a channel depends on the SSD capacity and performance requirements. The more logical units on a channel, the more concurrent ones, and the better the performance.

[0124] Among them, the logical unit (LUN) is the smallest basic management unit of flash memory communication. If multiple logical units are connected to a channel, each logical unit shares a set of buses on each channel. At this time, the flash memory controller uses the chip enable signal (ChipEnable, CE) to identify the logical unit (LUN) for communication. For example: before the flash memory controller sends read and write commands and data to the logical unit with a specific address, it first selects the chip enable signal (CE) corresponding to the logical unit (LUN), and then sends the read and write commands and data.

[0125] Since the physical chip encapsulates many devices (Target), each Target is completely independent and may only share data signals. Therefore, the chip enable signal (Chip Enable, CE) is needed to select which Target is currently transmitting data. For example, CE_n corresponds to one Target.

[0126] In an embodiment of the present application, the chip packaging structures connected by different channels present a non-aligned structure, for example: misalignment in type or quantity, thereby realizing a non-aligned storage structure to realize a flash memory device with non-standard capacity and improve the physical capacity of the flash memory device, increase the reserved space, thereby reducing the write amplification index, thereby further improving the random write performance of the flash memory device, and helping to extend the life of the flash memory device.

[0127] It can be understood that at least one channel is connected to a type of chip packaging structure, and the chip packaging structures connected between multiple channels can be partially the same, for example: channel CH0 and channel CH1 are both connected to the first chip packaging structure, and channel CH1 and channel CHN are both connected to the second chip packaging structure.

[0128] In an embodiment of the present application, a flash memory device with a non-aligned storage structure is provided, the device comprising: a controller, connecting a plurality of chip packages via a plurality of channels, wherein each channel is connected to at least one type of chip package structure, wherein the type or number of chip package structures connected by at least two channels is different, each chip package structure comprises at least one chip package, and each chip package comprises at least one logic unit.

[0129] By setting each channel to connect at least one type of chip packaging structure, wherein the types or quantities of chip packaging structures connected to at least two channels are different, the flash memory device presents a non-aligned structure, thereby increasing the reserved space, thereby reducing the write amplification index, and further improving the random write performance of the flash memory device, thereby extending the life of the flash memory device.

[0130] Embodiment 3

[0131] Different from the above-mentioned first and second embodiments, in the embodiment of the present application, each channel is connected to a number of non-2-aligned chip packaging structures to achieve a non-aligned structure in the channel.

[0132] Specifically, the flash memory device with the non-aligned storage structure includes:

[0133] The controller is connected to a plurality of chip packages through a plurality of channels, and the number of chip package structures corresponding to each channel is not equal to 2^n, where n is a positive integer.

[0134] Please refer to Figure 7 , Figure 7 is a schematic diagram of a sixth storage structure of a flash memory device provided in an embodiment of the present application;

[0135] like Figure 7 As shown, the controller is connected to the flash memory through N channels, the N channels are CH0, CH1, ..., CHN, wherein each channel is connected to three QDPs, so that the number of chip packaging structures corresponding to each channel is not equal to 2^n, wherein n is a positive integer.

[0136] It is understandable that the number of chip packaging structures corresponding to each channel is not equal to the power of 2, that is, not equal to 2, 4, 8, 16, etc., which can make the flash memory device present a non-aligned storage structure to meet diverse capacity specifications.

[0137] In the embodiment of the present application, each channel is connected to the same type of chip packaging structure.

[0138] or,

[0139] Each channel is connected to a chip package structure of one type, and at least two channels are connected to chip package structures of different types.

[0140] Each channel is connected to the same type of chip packaging structure, for example, channels CH0, CH1, . . . , CHN are all connected to three QDPs.

[0141] Each channel is connected to a chip packaging structure of one type, and at least two channels are connected to chip packaging structures of different types, for example, channel CH0 is connected to three DDPs, and channel CHN is connected to three QDPs.

[0142] In the embodiment of the present application, each channel connects at least two types of chip packaging structures, wherein:

[0143] The chip package structures connected to each channel are of the same type, and / or the number of chip packages connected to each channel is the same;

[0144] or,

[0145] The chip packaging structures connected by at least two channels are of different types, and / or the numbers of chip packaging connected by at least two channels are different.

[0146] Each channel is connected to at least two types of chip packaging structures, for example, each channel is connected to a DDP and a QDP.

[0147] The chip packaging structures connected to each channel are of the same type, for example, each channel is connected to three DDPs and three QDPs.

[0148] The number of chip packages connected to each channel is the same. For example, each channel is connected to three DDPs and three QDPs, so that the number of chip packages connected to each channel is the same.

[0149] The chip packaging structures connected by at least two channels are of different types. The chip packaging structures connected by channel CH0 are DDP and QDP, while the chip packaging structures connected by channel CH1 are DDP and ODP.

[0150] The number of chip packages connected to at least two channels is different. For example, the number of chip packages connected to channel CH0 is 12, and the number of chip packages connected to channel CH1 is 16.

[0151] In the embodiments of the present application, the chip packaging structure includes but is not limited to: single die per package (SDP), dual die per package (DDP), quad die per package (QDP) and octal die per package (ODP), wherein the single die package corresponds to one logic unit (Logic Unit, LUN), the dual die package corresponds to two logic units, the quad die package corresponds to four logic units, and the quad die package corresponds to eight logic units.

[0152] In the embodiment of the present application, each channel (Channel) corresponds to at least one chip enable signal (ChipEnable, CE), and each chip enable signal (ChipEnable, CE) corresponds to at least one logic unit.

[0153] In the embodiment of the present application, the storage capacity of each logical unit is fixed, and each logical unit includes a fixed number of physical blocks.

[0154] Since the storage capacity of each logical unit is fixed and each logical unit includes a fixed number of physical blocks, the address management structure of the flash memory device with an unaligned storage structure can be adjusted based on the address management structure of the aligned storage structure, which is conducive to realizing the specifications of different physical capacities of the unaligned storage structure.

[0155] It is understandable that from the perspective of the flash memory controller, in order to meet performance requirements, multiple flash memory logical units (LUN) are required to be concurrent, and multiple channels are usually configured. The number of logical units (LUN) hanging on a channel depends on the SSD capacity and performance requirements. The more logical units on a channel, the more concurrent ones, and the better the performance.

[0156] Among them, the logical unit (LUN) is the smallest basic management unit of flash memory communication. If multiple logical units are connected to a channel, each logical unit shares a set of buses on each channel. At this time, the flash memory controller uses the chip enable signal (ChipEnable, CE) to identify the logical unit (LUN) for communication. For example: before the flash memory controller sends read and write commands and data to the logical unit with a specific address, it first selects the chip enable signal (CE) corresponding to the logical unit (LUN), and then sends the read and write commands and data.

[0157] Since the physical chip encapsulates many devices (Target), each Target is completely independent and may only share data signals. Therefore, the chip enable signal (Chip Enable, CE) is needed to select which Target is currently transmitting data. For example, CE_n corresponds to one Target.

[0158] In an embodiment of the present application, a flash memory device with a non-aligned storage structure is provided, including: a controller, connecting multiple chip packages through multiple channels, and the number of chip package structures corresponding to each channel is not equal to 2^n, where n is a positive integer.

[0159] Due to the use of a non-aligned storage structure in which each channel is connected to a number of non-2-aligned chip packaging structures, the physical capacity can be flexibly adjusted to achieve diversified capacity specifications. In addition, the physical capacity is improved, the reserved space (Over-Provision, OP) is increased, thereby reducing the write amplification index, thereby further improving the random write performance of the flash memory device and extending the service life of the flash memory device.

[0160] Embodiment 4

[0161] It can be understood that based on the non-aligned storage structure mentioned in the above-mentioned Example 1, Example 2 and Example 3, the software also needs to be adapted and supported accordingly. For example, the software uses data bits to represent the storage organization structure for the storage structure, such as using bits to represent the storage organization structure, such as: using 4 bits to represent the channel (Channel), which can represent 16 Channels; using 1 bit to represent the chip enable signal (CE), which can represent 2 CEs; using 1 bit to represent the logical unit (LUN), which can represent 2 LUNs.

[0162] like Figure 4 As shown, a channel connects a quad-die package (QDP) and a dual-die package (DDP), that is, 4 CEs and 6 LUNs. The problem that needs to be addressed in the software is that two of the 4 CEs contain 2 LUNs, and the other two CEs contain 1 LUN.

[0163] In order to adapt to this non-aligned storage structure, an embodiment of the present application provides a data storage method.

[0164] See also Figure 8 , Figure 8 It is a flowchart of a data storage method provided by an embodiment of the present application;

[0165] The data storage method is applied to the flash memory device with non-aligned storage structure in the above embodiment.

[0166] like Figure 8 As shown, the data storage method includes:

[0167] Step S801: when the flash memory device is powered on for the first time, determining an invalid logical unit;

[0168] It is understandable that when a flash memory device is powered on for the first time, for example, in the mass production stage of the flash memory device, it is necessary to determine the invalid logic units in each flash memory device.

[0169] For details, please refer to Figure 4 and Fig. 9 , Fig. 9 yes Figure 4 A schematic diagram of the storage structure in the software perspective;

[0170] like Fig. 9 As shown, from the software perspective, the aligned address structure is used. Figure 4 The dual die package (DDP) in the disk is regarded as a quad die package (QDP), that is, the physical capacity of the 1.5T disk is 2T, and its physical structure is also a 2T physical structure. Each channel connects 2 QDPs, which includes 4 CEs and 8 LUNs.

[0171] Since the software needs to manage a 2T storage structure, the number of LUNs for each channel is 4*2=8, while the actual number of LUNs for each channel is 2*2+2*1=6. Therefore, the software needs to mark all physical blocks of non-existent logical units (LUNs) as bad blocks. For example, assuming that the eight logical units (LUNs) are LUN0, LUN1, LUN2, LUN3, LUN4, LUN5, LUN6, and LUN7, and the quad die package (QDP) corresponds to LUN0, LUN1, LUN2, and LUN3, and the actual number of LUNs in each channel is 2*2+2*1=6, since the dual die package (DDP) is regarded as a quad die package (QDP), in fact, the two chip enable signals (CE) of the dual die package (DDP) only contain one LUN, the first chip enable signal (CE) of the dual die package (DDP) corresponds to LUN4, and the second chip enable signal (CE) corresponds to LUN6, therefore, LUN5 and LUN7 are marked as invalid logical units.

[0172] Step S802: Mark all physical blocks in the invalid logical unit as bad blocks.

[0173] Please refer to Fig.10 , Fig.10 Yes Figure 4 A schematic diagram of invalidating some logical units in a storage structure;

[0174] like Fig.10 As shown, LUN5 and LUN7 are determined to be invalid logical units, and all physical blocks in LUN5 and LUN7 are marked as bad blocks. Similarly, all physical blocks in some logical units in the flash memory device are marked as bad blocks.

[0175] Furthermore, after marking all physical blocks in the invalid logical unit as bad blocks, a bad block scan is required to determine all bad blocks in the flash memory device, including marked bad blocks and original bad blocks.

[0176] Specifically, the bad block scan includes: scanning all physical blocks in the flash memory device to determine all bad blocks in the flash memory device.

[0177] Specifically, all physical blocks in the flash memory device are scanned to determine all bad blocks in the flash memory device, including:

[0178] sequentially scanning each physical block in the flash memory device;

[0179] When a physical block is scanned, it is determined whether the physical block belongs to an invalid logical unit;

[0180] If yes, mark the physical block as a bad block;

[0181] If not, further determine whether the physical block includes a bad block identifier;

[0182] If the physical block includes a bad block identifier, the physical block is confirmed to be a bad block;

[0183] Repeat the above operation to scan the next physical block until the last physical block of the flash memory device is scanned.

[0184] Please refer to Fig.11 , Fig.11 It is a flowchart of a bad block scan provided by an embodiment of the present application;

[0185] like Fig.11 As shown in the figure, the bad block scanning process includes:

[0186] Step S111: Start bad block scanning;

[0187] Specifically, the physical blocks in the flash memory device are scanned one by one, that is, the current physical block is scanned.

[0188] Step S112: whether it is an invalid logical unit;

[0189] Specifically, it is determined whether the logical unit where the current physical block is located is an invalid logical unit. If so, the process proceeds to step S905: marking as a bad block; if not, the process proceeds to step S803: reading the bad block mark;

[0190] Step S113: read bad block mark;

[0191] Specifically, the bad block mark of the current physical block is read to enter step S904: whether it is a bad block; in the embodiment of the present application, the bad block mark is a common bad block marking method of a flash memory device (Nand Flash), for example: the bad block mark is set at the first bit (byte) of the first physical page (page) and the last physical page (page) of each physical block or the first bit (byte) of the spare area (spare area). By reading the information of the bit, it is determined whether the current physical block is a bad block.

[0192] Step S114: whether it is a bad block;

[0193] Specifically, by reading the bad block mark of the current physical block, it is determined whether the current physical block is a bad block;

[0194] Step S115: Mark as bad block;

[0195] If the logical unit where the current physical block is located is an invalid logical unit, the current physical block is marked as a bad block, that is, the bad block mark corresponding to the current physical block is modified to mark the current physical block as a bad block; if the bad block mark of the current physical block is read to determine that the current physical block is a bad block, no further processing is performed.

[0196] Step S116: whether it is the last physical block;

[0197] Specifically, it is determined whether the current physical block is the last physical block of the flash memory device. If so, the process proceeds to step S117: scanning ends; if not, the process proceeds to the next physical block and returns to step S112 to repeat the subsequent scanning steps.

[0198] Step S117: Scanning ends;

[0199] In the embodiment of the present application, before performing bad block scanning on the physical block, the method further includes:

[0200] The logical units in the flash memory device are initialized one by one, and if a certain logical unit is an invalid logical unit, the invalid logical unit is skipped.

[0201] For details, please refer to Fig.12 , Fig.12 It is a schematic diagram of a process of initializing a logic unit provided in an embodiment of the present application;

[0202] like Fig.12 As shown, the process of initializing the logic unit includes:

[0203] Step S121: start initialization;

[0204] Specifically, the logical units in the flash memory device are initialized one by one to facilitate the host to read data of the logical unit, or write data to the logical unit;

[0205] Step S122: whether it is an invalid logical unit;

[0206] Specifically, it is judged whether the current logical unit is an invalid logical unit. It can be understood that before all logical units are initialized, all invalid logical units in the flash memory device are pre-marked, for example: an invalid mark is pre-added to the invalid logical unit to judge whether it is an invalid logical unit; if the current logical unit includes the invalid mark, it is determined that the current logical unit is an invalid logical unit, and the process proceeds to step S904: whether it is the last logical unit; if the current logical unit does not include the invalid mark, the process proceeds to step S903: initializing the current logical unit;

[0207] Step S123: Initialize the current logic unit;

[0208] Step S124: whether it is the last logical unit;

[0209] Specifically, it is determined whether the current logical unit is the last logical unit. If so, the process proceeds to step S125: the initialization ends; if not, the process proceeds to the next logical unit and the subsequent initialization steps are repeated;

[0210] Step S125: end initialization;

[0211] In an embodiment of the present application, the method further includes:

[0212] When accessing the flash device, all physical blocks in invalid logical units are skipped.

[0213] Specifically, when the host accesses the flash memory device, since invalid marks are added to invalid logical units in advance, when a physical block is accessed, all physical blocks in the invalid logical unit are skipped according to the invalid mark of the logical unit where the physical block is located.

[0214] In an embodiment of the present application, a data storage method is provided, which is applied to a flash memory device with a non-aligned storage structure in the above embodiment, and the method includes: when the flash memory device is powered on for the first time, determining an invalid logical unit; marking all physical blocks in the invalid logical unit as bad blocks. By determining the invalid logical unit and marking all physical blocks in the invalid logical unit as bad blocks, the flash memory device with a non-aligned storage structure can write or read data normally, thereby realizing a flash memory device with a non-standard capacity, and the invalid logical unit is equivalent to increasing the reserved space, which can improve the performance and life of the flash memory device.

[0215] Please refer to Fig.13 , Fig.13 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0216] like Fig.13 As shown, the flash memory device 130 includes one or more processors 131 and a memory 132. Fig.13 A processor 131 is taken as an example.

[0217] The processor 131 and the memory 132 may be connected via a bus or other means. Fig.13 The example of connecting through bus is taken in the following.

[0218] The processor 131 is used to provide computing and control capabilities to control the flash memory device 130 to perform corresponding tasks, for example, to control the flash memory device 130 to perform the data storage method in any of the above-mentioned method embodiments, including: when the flash memory device is powered on for the first time, determining invalid logical units; marking all physical blocks in the invalid logical units as bad blocks.

[0219] By determining invalid logical units, all physical blocks in the invalid logical units are marked as bad blocks, so that the flash memory device with non-aligned storage structure can write or read data normally, thereby realizing a flash memory device with non-standard capacity. In addition, the invalid logical units are equivalent to increasing the reserved space, which can improve the performance and life of the flash memory device.

[0220] The processor 131 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0221] The memory 132, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the data storage method in the embodiment of the present application. The processor 131 can implement the data storage method in any of the following method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 132. Specifically, the memory 132 may include a volatile memory (volatile memory, VM), such as a random access memory (random access memory, RAM); the memory 132 may also include a non-volatile memory (non-volatile memory, NVM), such as a read-only memory (read-only memory, ROM), a flash memory (flash memory), a hard disk drive (hard disk drive, HDD) or a solid-state drive (solid-state drive, SSD) or other non-transitory solid-state storage devices; the memory 132 may also include a combination of the above-mentioned types of memory.

[0222] The memory 132 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 132 may optionally include a memory remotely arranged relative to the processor 131, and these remote memories may be connected to the processor 131 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0223] One or more modules are stored in the memory 132, and when executed by one or more processors 131, the data storage method in any of the above method embodiments is executed, for example, the data storage method described above is executed. Figure 8 The steps shown.

[0224] In the embodiment of the present application, the flash memory device 130 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The flash memory device 130 may also include other components for realizing device functions, which will not be described in detail here.

[0225] The flash memory device of the embodiment of the present application exists in various forms. Figure 8 The steps shown include but are not limited to: storage devices such as solid state drives.

[0226] The present application also provides a computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the data storage method in the above embodiment. For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0227] The present application also provides a computer program product, which includes one or more program codes stored in a computer-readable storage medium. A processor of an electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code to complete the method steps of the data storage method provided in the above embodiment.

[0228] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0229] Through the description of the above implementation methods, ordinary technicians in this field can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Ordinary technicians in this field can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0230] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data storage method, characterized in that: Flash memory devices applied to non-aligned storage structures, The flash memory device of the non-aligned storage structure comprises: Connecting a plurality of chip packages through a plurality of channels, wherein each channel connects at least two types of chip package structures, each chip package structure includes at least one chip package, and each chip package includes at least one logic unit; The at least two types of chip packaging structures include a first chip packaging structure and a second chip packaging structure, and the number of logic units corresponding to the first chip packaging structure is greater than the number of logic units corresponding to the second chip packaging structure; The method comprises: Based on the alignment address structure, fictionalizing at least one logic unit for the second chip packaging structure, so that the number of logic units corresponding to the second chip packaging structure is equal to the number of logic units corresponding to the first chip packaging structure; When the flash memory device is powered on for the first time, determining an invalid logic unit, wherein the invalid logic unit is at least one fictitious logic unit in the second chip packaging structure; Marking all physical blocks in the invalid logical unit as bad blocks; Each channel corresponds to at least one chip enable signal, each chip enable signal corresponds to at least one logic unit, and the method further includes: Determine a valid logic unit according to the invalid logic unit, wherein the valid logic unit = the logic unit corresponding to the second chip packaging structure - the invalid logic unit; Determine the valid logic unit as the logic unit corresponding to the chip enable signal; The valid logic unit is identified by the chip enable signal, and a read / write command and data are sent to the valid logic unit.

2. The method according to claim 1, characterized in that The chip package structures connected to each channel are of the same type, and / or the number of chip packages connected to each channel is the same; or, The chip packaging structures connected by at least two channels are of different types, and / or the numbers of chip packaging connected by at least two channels are different.

3. The method according to claim 1, characterized in that The storage capacity of each of the logical units is fixed, and each of the logical units includes a fixed number of physical blocks.

4. The method according to any one of claims 1 to 3, characterized in that: The chip packaging structure includes single chip packaging, double chip packaging, quad chip packaging and eight chip packaging, wherein the single chip packaging corresponds to one logic unit, the double chip packaging corresponds to two logic units, the quad chip packaging corresponds to four logic units, and the eight chip packaging corresponds to eight logic units.

5. The method according to claim 1, characterized in that Each channel is connected to at least one type of chip packaging structure, wherein at least two channels are connected to chip packaging structures of different types or quantities, each chip packaging structure includes at least one chip package, and each chip package includes at least one logic unit.

6. The method according to claim 5, characterized in that The number of chip packages connected to each channel is the same; or, The number of die packages connected to at least two channels is different.

7. The method according to claim 1, characterized in that The number of chip packaging structures corresponding to each channel is not equal to 2^n, where n is a positive integer.

8. The method according to claim 7, characterized in that Each of the channels is connected to a chip packaging structure of the same type, or, Each of the channels is connected to a chip packaging structure of one type, and at least two channels are connected to chip packaging structures of different types.

9. The method according to claim 7, characterized in that: Each of the channels connects at least two types of chip packaging structures, wherein: The chip package structures connected to each channel are of the same type, and / or the number of chip packages connected to each channel is the same; or, The chip packaging structures connected by at least two channels are of different types, and / or the numbers of chip packaging connected by at least two channels are different.

10. The method according to claim 1, characterized in that The method further comprises: All physical blocks in the flash memory device are scanned to determine all bad blocks in the flash memory device.

11. The method according to claim 10, characterized in that Scanning all physical blocks in the flash memory device to determine all bad blocks in the flash memory device includes: sequentially scanning each physical block in the flash memory device; When a physical block is scanned, it is determined whether the physical block belongs to an invalid logical unit; If yes, mark the physical block as a bad block; If not, further determine whether the physical block includes a bad block identifier; If the physical block includes a bad block identifier, the physical block is confirmed to be a bad block; Repeat the above operation to scan the next physical block until the last physical block of the flash memory device is scanned.

12. The method according to claim 11, characterized in that The method further comprises: The logical units in the flash memory device are initialized one by one, and if a certain logical unit is an invalid logical unit, the invalid logical unit is skipped.

13. The method according to claim 1, characterized in that The method further comprises: When accessing the flash memory device, all physical blocks in the invalid logical unit are skipped.

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