A chip design method, device, electronic equipment and readable storage medium

Abstract

Embodiments of the present application disclose a chip design method and device, electronic equipment and readable storage medium, and relate to the technical field of chip design, and are invented to improve the design efficiency of chips. The method comprises the following steps: determining a first change range and a first change step of a first size of a die, and determining a second change range and a second change step of a second size of the die; wherein the first size is a width, and the second size is a height; determining, according to process parameters and wafer size, the number of dies arranged in the wafer corresponding to each value of the second size in the second change range and the second change step, under each value of the first size in the first change range and the first change step; and providing a reference for the layout of the die on the wafer according to the corresponding relationship between each value of the first size, each value of the second size and the number of dies. The present application is suitable for providing a reference for chip design.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, and particularly to a chip design method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] In the initial stage of physical design, the chip top layout design is performed according to the area estimated in the early design and the physical implementation requirements, that is, the width and height values of the chip are obtained, so as to obtain the number of chips (chips) arranged on the wafer during production. However, as the physical implementation progresses, the chip design may be modified, and the chip layout on the wafer may be iteratively adjusted. In the related art, there is no reference basis for the layout of the chip on the wafer during the modification and iteration, thereby resulting in low chip design efficiency. SUMMARY

[0003] Therefore, the embodiments of the present application provide a chip design method and device, electronic equipment and readable storage medium, which facilitate to improve the design efficiency of the chip.

[0004] In a first aspect, the embodiments of the present application provide a chip design method, comprising: determining a process parameter of a wafer slice and a size of the wafer; determining a first change range and a first change step of a first size of a chip, and determining a second change range and a second change step of a second size of the chip; wherein the first size is the width, and the second size is the height; or, the first size is the height, and the second size is the width; determining, according to the process parameter and the wafer size, the number of chips arranged in the wafer corresponding to each value of the second size in the second change range and the second change step, under each value of the first size in the first change range and the first change step; and providing a reference for the layout of the chip on the wafer according to the corresponding relationship between each value of the first size, each value of the second size and the number of chips.

[0005] According to a specific implementation manner of the embodiments of the present application, the determining of the first change range of the first size and the determining of the second change range of the second size comprise: determining an initial first size and an initial second size; and determining the first change range of the first size and the second change range of the second size according to a preset change ratio of the first size, a preset change ratio of the second size, the initial first size and the initial second size.

[0006] According to a specific implementation manner of the embodiment of the present application, the determining the initial first size and the initial second size comprises: determining an area of the chiplet according to the number of gate levels on the chiplet; and determining the initial first size and the initial second size according to the size of the IP module on the chiplet and the area of the chiplet.

[0007] According to a specific implementation manner of the embodiment of the present application, the providing reference for the layout of the chiplet on the wafer according to the correspondence between each value of the first size, each value of the second size and the number of chiplets comprises: determining, according to the correspondence between each value of the first size, each value of the second size and the number of chiplets, a value of the first size and a value of the second size of the chiplet under a preset number of chiplets, so that the area of the chiplet is at a maximum under the preset number of chiplets; or determining, according to the correspondence between each value of the first size, each value of the second size and the number of chiplets, a first optional range of a first predetermined value of the first size and a second optional range of a second predetermined value of the second size; and determining, according to the correspondence between each value of the first size, each value of the second size and the number of chiplets, a maximum value of the number of chiplets and corresponding values of the first size and the second size in the first optional range and the second optional range.

[0008] According to a specific implementation manner of the embodiment of the present application, before the determining the value of the first size and the value of the second size of the chiplet under the preset number of chiplets, the method further comprises: displaying, according to the correspondence between each value of the first size, each value of the second size and the number of chiplets, the correspondence between each value of the first size and the number of chiplets under each value of the second size on a graphical user interface, with the second size as a first coordinate and the number of chiplets as a second coordinate.

[0009] According to a specific implementation manner of the embodiment of the present application, the determining the value of the first size and the value of the second size of the chiplet under the preset number of chiplets comprises: determining, according to the displayed correspondence between each value of the first size and the number of chiplets under each value of the second size, a maximum value of the second size of the chiplet under the preset number of chiplets; and determining a value of the first size corresponding to the maximum value of the second size and the preset number of chiplets.

[0010] In a second aspect, an embodiment of the present application provides a chip design device, comprising: a first determining module configured to determine a process parameter of wafer slicing and a size of a wafer; a second determining module configured to determine a first variation range and a first variation step of a first size of a die, and determine a second variation range and a second variation step of a second size of the die; wherein the first size is a width, and the second size is a height; or, the first size is a height, and the second size is a width; a third determining module configured to determine, according to the process parameter and the wafer size, a number of the die arranged in the wafer corresponding to each value of the first size in the first variation range and each value of the second size in the second variation range and changed by the first variation step and the second variation step; and a reference providing module configured to provide a reference for a layout of the die on the wafer according to a corresponding relationship between each value of the first size, each value of the second size, and the number of the die.

[0011] According to a specific implementation of an embodiment of the present application, the second determining module comprises: a first determining submodule configured to determine an initial first size and an initial second size; and a second determining submodule configured to determine the first variation range of the first size and the second variation range of the second size according to a preset variation ratio of the first size, a preset variation ratio of the second size, the initial first size, and the initial second size.

[0012] According to a specific implementation of an embodiment of the present application, the first determining submodule is specifically configured to: determine an area of the die according to a number of gate levels on the die; and determine the initial first size and the initial second size according to a size of an IP module on the die and the area of the die.

[0013] According to a specific implementation of an embodiment of the present application, the reference providing module comprises: a third determining submodule configured to: determine, according to the corresponding relationship between each value of the first size, each value of the second size, and the number of the die, a value of the first size and a value of the second size of the die under a preset number, so that an area of the die is at a maximum value under the preset number; or, determine a first optional range of a first preset value of the first size and a second optional range of a second preset value of the second size according to the corresponding relationship between each value of the first size, each value of the second size, and the number of the die; and determine, according to the corresponding relationship between each value of the first size, each value of the second size, and the number of the die, a maximum value of the number of the die and corresponding values of the first size and the second size in the first optional range and the second optional range.

[0014] According to a specific implementation manner of the embodiment of the present application, the apparatus further comprises a display module configured to, before the third determining submodule determines the first size of the crack piece and the second size of the crack piece under the preset quantity, display the correspondence between each value of the first size and each value of the second size and the quantity of the crack pieces under each value of the first size on a graphical user interface according to the correspondence between each value of the first size and each value of the second size and the quantity of the crack pieces under each value of the first size.

[0015] According to a specific implementation manner of the embodiment of the present application, the third determining submodule is specifically configured to: determine the maximum value of the second size of the crack piece under the preset quantity according to the displayed correspondence between each value of the first size and each value of the second size and the quantity of the crack pieces under each value of the first size; and determine the value of the first size corresponding to the maximum value of the second size and the preset quantity.

[0016] In a third aspect, the embodiment of the present application provides an electronic device, which comprises a shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the shell, the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; and the processor is configured to run programs corresponding to the executable program codes by reading the executable program codes stored in the memory, so as to execute the chip design method in any of the foregoing implementation manners.

[0017] In a fourth aspect, the embodiment of the present application provides a computer readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method in any of the foregoing implementation manners.

[0018] The chip design method, apparatus, electronic device and readable storage medium of the embodiment can determine the first change range and the first change step of the first size of the crack piece and the second change range and the second change step of the second size of the crack piece, and determine the quantity of the crack pieces arranged in the wafer corresponding to each value of the first size and each value of the second size according to the determined process parameters and wafer size, so that the correspondence between each value of the first size and each value of the second size and the quantity of the crack pieces can be used as a reference for the layout of the crack pieces on the wafer, thereby facilitating the improvement of the chip design efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained on the basis of these drawings without any creative effort.

[0020] Figure 1 The flowchart of the chip design method provided by an embodiment of the present application is shown in the figure.

[0021] Figure 2 The reference diagram of the split chip arranged on the wafer in an embodiment of the present application is shown in the figure.

[0022] Figure 3 The effective split chip of type 1 in the figure is shown in the figure. Figure 2

[0023] The waste chip of type 2 in the figure is shown in the figure. Figure 4 Figure 2 The waste chip of type 3 in the figure is shown in the figure.

[0024] Figure 5 Figure 2 The schematic diagram of the slicing groove of an embodiment of the present application is shown in the figure.

[0025] Figure 6 The flowchart of a specific embodiment of the present application is shown in the figure.

[0026] Figure 7 The flowchart of determining the initial value of the width and height of the chip in a specific embodiment of the present application is shown in the figure.

[0027] Figure 8 The flowchart of drawing the change curve in a specific embodiment of the present application is shown in the figure.

[0028] Figure 9 The flowchart of drawing the change curve in a specific embodiment of the present application is shown in the figure.

[0029] Figure 10 The curve shown in a specific embodiment of the present application is shown in the figure.

[0030] Figure 11 The structural diagram of the chip design device provided by an embodiment of the present application is shown in the figure.

[0031] Figure 12 The structural diagram of the electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0032] ​​The embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0033] In order for those skilled in the art to better understand the technical concepts, implementation schemes and beneficial effects of the embodiments of the present application, the following will be described in detail through specific embodiments.

[0034] An embodiment of the present application provides a chip design method, comprising: determining a process parameter of wafer slicing and a size of a wafer; determining a first change range and a first change step of a first size of a wafer piece, and determining a second change range and a second change step of a second size of the wafer piece; wherein the first size is a width, and the second size is a height; or, the first size is a height, and the second size is a width; determining, according to the process parameter and the wafer size, a number of wafer pieces arranged in the wafer corresponding to each value of the second size in the second change range and the second change step, under each value of the first size in the first change range and the first change step, and providing a reference for the layout of the wafer piece on the wafer according to the corresponding relationship between each value of the first size, each value of the second size and the number of wafer pieces, so as to improve the chip design efficiency.

[0035] Figure 1 A flowchart of the chip design method provided by an embodiment of the present application is shown in FIG. 1, which can include the following steps. Figure 1

[0036] S101, determining a process parameter of wafer slicing and a size of a wafer.

[0037] A wafer is a basic base for chip production, which is obtained by cutting and polishing a crystal cylinder, and can refer to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit. Since the wafer is circular in shape, it is called a wafer. Various circuit element structures can be processed and manufactured on the silicon wafer to become an integrated circuit product with specific electrical functions. The raw material of the wafer is silicon. In the embodiments, the wafer can be represented by a planar circle, and the size of the wafer can be the size of the planar circle.

[0038] Wafer slicing technology can be a process of cutting an integrated circuit, which can be simply abstracted as printing a plurality of fixed patterns on a planar circle (wafer), and then cutting each single pattern (which can generally be a square).

[0039] Referring to FIG. 2, a wafer slicing process can include the following steps. Figures 2-6 ​In the production process of wafer slicing, edge loss and single-sided loss will occur due to mechanical shaking, mechanical fixing requirements, etc., which will cause the local internal pattern to be incomplete, resulting in waste pieces, and the chip cutting cannot be done to 0 width cutting, so there is a corresponding scribe groove to ensure that the single chip will not be damaged during cutting. The above parameters can be referred to as process parameters, which can be determined by the selected foundry. When the chip design enters the physical design stage, the production process parameters need to be determined.

[0040] S102, determine a first change range and a first change step of a first size of the split piece, and determine a second change range and a second change step of a second size of the split piece.

[0041] The shape of the split piece can be rectangular or positive direction. In some examples, the first size is the width and the second size is the height; in other examples, the first size is the height and the second size is the width.

[0042] The split piece in the embodiment can refer to a single chip cut from a wafer.

[0043] The first change range can be represented by a minimum value to a maximum value, the first change step can be the minimum value of the change of the first size, and the second change range and the second change step can refer to the first change range and the first change step.

[0044] S103, according to the process parameters and the wafer size, determine the number of split pieces arranged in the wafer corresponding to each value of the second size in the second change range and the second change step, under each value of the first size in the first change range and the first change step.

[0045] According to the process parameters and the wafer size of S101, the number of split pieces arranged in the wafer corresponding to each value of the second size in the second change range and the second change step, under each value of the first size in the first change range and the first change step can be determined.

[0046] When a group of first size values and second size values are determined under the condition that the process parameters and the wafer size are determined, the number of split pieces that can be arranged on the wafer can be obtained,

[0047] In the embodiment, the first size can be in a certain value in the first change range, and the number of the split pieces corresponding to each value of the second size in the second change range and changed by the second change step can be obtained. The first size can be in another value changed by the first change step, and the number of the split pieces corresponding to each value of the second size in the second change range and changed by the second change step can be obtained. According to the above rule, the number of the split pieces arranged in the wafer corresponding to each value of the second size in the second change range and changed by the second change step can be calculated under each value of the first size in the first change range and changed by the first change step.

[0048] In S104, the layout of the split pieces on the wafer is provided with reference according to the correspondence between each value of the first size, each value of the second size and the number of the split pieces.

[0049] According to the correspondence between each value of the first size, each value of the second size and the number of the split pieces, the change value of the number of the split pieces when the first size and the second size change can be obtained, and the changeable range of the first size and the second size when the number of the split pieces is certain can also be obtained. Therefore, the layout of the split pieces on the wafer can be provided with reference.

[0050] In the embodiment, the first change range of the first size of the split piece and the second change range of the second size of the split piece are determined, and the number of the split pieces arranged in the wafer corresponding to each value of the second size in the second change range and changed by the second change step can be calculated under each value of the first size in the first change range and changed by the first change step according to the determined process parameters and wafer size. Therefore, the layout of the split pieces on the wafer can be provided with reference according to the correspondence between each value of the first size, each value of the second size and the number of the split pieces. Thus, the chip design efficiency can be improved, and the problem of low chip design efficiency caused by the lack of reference for the layout of the split pieces on the wafer in the prior art can be avoided.

[0051] In an embodiment of the present application, the first change range of the first size of the split piece and the second change range of the second size are determined, including:

[0052] In S102a, the initial first size and the initial second size are determined.

[0053] In some examples, the initial first size and the initial second size can be determined (S102a), including:

[0054] A1, the area of the split piece is determined according to the number of gate levels on the split piece.

[0055] The semiconductor device is printed on the die before the die is cut from the wafer to realize the function of the die (chip), and therefore the area of the die should at least be able to carry the semiconductor device printed on the die. In some embodiments, the area of the die can be estimated according to the number of gates obtained in the behavioral design stage.

[0056] A2, determining the initial first size and the second size according to the size of the IP module on the die and the area of the die.

[0057] The IP (Intellectual Property) core module can be a pre-designed, even verified integrated circuit, device or component with certain determined function, which can be assembled or integrated by chip designers. In this embodiment, the initial values of the first size and the second size can be determined according to the IP module on the die and the area of the die.

[0058] S102b, determining the first change range of the first size and the second change range of the second size according to the preset change ratio of the first size, the preset change ratio of the second size, the initial first size and the initial second size.

[0059] The change range of the first size can be determined according to the preset change ratio of the first size and the initial first size. Specifically, the initial first size can be multiplied by the change ratio to obtain the change range of the first size. The change ratio can be greater than 1 or less than 1. Specifically, according to the possible adjustment of the size of the die in the late chip design, the change ratio less than 1 and the change ratio greater than 1 can be selected, such as 0.9 and 1.1. That is, the initial first size is multiplied by 0.9 and 1.1 respectively to obtain two numerical values as the two endpoints of the change range of the first size. The change range of the first size is composed of the two endpoints and the numerical values between the two endpoints.

[0060] The determination of the change range of the second size is similar to the determination of the change range of the first size.

[0061] In order to improve the utilization rate of the wafer, an embodiment of the present application is basically the same as the above-mentioned embodiment, except that the embodiment provides a reference for the layout of the die on the wafer according to the correspondence between each numerical value of the first size, each numerical value of the second size and the number of dies (S104), which comprises:

[0062] S104a, determining the numerical value of the first size and the numerical value of the second size of the die under the preset number according to the correspondence between each numerical value of the first size, each numerical value of the second size and the number of dies, so that the area of the die is at a maximum under the preset number.

[0063] Since the first size is at a value, a corresponding relationship between each value of the second size and the number of splits can be determined, and the first size can change in a first change range with a first change step, that is, the value of the first size can be multiple, so that multiple corresponding relationships between each value of the second size and the number of splits can be obtained. Further, when the number of splits is a preset number, multiple sets of values of the first size and the second size can be obtained. For one set of values of the first size and the second size, there is still a space for fine adjustment. At this time, according to the corresponding relationship between each value of the second size and the number of splits, a maximum value of the second size can be determined under the condition that the number of splits is the preset number and the value of the first size is unchanged. In this way, multiple sets of values of the first size and the maximum value of the second size can be obtained, and each set of values of the first size and the maximum value of the second size can make the area of the splits be at a maximum value under the predetermined number of splits.

[0064] The utilization rate of the wafer is equal to the product of the number of splits and the area of a single split divided by the area of the wafer. When the number of splits is constant, the larger the area of a single split is, the higher the utilization rate of the wafer is. Each set of values of the first size and the maximum value of the second size can make the area of the splits be at a maximum value under the predetermined number of splits, that is, the size of the chip is increased. In this way, each set of values of the first size and the maximum value of the second size can make the utilization rate of the wafer be higher when the number of splits is predetermined.

[0065] In order to facilitate the use of designers and provide a user experience, before determining the values of the first size and the second size of the splits under the preset number of splits, the method further includes, in some examples:

[0066] S104b, according to the corresponding relationship between each value of the first size and each value of the second size and the number of splits, the corresponding relationship between each value of the second size and the number of splits under each value of the first size is displayed on a graphical user interface with the second size as a first coordinate and the number of splits as a second coordinate.

[0067] The corresponding relationship between each value of the second size and the number of splits under each value of the first size can be displayed using different display elements, for example, different display elements can be used to display different values of the first size.

[0068] The first coordinate can be the abscissa, and the second coordinate can be the ordinate; or the first coordinate can be the ordinate, and the second coordinate can be the abscissa.

[0069] In the embodiment, the correspondence between the second size and the number of the chips is displayed on the graphical user interface with the second size as the first coordinate and the number of the chips as the second coordinate, so that the chip width and height can be suggested for the initial chip layout adjustment, and the impact of the chip size adjustment can be displayed, and the adjustable range of the chip size can be observed earlier and more intuitively.

[0070] In order to improve the design efficiency of the chip, in some examples, the first size and the second size of the chip under the preset number of the chips are determined by:

[0071] B1, the maximum value of the second size of the chip under the preset number of the chips is determined according to the correspondence between the second size and the number of the chips under each value of the first size.

[0072] In the graph of the correspondence between the second size and the number of the chips under one value of the first size, the maximum value of the second size of the chip under the preset number of the chips is at the inflection point of the graph, so that the maximum value of the second size of the chip under the preset number of the chips can be determined more conveniently according to the correspondence between the second size and the number of the chips under one value of the first size.

[0073] B2, the value of the first size corresponding to the maximum value of the second size and the preset number is determined.

[0074] The cost of one-time flow sheet of the chip is very high when the chip is produced, and the more the number of the chips on the layout of the wafer, the lower the cost of the single chip, so as to facilitate the reduction of the cost of the single chip, in some examples, the layout of the chip on the wafer is provided with reference according to the correspondence between the first size and the number of the chips under each value of the second size, including:

[0075] C1, the first optional range of the first predetermined value of the first size and the second optional range of the second predetermined value of the second size are determined according to the correspondence between the first size and the number of the chips under each value of the second size.

[0076] In the chip design process, the first size and the second size can be determined according to the correspondence between the first size and the number of the chips under each value of the second size, and as the physical implementation advances, the first predetermined value of the first size and the second predetermined value of the second size can be determined when the size needs to be modified, and similarly, the first optional range of the first predetermined value and the second optional range of the second predetermined value can be determined according to the correspondence between the first size and the number of the chips under each value of the second size.

[0077] C2, according to the correspondence between each value of the first size, each value of the second size and the number of splits, determining the maximum value of the number of splits and the corresponding value of the first size and the value of the second size in the first optional range and the second optional range.

[0078] According to the correspondence between each value of the first size, each value of the second size and the number of splits, the maximum value of the number of splits is determined in the first optional range and the second optional range, and the first value and the second size value corresponding to the maximum value of the number of splits are selected to continue the subsequent physical design of the chip.

[0079] In the following, a specific embodiment is used to explain the scheme of the present application in detail.

[0080] Referring to Figure 7 , the chip design method of the embodiment can include:

[0081] S1: determining production parameters.

[0082] Including wafer size, slice slot size, edge loss parameter and single side loss.

[0083] S2: determining the theoretical minimum area of the chip to obtain the initial value of the width and height of the chip.

[0084] Second, according to important factors such as front-end design and IP, the height (DH) and width (DW) of the chip are determined, and referring to Figure 8 , the determination of the theoretical minimum area of the chip to obtain the initial value of the width and height of the chip (S2) includes:

[0085] S21, the number of gate levels is obtained by behavioral design to obtain the estimated area.

[0086] S22, considering the size requirement of important elements such as IP.

[0087] S23, obtaining the initial value of the width and height of the chip.

[0088] S3: selecting the scanning range of width and height, calculating the corresponding number of splits at different width and height, and drawing the change curve.

[0089] According to the adjustment expectation, the scanning range and scanning step of the width and height of the chip are selected, the range of DH is scanned for each selected scanning width DWS, the change curve of the number of splits in the process of DH change under different DWS is obtained, and referring to Figure 9 and Figure 10 , selecting the scanning range of width and height, calculating the corresponding number of splits at different width and height, and drawing the change curve (S3) can include:

[0090] S31, according to the adjustment of the late consideration, the selection of scanning range.

[0091] For example, the scanning range can be from 0.9 times to 1.1 times of the initial value of the width and height, with a step of 1 nm.

[0092] S32, according to a selected DW, the DH is scanned to obtain a curve of the number of fragments changing with the change of DH.

[0093] S33, the step of S32 is repeated several times according to the selected value of S31 to obtain a plurality of curves of the number of fragments changing with the change of DH.

[0094] The curve of the number of fragments corresponding to each DW changing with the change of DH can be displayed on the graphical user interface.

[0095] S4, the analysis of the change curve provides a reference for chip design.

[0096] The convex point of the change curve is analyzed to obtain the best area, and the curve analysis can be performed to select the maximum extreme point of the area near DW and DH, wherein an embodiment is to analyze a single curve (fixed DW), and the inflection point of each step is the best area point (DH maximization) under the current number of fragments.

[0097] Another embodiment can comprehensively consider a plurality of curves, and the corresponding convex point on the same fragment quantity axis is a selectable scheme.

[0098] Another embodiment, when DW and DH are selected, the trend of different curves can also be a preview of the change of the number of fragments caused by the adjustment of the width and height.

[0099] In actual use, the implementation process of the above steps can be placed in the tool, so that the personnel responsible for the top-level design of the chip can scan and view the change of the number of fragments after the layout adjustment at any time; each adjustment can find the best area point as soon as possible to improve the utilization rate.

[0100] An embodiment of the present application provides a chip design device, which comprises: a first determining module configured to determine a process parameter of wafer slicing and a size of a wafer; a second determining module configured to determine a first variation range and a first variation step of a first size of a wafer piece, and determine a second variation range and a second variation step of a second size of the wafer piece; wherein the first size is width, and the second size is height; or the first size is height, and the second size is width; a third determining module configured to determine, according to the process parameter and the wafer size, a number of the wafer pieces arranged in the wafer corresponding to each value of the second size in the second variation range and the second variation step, under each value of the first size in the first variation range and the first variation step; and a reference providing module configured to provide reference for layout of the wafer piece on the wafer according to a corresponding relationship among each value of the first size, each value of the second size and the number of the wafer pieces, so as to improve chip design efficiency.

[0101] Figure 11 A structural schematic diagram of the chip design device provided by an embodiment of the present application is shown in FIG. 1. Figure 11 As shown in FIG. 1, the chip design device of the embodiment can comprise: a first determining module 11 configured to determine a process parameter of wafer slicing and a size of a wafer; a second determining module 12 configured to determine a first variation range and a first variation step of a first size of a wafer piece, and determine a second variation range and a second variation step of a second size of the wafer piece; wherein the first size is width, and the second size is height; or the first size is height, and the second size is width; a third determining module 13 configured to determine, according to the process parameter and the wafer size, a number of the wafer pieces arranged in the wafer corresponding to each value of the second size in the second variation range and the second variation step, under each value of the first size in the first variation range and the first variation step; and a reference providing module 14 configured to provide reference for layout of the wafer piece on the wafer according to a corresponding relationship among each value of the first size, each value of the second size and the number of the wafer pieces.

[0102] The device of the embodiment can be used to execute the technical solution of the method embodiment shown in FIG. 2, and the implementation principle and technical effects are similar, which will not be repeated here. Figure 1

[0103] ​The embodiment determines the first change range of the first size of the crack piece and the second change range of the second size of the crack piece, determines the crack piece number corresponding to each value of the second size in the second change range and the second change step, and determines the crack piece number corresponding to each value of the first size in the first change range and the first change step according to the determined process parameters and wafer size, so that the crack piece layout on the wafer can be provided with reference according to the corresponding relationship between each value of the first size, each value of the second size and the crack piece number, thereby facilitating the chip design efficiency and avoiding the problem of low chip design efficiency caused by the fact that the crack piece layout on the wafer has no reference in the prior art.

[0104] As an optional implementation, the second determining module comprises: a first determining submodule, configured to determine the initial first size and the initial second size; and a second determining submodule, configured to determine the first change range of the first size and the second change range of the second size according to the preset change ratio of the first size, the preset change ratio of the second size, the initial first size and the initial second size.

[0105] As an optional implementation, the first determining submodule is specifically configured to: determine the area of the crack piece according to the number of gate levels on the crack piece; and determine the initial first size and the initial second size according to the size of the IP module on the crack piece and the area of the crack piece.

[0106] As an optional implementation, the reference providing module comprises: a third determining submodule, configured to determine the value of the first size and the value of the second size of the crack piece under a preset number according to the corresponding relationship between each value of the first size, each value of the second size and the crack piece number, so that the area of the crack piece is at a maximum value under the preset number; or configured to: determine a first optional range of a first predetermined value of the first size and a second optional range of a second predetermined value of the second size according to the corresponding relationship between each value of the first size, each value of the second size and the crack piece number; and determine the maximum value of the crack piece number and the corresponding value of the first size and the value of the second size in the first optional range and the second optional range according to the corresponding relationship between each value of the first size, each value of the second size and the crack piece number.

[0107] As an optional implementation, the apparatus further comprises a display module configured to, before the third determining submodule determines the preset number of the fragments, the maximum value of the second dimension of the fragments, and the value of the first dimension corresponding to the maximum value of the second dimension and the preset number, display, according to the correspondence between each value of the first dimension and each value of the second dimension of the fragments corresponding to each number of the fragments, the correspondence between each value of the first dimension and each value of the second dimension of the fragments corresponding to each number of the fragments on a graphical user interface, taking the second dimension as a first coordinate and the number of the fragments as a second coordinate.

[0108] As an optional implementation, the third determining submodule is specifically configured to: determine, according to the displayed correspondence between each value of the first dimension and each value of the second dimension of the fragments corresponding to each number of the fragments, the preset number of the fragments, the maximum value of the second dimension of the fragments, and the value of the first dimension corresponding to the maximum value of the second dimension and the preset number.

[0109] The apparatuses in the above embodiments can be used to execute the technical solutions of the above method embodiments, and have similar implementation principles and technical effects, which will not be described here.

[0110] Figure 12 As shown in a structural schematic diagram of an electronic device provided by an embodiment of the present application, Figure 12 the electronic device can include a housing 61, a processor 62, a memory 63, a circuit board 64, and a power supply circuit 65, wherein the circuit board 64 is arranged inside a space enclosed by the housing 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; the power supply circuit 65 is configured to supply power to each circuit or device of the electronic device; the memory 63 is configured to store executable program codes; and the processor 62 is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory 63, and execute any chip design method provided by the above embodiments, thus achieving the corresponding beneficial technical effects, which have been described in detail above and will not be described here.

[0111] The above electronic device exists in various forms, including but not limited to:

[0112] (1) Mobile communication device: This type of device is characterized by having mobile communication function and providing voice and data communication as the main target. This type of terminal includes smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones.

[0113] (2) Ultra-mobile personal computer device: This type of device belongs to the category of personal computers and has computing and processing functions, and generally also has the feature of mobile Internet. This type of terminal includes PDA, MID, and UMPC devices, such as iPad.

[0114] (3) Server: a device providing computing services, the configuration of the server includes a processor, a hard disk, a memory, a system bus, etc., the server is similar to a general computer architecture, but since it needs to provide high-reliable services, it has higher requirements in processing capability, stability, reliability, security, scalability, manageability, etc.

[0115] (4) Other electronic devices with data interaction function.

[0116] Correspondingly, the embodiment of the application also provides a computer readable storage medium, the computer readable storage medium stores one or more programs, the one or more programs can be executed by one or more processors to implement the chip design method provided by any of the foregoing embodiments, so as to achieve the corresponding technical effects, which have been described in detail in the foregoing, and will not be described here.

[0117] It should be noted that, in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements does not only include those elements, but also includes other elements not explicitly listed or other elements inherent to such process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0118] Each embodiment in the specification is described in a relevant manner, and the same and similar parts between each embodiment can be referred to each other, and each embodiment mainly explains the difference from other embodiments.

[0119] Especially, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0120] For the convenience of description, the above device is described as various units / modules respectively described in function. Of course, in the implementation of the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0121] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware, and the program can be stored in a computer readable storage medium. When the program is executed, the program can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0122] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip design method, characterized in that, include: Determine the process parameters and wafer dimensions for wafer slicing; A first variation range and a first variation step size of a first dimension of a cleavage are determined, and a second variation range and a second variation step size of a second dimension of the cleavage are determined; wherein, the first dimension is the width and the second dimension is the height; or, the first dimension is the height and the second dimension is the width; Based on the process parameters and the wafer size, determine the number of diced wafers arranged in the wafer corresponding to each value obtained by changing the first size within the first variation range with the first variation step size, and the number of diced wafers arranged in the wafer within the second variation range with the second variation step size, for each value obtained by changing the second size within the second variation range. Based on the correspondence between each value of the first dimension, each value of the second dimension, and the number of cleavages, a reference is provided for the layout of the cleavages on the wafer; The step of providing a reference for the layout of the cleavages on the wafer based on the correspondence between each value of the first dimension, each value of the second dimension, and the number of cleavages includes: Based on the correspondence between each value of the first dimension, each value of the second dimension, and the number of cleavages, determine the values ​​of the first dimension and the second dimension of the cleavages at a preset number, so that the area of ​​the cleavages is at its maximum value at the preset number; or, Based on the correspondence between each value of the first dimension, each value of the second dimension and the number of cleavages, a first selectable range of a first predetermined value of the first dimension and a second selectable range of a second predetermined value of the second dimension are determined; based on the correspondence between each value of the first dimension, each value of the second dimension and the number of cleavages, the maximum value of the number of cleavages and the corresponding values ​​of the first dimension and the second dimension are determined within the first selectable range and the second selectable range.

2. The method according to claim 1, characterized in that, The determination of the first range of variation of the first size of the cleavage and the determination of the second range of variation of the second size include: Determine the initial first dimension and the initial second dimension; Based on the preset change ratio of the first dimension, the preset change ratio of the second dimension, the initial first dimension, and the initial second dimension, a first change range of the first dimension and a second change range of the second dimension are determined.

3. The method according to claim 2, characterized in that, Determining the initial first dimension and the initial second dimension includes: The area of ​​the fragment is determined based on the number of gates on the fragment; The initial first size and the initial second size are determined based on the size of the IP module on the cleavage and the area of ​​the cleavage.

4. The method according to claim 1, characterized in that, Before determining the values ​​of the first dimension and the second dimension of the cleavage at a preset number, the method further includes: Based on the correspondence between each value of the first dimension, each value of the second dimension, and the number of cleavages, the graphical user interface displays the correspondence between each value of the second dimension and the number of cleavages for each value of the first dimension, with the second dimension as the first coordinate and the number of cleavages as the second coordinate.

5. The method according to claim 4, characterized in that, Determining the values ​​of the first dimension and the second dimension of the cleavage within a preset number of cleavages includes: Based on the correspondence between each value of the second dimension and the number of shards for each value of the first dimension shown, the maximum value of the second dimension of the shards is determined for a preset number of shards. Determine the value of the first dimension corresponding to the maximum value of the second dimension and the preset quantity.

6. A chip design apparatus, characterized in that, include: The first determining module is used to determine the process parameters and wafer dimensions for wafer slicing; The second determining module is used to determine a first variation range and a first variation step size of the first dimension of the cleavage, and to determine a second variation range and a second variation step size of the second dimension of the cleavage; wherein the first dimension is the width and the second dimension is the height; or, the first dimension is the height and the second dimension is the width; The third determining module is used to determine, based on the process parameters and the wafer size, the number of diced wafers arranged in the wafer corresponding to each value obtained by changing the first dimension within the first variation range with the first variation step size, and each value obtained by changing the second dimension within the second variation range with the second variation step size. A reference providing module is used to provide a reference for the layout of the cleavages on the wafer based on the correspondence between each value of the first dimension, each value of the second dimension and the number of cleavages; The reference providing module includes: The third determining submodule is used to determine, based on the correspondence between each value of the first dimension, each value of the second dimension, and the number of cleavages, the values ​​of the first dimension and the second dimension of the cleavages at a preset number, so that the area of ​​the cleavages is at its maximum value at the preset number; or The method is used to determine a first selectable range of a first predetermined value of the first dimension and a second selectable range of a second predetermined value of the second dimension based on the correspondence between each value of the first dimension, each value of the second dimension and the number of fragments; and to determine the maximum value of the number of fragments and the corresponding values ​​of the first dimension and the second dimension within the first selectable range and the second selectable range based on the correspondence between each value of the first dimension, each value of the second dimension and the number of fragments.

7. The apparatus according to claim 6, characterized in that, The second determining module includes: A first determining submodule is used to determine the initial first dimension and the initial second dimension; The second determining submodule is used to determine a first variation range of the first dimension and a second variation range of the second dimension based on a preset variation ratio of the first dimension, a preset variation ratio of the second dimension, an initial first dimension, and an initial second dimension.

8. The apparatus according to claim 7, characterized in that, The first determining submodule is specifically used for: The area of ​​the fragment is determined based on the number of gates on the fragment; The initial first size and the initial second size are determined based on the size of the IP module on the cleavage and the area of ​​the cleavage.

9. The apparatus according to claim 6, characterized in that, The device further includes: The display module is used to, before the third determining submodule determines the value of the first dimension and the value of the second dimension of the cleavage under a preset number, display on a graphical user interface, with the second dimension as the first coordinate and the number of cleavages as the second coordinate, the correspondence between each value of the first dimension, each value of the second dimension and the number of cleavages under each value of the first dimension and the number of cleavages under each value of the second dimension, according to the correspondence between each value of the first dimension, each value of the second dimension and the number of cleavages under each value of the second dimension.

10. The apparatus according to claim 9, characterized in that, The third determining submodule is specifically used for: Based on the correspondence between each value of the second dimension and the number of shards for each value of the first dimension shown, the maximum value of the second dimension of the shards is determined for a preset number of shards. Determine the value of the first dimension corresponding to the maximum value of the second dimension and the preset quantity.

11. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the chip design method according to any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip design method according to any one of claims 1-5.

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