A data flow driven convolutional neural network accelerator

Abstract

The present invention relates to a data flow driven convolutional neural network accelerator, comprising: a preprocessing module, a convolution module, a pooling module and an instruction distribution module; the preprocessing module is used to load input features to perform preprocessing of the convolutional neural network; the convolution module is used to load weights, bias data and input features to perform calculations of the convolution layer, the fully connected layer or the nonlinear activation layer; the pooling module is used to load the calculation results of the convolution module to perform the calculation output of the pooling layer; the instruction distribution module is used to configure and control the working mode of the preprocessing module, the convolution module and the pooling module; under the working mode configuration and control of the instruction distribution module, according to the convolutional neural network structure, the preprocessing module, the convolution module and the pooling module are dynamically connected in a streaming structure; and the convolutional neural network acceleration processing of the input data is realized. The present invention improves the scalability of the CNN accelerator and improves the overall performance of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of deep learning acceleration circuits, and specifically relates to a data stream-driven convolutional neural network accelerator. Background Art

[0002] At present, deep learning technology represented by convolutional neural networks (CNN) has received widespread attention from academia and industry. A series of CNN models with deeper depth, more complex topology and higher accuracy have been proposed one after another. However, the control logic of existing deep learning processor architectures driven by control flow is relatively complex and lacks scalability, making it difficult to adapt to the rapid changes in CNN operator types, topology, network depth, etc. For example, the depth separation convolution layer that appears in MobileNet has a significant difference in calculation process from that of ordinary convolution layers; the ShortCut layer proposed in ResNet makes the network topology of CNN no longer a simple serial structure. Therefore, it has become a demand to design a convolutional neural network accelerator architecture that can further enhance the computing performance of the system while improving scalability. Summary of the Invention

[0003] In view of the above analysis, the present invention aims to disclose a data flow-driven convolutional neural network accelerator, which implements different network layers and various data transmission functions in different modules and connects them through a streaming structure; while improving the scalability of the CNN accelerator, it further enhances the overall performance of the accelerator.

[0004] The present invention discloses a data flow driven convolutional neural network accelerator, comprising: a preprocessing module, a convolution module, a pooling module and an instruction distribution module;

[0005] The preprocessing module is used to load input features and perform preprocessing of the convolutional neural network;

[0006] The convolution module is used to load weights, bias data and input features to perform calculations of convolutional layers, fully connected layers or nonlinear activation layers;

[0007] The pooling module is used to load the calculation results of the convolution module and execute the calculation output of the pooling layer;

[0008] The instruction distribution module is used to configure and control the working modes of the preprocessing module, convolution module and pooling module under the control of the external master control instruction;

[0009] Under the working mode configuration and control of the instruction distribution module, the preprocessing module, the convolution module and the pooling module are dynamically connected in a streaming structure according to the convolutional neural network structure, thereby realizing the convolutional neural network accelerated processing of the input data.

[0010] Furthermore, under the configuration and control of the instruction distribution module, the dynamic streaming structure connection includes:

[0011] The structure of connecting the preprocessing module to the convolution module and bypassing the pooling module; connecting the convolution module to the pooling module and bypassing the preprocessing module; or retaining the structure of the convolution module bypassing the preprocessing module and the pooling module.

[0012] Furthermore, in a structure in which the preprocessing module is connected to the convolution module and the pooling module is bypassed, the preprocessing module is configured in a preprocessing mode, and the convolution module is configured in a processing mode of a convolution layer or a convolution layer + a nonlinear activation layer;

[0013] Connect the convolution module to the pooling module and bypass the preprocessing module. Configure the convolution module to the convolution layer or convolution layer + nonlinear activation layer processing mode, and configure the pooling module to a specific pooling mode.

[0014] In the structure of retaining the convolution module bypassing the preprocessing module and the pooling module, the convolution module is configured as a processing mode of convolution layer, fully connected layer, convolution layer + non-linear activation layer, or fully connected layer + non-linear activation layer.

[0015] Furthermore, it also includes a feature loader, a weight loader, a feature unloader and an external DRAM memory;

[0016] The feature loader is used to obtain input features from the external DRAM memory and load them into the connected preprocessing module or convolution module;

[0017] The weight loader is used to obtain weight and bias data from an external DRAM memory and load them into the convolution module;

[0018] The feature unloader is used to obtain feature data from the connected pooling module or convolution module and unload it to the external DRAM memory.

[0019] Furthermore, a first FIFO-A is connected between the feature loader and the preprocessing module, and a first FIFO-B is connected between the output end of the preprocessing module and the second input end of the convolution module;

[0020] A second FIFO-A is connected between the output end of the weight loader and the first input end of the convolution module, and a second FIFO-B is connected between the output end of the convolution module and the input end of the pooling module;

[0021] A third FIFO-A is connected between the input end of the feature unloader and the output end of the pooling module.

[0022] Furthermore, a first bypass is connected between the output end of the first FIFO-A and the input end of the first FIFO-B; the bypass is connected under the control of the instruction distribution module;

[0023] A second bypass is connected between the output end of the first FIFO-B and the output end of the convolution module; the bypass is connected under the control of the instruction distribution module;

[0024] A third bypass is connected between the output end of the second FIFO-B and the output end of the pooling module; the third bypass is connected under the control of the instruction distribution module.

[0025] Furthermore, FIFO-A has a data buffering function; FIFO-B has an inter-module data transmission function; and the data depth of FIFO-A is greater than that of FIFO-B.

[0026] Furthermore, both FIFO-A and FIFO-B are stream-structured FIFOs.

[0027] Furthermore, the modules are connected through a streaming structure FIFO; after the instruction distribution module configures the working mode of each controlled module, the running or blocking state of each module is driven by data; when the upper FIFO of the corresponding module is not empty and the lower FIFO is not full, the module enters the running state; otherwise, it enters the blocking state.

[0028] Furthermore, under the configuration and control of the instruction distribution module, the VGG-16 network structure is executed to perform convolutional neural network calculations; in the process of performing dynamic streaming structure connection, the following steps are included:

[0029] 1) Connect the preprocessing module to the convolution module through configuration, bypassing the pooling module;

[0030] The feature loader obtains input image features from the external DRAM memory, loads them into the preprocessing module for preprocessing, and then outputs them to the convolution module for one convolution layer. The feature unloader unloads the convolution result into the external DRAM memory;

[0031] 2) Connect the convolution module to the pooling module through configuration, bypassing the preprocessing module;

[0032] The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for one convolution layer, and then outputs it to the pooling module for pooling layer processing. The feature unloader unloads the pooling result into the external DRAM memory;

[0033] 3) By configuring the retained convolution module, the preprocessing module and the pooling module are bypassed;

[0034] The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for processing one convolution layer, and then the feature unloader unloads the convolution result to the external DRAM memory;

[0035] 4) Connect the convolution module to the pooling module through configuration, bypassing the preprocessing module;

[0036] The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for one convolution layer, and then outputs it to the pooling module for pooling layer processing. The feature unloader unloads the pooling result into the external DRAM memory;

[0037] 5) Repeat steps 3)-4) until the fully connected layer of the VGG-16 network structure;

[0038] 6) By configuring the retained convolution module, bypass the preprocessing module and the pooling module; and configure the convolution module as a fully connected layer;

[0039] The feature loader obtains the output of the previous layer from the external DRAM memory, loads it into the convolution module for a fully connected layer, and then the feature unloader unloads the fully connected result to the external DRAM memory;

[0040] 7) Repeat step 6) until the last fully connected layer of the VGG-16 network structure is completed and output.

[0041] The present invention can achieve at least one of the following beneficial effects:

[0042] This paper improves the scalability of CNN accelerators by standardizing the operator and data transmission functions within CNNs. It also improves overall system performance by streamlining and parallelizing the operation of each functional module. This enables FPGA-based CNN accelerators to efficiently adapt to the rapid changes in CNN operator types and topology. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0044] Figure 1 This is a schematic diagram of the connection principle of the convolutional neural network accelerator in an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of the network structure of the typical CNN model VGG-16 in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, which constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0047] One embodiment of the present invention discloses a data stream driven convolutional neural network accelerator, which is implemented with FPGA. Figure 1 As shown, it includes: preprocessing module, convolution module, pooling module and instruction distribution module;

[0048] The preprocessing module is used to load input features and perform preprocessing of the convolutional neural network;

[0049] The convolution module is used to load weights, bias data and input features to perform calculations of convolutional layers, fully connected layers or nonlinear activation layers;

[0050] The pooling module is used to load the calculation results of the convolution module and execute the calculation output of the pooling layer;

[0051] The instruction distribution module is used to configure and control the working modes of the preprocessing module, convolution module and pooling module under the control of the external master control instruction;

[0052] Under the working mode configuration and control of the instruction distribution module, the preprocessing module, the convolution module and the pooling module are dynamically connected in a streaming structure according to the convolutional neural network structure, thereby realizing the convolutional neural network accelerated processing of the input data.

[0053] In the CNN network model, the calculation methods of the convolutional layer and the fully connected layer are basically the same, and both can be abstracted as matrix-vector multiplication operations, and can be implemented by reusing the same set of hardware circuits in the FPGA; the nonlinear activation layer generally follows the convolutional layer or the fully connected layer, and the calculation process is simple, so it can be integrated with the convolutional layer or the fully connected layer. Therefore, in the convolution module of this embodiment, a hardware circuit that can realize the convolutional layer, the fully connected layer, the convolutional layer + the nonlinear activation layer, or the fully connected layer + the nonlinear activation layer is arranged. Under the working mode configuration and control of the instruction distribution module, the functions of the actual convolutional layer, the fully connected layer, the convolutional layer + the nonlinear activation layer, or the fully connected layer + the nonlinear activation layer are selected.

[0054] Since the pooling layer has many different calculation modes, such as maximum pooling and average pooling, and the pooling window size and pooling step size of different layers are also different, it is not suitable to be integrated with the convolution module, otherwise the scalability of the accelerator will be affected. Therefore, in the accelerator of this embodiment, a separate pooling module is set up to implement the pooling layer function;

[0055] Since the CNN network usually inputs images of large size (common sizes include 224×224, 416×416, 1024×1024, etc.), the preprocessing function has a large amount of computation and takes a long time to calculate in the CPU. Therefore, it is suitable to perform hardware acceleration in the FPGA. However, the preprocessing function varies depending on the algorithm and application scenario. To improve the scalability of the system, a separate preprocessing module is set in the accelerator of this embodiment.

[0056] However, the post-processing function of the CNN network has a small amount of computation and involves a large number of floating-point operations, so it is not suitable for implementation in FPGA hardware. In this embodiment, the final output data of the accelerator is output to the DSP or other modules suitable for floating-point operations through the corresponding interface for corresponding processing.

[0057] Specifically, under the configuration and control of the instruction distribution module, the dynamic streaming structure connection includes:

[0058] The structure of connecting the preprocessing module to the convolution module and bypassing the pooling module; connecting the convolution module to the pooling module and bypassing the preprocessing module; or retaining the structure of the convolution module bypassing the preprocessing module and the pooling module.

[0059] In a structure in which the preprocessing module is connected to the convolution module and the pooling module is bypassed, the preprocessing module is configured as a preprocessing mode, and the convolution module is configured as a processing mode of a convolution layer or a convolution layer + a nonlinear activation layer; the preprocessing mode is a mode corresponding to the preprocessing requirements of the input image.

[0060] Connect the convolution module to the pooling module and bypass the preprocessing module. Configure the convolution module to the convolution layer or convolution layer + nonlinear activation layer processing mode, and configure the pooling module to a specific pooling mode.

[0061] In the structure of retaining the convolution module bypassing the preprocessing module and the pooling module, the convolution module is configured as a processing mode of convolution layer, fully connected layer, convolution layer + non-linear activation layer, or fully connected layer + non-linear activation layer.

[0062] Typically, the data transmission method between the CNN accelerator and the off-chip storage varies depending on the on-chip bus protocol of the actual deployment platform. To improve the scalability of the system, this embodiment separates the data transmission function from the circuits of each computing function; it also includes a feature loader, a weight loader, a feature unloader, and an external DRAM memory;

[0063] The feature loader is used to obtain input features from the external DRAM memory and load them into the connected preprocessing module or convolution module;

[0064] The weight loader is used to obtain weight and bias data from an external DRAM memory and load them into the convolution module;

[0065] The feature unloader is used to obtain feature data from the connected pooling module or convolution module and unload it to the external DRAM memory.

[0066] The feature loader, weight loader and feature unloader are used to separately realize the loading of feature data, loading of weight and bias data and unloading of feature data, so that the computing module is independent of the specific bus protocol and has good portability.

[0067] More preferably, in this embodiment, the data transmission module is isolated from other modules in the system using structures such as FIFO, which can realize the operation of the data transmission module in different clock domains, thereby improving the matching degree between the data bandwidth and the computing rate; a data buffer can be added to the data transmission module to provide the computing module with an instantaneous bandwidth higher than the physical bandwidth upper limit.

[0068] Specifically, a first FIFO-A is connected between the feature loader and the preprocessing module, and a first FIFO-B is connected between the output end of the preprocessing module and the second input end of the convolution module;

[0069] A second FIFO-A is connected between the output end of the weight loader and the first input end of the convolution module, and a second FIFO-B is connected between the output end of the convolution module and the input end of the pooling module;

[0070] A third FIFO-A is connected between the input end of the feature unloader and the output end of the pooling module.

[0071] More specifically, a first bypass is connected between the output end of the first FIFO-A and the input end of the first FIFO-B; the bypass is connected under the control of the instruction distribution module;

[0072] Under the configuration of the instruction distribution module, when the first bypass is connected, the output end of the first FIFO-A is directly connected to the input end of the first FIFO-B, so that the preprocessing module is bypassed and does not participate in the accelerator's operation. When the first bypass is disconnected, the preprocessing module is connected to participate in the accelerator's operation.

[0073] More specifically, a second bypass is connected between the output end of the first FIFO-B and the output end of the convolution module; the bypass is connected under the control of the instruction distribution module;

[0074] Under the configuration of the instruction distribution module, when the second bypass is connected, the output end of the first FIFO-B is directly connected to the input end of the second FIFO-B, so that the convolution module is bypassed and does not participate in the accelerator's operation. When the first bypass is disconnected, the convolution module is connected to participate in the accelerator's operation.

[0075] A third bypass is connected between the output end of the second FIFO-B and the output end of the pooling module; the third bypass is connected under the control of the instruction distribution module.

[0076] Under the configuration of the instruction distribution module, when the third bypass is connected, the output end of the second FIFO-B is directly connected to the input end of the third FIFO-A, so that the pooling module is bypassed and does not participate in the accelerator's operation. When the third bypass is disconnected, the pooling module is connected to participate in the accelerator's operation.

[0077] Specifically, FIFO-A and FIFO-B are both streaming FIFOs. Modules are connected via streaming FIFOs. After the instruction dispatch module configures the operating mode of each controlled module, the running or blocking state of each module is driven by data. When the corresponding module's upper FIFO is not empty and the lower FIFO is not full, the module enters the running state; otherwise, it enters the blocking state.

[0078] Moreover, among the two types of FIFOs in the accelerator, FIFO-A has a greater data depth than FIFO-B. FIFO-A is used to connect the data transmission module and the computing module, and is generally deeper. Its larger data buffering capacity can provide the computing module with an instantaneous bandwidth higher than the physical bandwidth limit. FIFO-B is used to connect the computing module. Under the condition that the data throughput rates of each module are basically matched, there is no need for data buffering function, so its depth is shallower.

[0079] By placing FIFOs between each module, the data interfaces between modules within the accelerator are all FIFO interfaces, and the control interface is a handshake protocol interface. The system's external interface depends on the hardware platform's on-chip bus protocol. Common data transmission interfaces include the AXI interface, and the instruction transmission interface is the AXI-Lite interface. In short, the interfaces of each module within the system are simple and unified, facilitating the addition, deletion, and reordering of modules, thereby further improving system scalability. Furthermore, through configuration and control, the computing modules can be arranged upstream and downstream of the data flow as required, and modules can also work in parallel in a "pipelined" manner, resulting in higher overall system performance.

[0080] This embodiment also discloses a specific solution to achieve this, such as Figure 2The VGG-16 network structure shown in the figure is used to perform convolutional neural network calculations under the configuration and control of the instruction distribution module. The following steps are included in the process of dynamically connecting the streaming structure:

[0081] 1) Connect the preprocessing module to the convolution module through configuration, bypassing the pooling module;

[0082] The feature loader obtains input image features from the external DRAM memory, loads them into the preprocessing module for preprocessing, and then outputs them to the convolution module for one convolution layer. The feature unloader unloads the convolution result into the external DRAM memory;

[0083] 2) Connect the convolution module to the pooling module through configuration, bypassing the preprocessing module;

[0084] The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for one convolution layer, and then outputs it to the pooling module for pooling layer processing. The feature unloader unloads the pooling result into the external DRAM memory;

[0085] 3) By configuring the retained convolution module, the preprocessing module and the pooling module are bypassed;

[0086] The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for processing one convolution layer, and then the feature unloader unloads the convolution result to the external DRAM memory;

[0087] 4) Connect the convolution module to the pooling module through configuration, bypassing the preprocessing module;

[0088] The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for one convolution layer, and then outputs it to the pooling module for pooling layer processing. The feature unloader unloads the pooling result into the external DRAM memory;

[0089] 5) Repeat steps 3)-4) until the fully connected layer of the VGG-16 network structure;

[0090] 6) By configuring the retained convolution module, bypass the preprocessing module and the pooling module; and configure the convolution module as a fully connected layer;

[0091] The feature loader obtains the output of the previous layer from the external DRAM memory, loads it into the convolution module for a fully connected layer, and then the feature unloader unloads the fully connected result to the external DRAM memory;

[0092] 7) Repeat step 6) until the last fully connected layer of the VGG-16 network structure is completed and output.

[0093] The accelerator outputs the results to the corresponding processor for VGG-16 post-processing, completing the VGG-16 CNN neural network calculation.

[0094] In summary, the embodiments of the present invention utilize a method for modularizing the operator functions and data transmission functions within a CNN to improve the scalability of the CNN accelerator. By streamlining and parallelizing the operation of each functional module, the overall system performance is enhanced. This enables the FPGA-based CNN accelerator to efficiently adapt to the rapid changes in CNN operator types, topology, and other aspects.

[0095] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A data flow driven convolutional neural network accelerator, It is characterized in that include: Preprocessing module, convolution module, pooling module and instruction distribution module; The preprocessing module is used to load input features to perform preprocessing of the convolutional neural network; The convolution module is used to load weights, bias data and input features to perform calculations of convolutional layers, fully connected layers or non-linear activation layers; The pooling module is used to load the calculation results of the convolution module to perform the calculation output of the pooling layer; The instruction distribution module is used to configure and control the working mode of the preprocessing module, the convolution module and the pooling module under the control of the external master control instruction; Under the working mode configuration and control of the instruction distribution module, the preprocessing module, the convolution module and the pooling module are dynamically connected in a streaming structure according to the convolutional neural network structure; Realize the accelerated processing of convolutional neural network input data; Under the configuration and control of the instruction distribution module, the dynamic streaming structure connection includes: The structure of connecting the preprocessing module to the convolution module and bypassing the pooling module; the structure of connecting the convolution module to the pooling module and bypassing the preprocessing module; or retaining the structure of the convolution module bypassing the preprocessing module and the pooling module; In a structure in which a preprocessing module is connected to a convolution module and a pooling module is bypassed, the preprocessing module is configured as a preprocessing mode, and the convolution module is configured as a processing mode of a convolution layer or a convolution layer + a nonlinear activation layer; In the structure where the convolution module is connected to the pooling module and the preprocessing module is bypassed, the convolution module is configured as a processing mode of a convolution layer or a convolution layer + a nonlinear activation layer, and the pooling module is configured as a specific pooling mode; In the structure of retaining the convolution module bypassing the preprocessing module and the pooling module, the convolution module is configured as a processing mode of a convolution layer, a fully connected layer, a convolution layer + a non-linear activation layer, or a fully connected layer + a non-linear activation layer; It also includes a feature loader, a weight loader, a feature unloader, and an external DRAM memory; The feature loader is used to obtain input features from an external DRAM memory and load them into the connected preprocessing module or convolution module; The weight loader is used to obtain weight and bias data from an external DRAM memory and load them into the convolution module; The feature unloader is used to obtain feature data from the connected pooling module or convolution module and unload it to the external DRAM memory; A first FIFO-A is connected between the feature loader and the preprocessing module, and a first FIFO-B is connected between the output end of the preprocessing module and the second input end of the convolution module; A second FIFO-A is connected between the output end of the weight loader and the first input end of the convolution module, and a second FIFO-B is connected between the output end of the convolution module and the input end of the pooling module; A third FIFO-A is connected between the input end of the feature unloader and the output end of the pooling module; A first bypass is connected between the output end of the first FIFO-A and the input end of the first FIFO-B; the bypass is turned on under the control of the instruction distribution module; A second bypass is connected between the output end of the first FIFO-B and the output end of the convolution module; the bypass is connected under the control of the instruction distribution module; A third bypass is connected between the output end of the second FIFO-B and the output end of the pooling module; the third bypass is connected under the control of the instruction distribution module.

2. The convolutional neural network accelerator according to claim 1, It is characterized in that FIFO-A has data buffering function; FIFO-B has inter-module data transmission function; FIFO-A data depth is greater than FIFO-B.

3. The convolutional neural network accelerator according to claim 2, It is characterized in that The FIFO-A and FIFO-B are both stream structure FIFOs.

4. The convolutional neural network accelerator according to claim 3, It is characterized in that The modules are connected through a streaming structure FIFO; after the instruction distribution module configures the working mode of each controlled module, the running or blocking state of each module is driven by data; when the upper FIFO of the corresponding module is not empty and the lower FIFO is not full, the module enters the running state; otherwise, it enters the blocking state.

5. The convolutional neural network accelerator according to claim 4, It is characterized in that Under the configuration and control of the instruction distribution module, the network structure of VGG-16 is executed to perform convolutional neural network calculations; in the process of performing dynamic streaming structure connection, the following steps are included: 1) The preprocessing module is connected to the convolution module through configuration, bypassing the pooling module; The feature loader obtains input image features from the external DRAM memory, loads them into the preprocessing module for preprocessing, and then outputs them to the convolution module for one convolution layer. The feature unloader unloads the convolution result into the external DRAM memory; 2) Connect the convolution module to the pooling module through configuration, bypassing the preprocessing module; The feature loader obtains the convolution result of the previous convolution layer from the external DRAM memory, loads it into the convolution module for one convolution layer, and then outputs it to the pooling module for pooling layer processing. The feature unloader unloads the pooling result into the external DRAM memory. 3) By configuring the retained convolution module, the preprocessing module and the pooling module are bypassed; The feature loader obtains the convolution result output by the previous convolution layer from the external DRAM memory, loads it into the convolution module for processing one convolution layer, and then the feature unloader unloads the convolution result into the external DRAM memory; 4) Connect the convolution module to the pooling module through configuration, bypassing the preprocessing module; The feature loader obtains the convolution result of the previous convolution layer from the external DRAM memory, loads it into the convolution module for one convolution layer, and then outputs it to the pooling module for pooling layer processing. The feature unloader unloads the pooling result into the external DRAM memory. 5) Repeat steps 3)-4) until the fully connected layer of the VGG-16 network structure; 6) By configuring the retained convolution module, bypass the preprocessing module and the pooling module; and configure the convolution module as a fully connected layer; The feature loader obtains the output result of the previous layer from the external DRAM memory, loads it into the convolution module for a fully connected layer, and then the feature unloader unloads the fully connected result to the external DRAM memory; 7) Repeat step 6) until the last fully connected layer of the VGG-16 network structure is completed and output.

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