An 8T SRAM-based in-memory bidirectional row-column subtraction calculation circuit structure

Abstract

The present invention discloses a circuit structure for bidirectional row and column subtraction calculations within an 8T SRAM memory, comprising: an overall timing control module, a row address decoding module, a column address decoding module, a row word line selection module, a column word line selection module, an SRAM storage array, a row output module, and a column output module; the row address decoding module is connected to the row word line selection module, the column address decoding module is connected to the column word line selection module, and the row word line selection module, the column word line selection module, the row output module, and the column output module are respectively connected to the SRAM storage array; the unit weight is controlled by adjusting the width-to-length ratio of the word line transfer transistor of the 8-transistor SRAM cell to achieve subtraction calculations. The present invention can perform row subtraction and column subtraction calculations within the 8T SRAM memory, reduce the consumption during the transmission process, significantly reduce the power consumption, and enable the word lines of all SRAM cells to be simultaneously turned on for parallel calculation during subtraction calculations, greatly improving the data throughput rate during calculations.

Description

Technical Field

[0001] The present invention relates to the technical field of SRAM (Static Random Access Memory), and in particular to a two-way row-column subtraction calculation circuit structure in 8T SRAM (8T SRAM refers to an 8-transistor static random access memory). Background Art

[0002] Nowadays, we are in the big data era where everything is interconnected. The extremely high energy consumption and large time occupancy brought by the traditional von Neumann computing architecture undoubtedly become the biggest obstacle to the improvement of system performance. In order to address the memory wall of the von Neumann computing architecture and solve a series of problems brought by it, scientists have proposed a new type of computing architecture - in-memory computing architecture. In-memory computing (abbreviated as CIM) architecture embeds logic into the memory to reduce data transfer between the processor and the memory. The traditional CIM architecture is based on a memory cell composed of 6T or more transistors. The biggest difference between the CIM architecture and the traditional von Neumann computing architecture is that when performing data operations, the CIM architecture does not need to fetch data from the memory, thus avoiding multiple accesses to the memory cells, effectively reducing the energy consumption of data access, and increasing the throughput of the storage system. The proposed CIM architecture not only timely and effectively solves the dilemma of the von Neumann computing architecture, but also provides a new research direction for the memory design industry. In-memory computing does not need to transfer data to the processor and directly performs operations in the memory, so it greatly reduces the energy consumption of data access during the computing process, and at the same time improves the computing speed and energy efficiency.

[0003] Static random access memory has incomparable advantages such as high speed, low power consumption, and better compatibility with logic circuits, so it is widely used in caches. As the area occupied by the memory on the entire chip is getting larger and the proportion of the power consumption of the memory in the entire chip is constantly rising, the design of high-speed and low-power SRAM becomes more and more important. In in-memory computing, SRAM has always been one of the key research objects. In the prior art, the technologies for implementing in-memory computing in SRAM mainly include the following points:

[0004] (1) An absolute value of difference circuit is implemented by using multi-row reading and pulse width modulation. This circuit structure uses pulse modulation to make the discharge time of high-order cells longer and the discharge time of low-order cells shorter, achieving the effect of weighted reading, converting the traditional binary reading technology into a decimal value of reading multiple rows at a time, and improving the data reading efficiency.

[0005] (2) By modulating the WL pulse of the bit line to control the weighting of the values in the memory, a method is proposed to achieve multiplication by utilizing the charge sharing of capacitors, thereby improving the energy efficiency of data operations. However, when the number of rows in the storage array is large, the number of repeated operations increases, resulting in a decrease in the calculation speed.

[0006] (3) By using the word line voltage to control the high and low of the binary weights, different word line voltages correspond to different discharge capabilities of the unit to the bit line, realizing the conversion from binary to decimal modulus. However, it is more affected by the low signal-to-noise ratio of analog computing and has relatively large calculation errors.

[0007] For the above existing technologies, it is difficult to achieve high linearity, an additional weight modulation circuit is required, and the data throughput rate during calculation is low, and the operation takes a long time. In view of this, the present invention is specifically proposed. Summary of the Invention

[0008] The purpose of the present invention is to provide a subtraction calculation circuit structure with two-way row and column in an 8T SRAM memory to solve the above technical problems existing in the prior art. The present invention can realize row subtraction and column subtraction calculations in the 8T SRAM memory, reduce the consumption during the transmission process, greatly reduce the power consumption, and can simultaneously turn on the word lines of all SRAM cells for parallel calculation during subtraction calculation, greatly improving the data throughput rate during calculation and shortening the operation time.

[0009] The purpose of the present invention is achieved through the following technical solutions:

[0010] A subtraction calculation circuit structure with two-way row and column in an 8T SRAM memory, the subtraction calculation circuit includes: an overall timing control module, a row address decoding module, a column address decoding module, a row word line selection module, a column word line selection module, an SRAM storage array, a row output module, and a column output module; wherein:

[0011] The overall timing control module is respectively connected to the row address decoding module, the column address decoding module, the row word line selection module, the column word line selection module, the SRAM storage array, the row output module, and the column output module; the row address decoding module is connected to the row word line selection module, and the column address decoding module is connected to the column word line selection module;

[0012] The SRAM storage array is composed of a plurality of subtraction calculation unit modules Block4B;

[0013] The subtraction calculation unit module Block4B includes 4 four-word four-bit 8-transistor SRAM cells, 4 PMOS transistors, 4 capacitors, 4 transmission gates, 1 local left column bit line LBL, 1 local right column bit line LBLB, 1 local left row bit line LRBL, and 1 local right row bit line LRBLB; the 4 four-word four-bit 8-transistor SRAM cells are respectively denoted as CELL0 to CELL3, the 4 PMOS transistors are respectively denoted as P0 to P3, the 4 capacitors are respectively denoted as C0 to C3, and the 4 transmission gates are respectively denoted as TG0 to TG3;

[0014] The left column word line WLL0 of the four-word four-bit 8-transistor SRAM cell CELL0 is connected to the left column word line WLL0 output by the column word line selection module, the right column word line WLR0 of the four-word four-bit 8-transistor SRAM cell CELL0 is connected to the right column word line WLR0 output by the column word line selection module, the left row word line WLL_VICE0 of the four-word four-bit 8-transistor SRAM cell CELL0 is connected to the left row word line WLL_VICE0 output by the row word line selection module, and the right row word line WLR_VICE0 of the four-word four-bit 8-transistor SRAM cell CELL0 is connected to the right row word line WLR_VICE0 output by the row word line selection module;

[0015] The left column word line WLL1 of the four-word four-bit 8-transistor SRAM cell CELL1 is connected to the left column word line WLL1 output by the column word line selection module, the right column word line WLR1 of the four-word four-bit 8-transistor SRAM cell CELL1 is connected to the right column word line WLR1 output by the column word line selection module, the left row word line WLL_VICE1 of the four-word four-bit 8-transistor SRAM cell CELL1 is connected to the left row word line WLL_VICE1 output by the row word line selection module, and the right row word line WLR_VICE1 of the four-word four-bit 8-transistor SRAM cell CELL1 is connected to the right row word line WLR_VICE1 output by the row word line selection module;

[0016] The left column word line WLL2 of the four-word four-bit 8-transistor SRAM cell CELL2 is connected to the left column word line WLL2 output by the column word line selection module, the right column word line WLR2 of the four-word four-bit 8-transistor SRAM cell CELL2 is connected to the right column word line WLR2 output by the column word line selection module, the left row word line WLL_VICE2 of the four-word four-bit 8-transistor SRAM cell CELL2 is connected to the left row word line WLL_VICE2 output by the row word line selection module, and the right row word line WLR_VICE2 of the four-word four-bit 8-transistor SRAM cell CELL2 is connected to the right row word line WLR_VICE2 output by the row word line selection module;

[0017] The left column word line WLL3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the left column word line WLL3 output by the column word line selection module. The right column word line WLR3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the right column word line WLR3 output by the column word line selection module. The left row word line WLL_VICE3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the left row word line WLL_VICE3 output by the row word line selection module. The right row word line WLR_VICE3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the right row word line WLR_VICE3 output by the row word line selection module;

[0018] The left column bit line BL terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local left column bit line LBL. The right column bit line BLB terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local right column bit line LBLB. The left row bit line RBL terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local left row bit line LRBL. The right row bit line RBLB terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local right row bit line LRBLB;

[0019] The source of the PMOS transistor P0 is connected to the power supply VDD. The drain of the PMOS transistor P0 is connected to the global left column bit line GBL. The gate of the PMOS transistor P0 is connected to the precharge signal PRE. The source of the PMOS transistor P1 is connected to the power supply VDD. The drain of the PMOS transistor P1 is connected to the global right column bit line GBLB. The gate of the PMOS transistor P1 is connected to the precharge signal PRE. The source of the PMOS transistor P2 is connected to the power supply VDD. The drain of the PMOS transistor P2 is connected to the global left row bit line GRBL. The gate of the PMOS transistor P2 is connected to the precharge signal PRE. The source of the PMOS transistor P3 is connected to the power supply VDD. The drain of the PMOS transistor P3 is connected to the global right row bit line GRBLB. The gate of the PMOS transistor P3 is connected to the precharge signal PRE;

[0020] One end of the capacitor C0 is connected to the local left column bit line LBL, and the other end of the capacitor C0 is connected to GND. One end of the capacitor C1 is connected to the local right column bit line LBLB, and the other end of the capacitor C1 is connected to GND. One end of the capacitor C2 is connected to the local left row bit line LRBL, and the other end of the capacitor C2 is connected to GND. One end of the capacitor C3 is connected to the local right row bit line LRBLB, and the other end of the capacitor C3 is connected to GND;

[0021] The transmission gate TG0 connects the global left column bit line GBL and the local left column bit line LBL; the transmission gate TG1 connects the global right column bit line GBLB and the local right column bit line LBLB; the transmission gate TG2 connects the global left row bit line GRBL and the local left row bit line LRBL; the transmission gate TG3 connects the global right row bit line GRBLB and the local right row bit line LRBLB; both the global left column bit line GBL and the global right column bit line GBLB are connected to the column output module; both the global left row bit line GRBL and the global right row bit line GRBLB are connected to the row output module.

[0022] Preferably, the structure of the four-word-line four-bit-line 8-transistor SRAM cell includes: 6 NMOS transistors and 2 PMOS transistors. The 6 NMOS transistors are respectively denoted as N0 to N5, and the 2 PMOS transistors are respectively denoted as P4 to P5; the PMOS transistor P4 and the NMOS transistor N0 form the first inverter, the PMOS transistor P5 and the NMOS transistor N1 form the second inverter, and these two inverters are cross-coupled; the NMOS transistors N2, N3, N4, and N5 serve as transmission transistors; wherein, the source of the NMOS transistor N2 is connected to the BL end of the left column bit line, the gate of the NMOS transistor N2 is connected to the left row word line WLL, and the drain of the NMOS transistor N2 is connected to the storage node Q; the source of the NMOS transistor N3 is connected to the BLB end of the right column bit line, the gate of the NMOS transistor N3 is connected to the right row word line WLR, and the drain of the NMOS transistor N2 is connected to the storage node QB; the source of the NMOS transistor N4 is connected to the RBL end of the left row bit line, the gate of the NMOS transistor N4 is connected to the left column word line WLL_VICE, and the drain of the NMOS transistor N4 is connected to the storage node Q; the source of the NMOS transistor N5 is connected to the RBLB end of the right row bit line, the gate of the NMOS transistor N5 is connected to the right column word line WLR_VICE, and the drain of the NMOS transistor N5 is connected to the storage node QB.

[0023] Preferably, each of the transmission gates is controlled by the transmission gate control signals TGE and TGEB, and the control signals TGE and TGEB are generated by the corresponding control timing generation circuit.

[0024] Preferably, by adjusting the width-to-length ratio of the word line transmission transistors of each four-word-line four-bit-line 8-transistor SRAM cell, the weight of each four-word-line four-bit-line 8-transistor SRAM cell can be controlled, thereby realizing subtraction calculation.

[0025] Preferably, the width-to-length ratios of the word line transmission transistors of the four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are 1:2:4:8.

[0026] Preferably, the row word line selection module adopts a plurality of row word line selection sub - modules, and the overall timing control module is respectively connected to each row word line selection sub - module. Each row word line selection sub - module is responsible for providing a left row word line and a right row word line for each row of subtraction calculation unit modules Block4B; the column word line selection module adopts a plurality of column word line selection sub - modules, and the overall timing control module is respectively connected to each column word line selection sub - module. Each column word line selection sub - module is responsible for providing a left column word line and a right column word line for each column of subtraction calculation unit modules Block4B.

[0027] Compared with the prior art, the row - column bidirectional subtraction calculation circuit provided by the present invention based on 8T SRAM has a simple structure. It is composed of 4 four - word - line four - bit - line 8 - transistor SRAM units to form a 4 - bit binary row - column bidirectional subtraction calculation unit module Block4B. 4 - bit binary data is stored in 4 four - word - line four - bit - line 8 - transistor SRAM units. By adjusting the width - to - length ratio of the word - line transfer transistors of these 8 - transistor SRAM units, the unit weight is controlled, and row - column bidirectional subtraction calculation is realized without an additional weight modulation circuit. Moreover, the word lines of all units are turned on simultaneously, but the voltage of the turned - on word lines is only 0.25V, and the opening time per unit is 2ns for parallel calculation, greatly improving the data throughput rate during calculation, shortening the operation time, and being able to calculate within the 8 - transistor SRAM unit block without reading the data out of the SRAM, reducing the consumption during the transmission process, and thus greatly reducing the energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 It is the overall structure schematic diagram of the row - column bidirectional subtraction calculation circuit based on 8T SRAM provided by the embodiment of the present invention;

[0030] Figure 2 It is the structure schematic diagram of the 4 - bit binary subtraction calculation unit module Block4B composed of 4 four - word - line four - bit - line 8 - transistor SRAM units provided by the embodiment of the present invention;

[0031] Figure 3 It is the structure schematic diagram of the four - word - line 8 - transistor SRAM unit provided by the embodiment of the present invention;

[0032] Figure 4 It is the row subtraction working schematic diagram of the four - word - line 8 - transistor SRAM unit provided by the embodiment of the present invention;

[0033] Figure 5 Schematic diagram of column subtraction operation of the four - word - line 8 - tube SRAM cell provided by the embodiment of the present invention;

[0034] Figure 6 Operation timing diagram for column subtraction calculation in Embodiment 1 of the present invention;

[0035] Figure 7 Simulation result diagram of the difference obtained by column subtraction calculation for 4 - bit binary data provided by the embodiment of the present invention. Detailed implementation manners

[0036] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described; obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, which does not constitute a limitation to the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] First, the following explanations are given for the terms that may be used in this article:

[0038] The description of terms such as "comprising", "including", "containing", "having" or other similar semantics should be interpreted as non - exclusive inclusion. For example, including a certain technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article, etc.) should be interpreted as not only including the clearly listed certain technical feature element, but also including other well - known technical feature elements in the art that are not clearly listed.

[0039] The term "consisting of" means excluding any technical feature element that is not clearly listed. If this term is used in a claim, this term will make the claim a closed - type claim, so that it does not include technical feature elements other than the clearly listed technical feature elements, except for related conventional impurities. If this term only appears in a certain clause of a claim, then it only limits the elements clearly listed in that clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0040] The following provides a detailed description of the subtraction calculation circuit structure based on the 8T SRAM in-memory row-column bidirectional of the present invention. The content not described in detail in the present invention belongs to the prior art well-known to those skilled in the art. In the embodiments of the present invention, those not specified in specific conditions are carried out according to the conventional conditions in the art or the conditions recommended by the manufacturer. The reagents or instruments used in the embodiments of the present invention without indicating the manufacturer are all conventional products that can be obtained through commercial purchase.

[0041] As Figure 1 , Figure 2 and Figure 3 shown, a subtraction calculation circuit structure based on the 8T SRAM in-memory row-column bidirectional is an energy-efficient circuit structure for subtraction absolute value calculation. The subtraction calculation circuit includes: a global timing control module (GLOBAL CONTROL), a row address decoding module (ROW ADDR DECODE), a column address decoding module (COLUMN ADDRDECODER), a row word line selection module (WL_VICE SEL), a column word line selection module (WL SEL), an SRAM storage array (SRAMARRY), a row output module (ROW SA&ADC), and a column output module (CLOUMN SA&ADC). Among them:

[0042] The global timing control module is respectively connected to the row address decoding module, the column address decoding module, the row word line selection module, the column word line selection module, the SRAM storage array, the row output module, and the column output module.

[0043] The row address decoding module is connected to the row word line selection module, the row word line selection module is connected to the SRAM storage array, and the SRAM storage array is connected to the row output module; the column address decoding module is connected to the column word line selection module, the column word line selection module is connected to the SRAM storage array, and the SRAM storage array is connected to the column output module.

[0044] The SRAM storage array is composed of a number of subtraction calculation unit modules Block4B; the subtraction calculation unit module Block4B is a 4-bit binary subtraction calculation unit module Block4B; the subtraction calculation unit module Block4B includes 4 four-word-line four-bit-line 8-transistor SRAM cells, 4 PMOS transistors, 4 capacitors, 4 transmission gates, 1 local left column bit line LBL, 1 local right column bit line LBLB, 1 local left row bit line LRBL, and 1 local right row bit line LRBLB; the 4 four-word-line four-bit-line 8-transistor SRAM cells are respectively denoted as CELL0 to CELL3, the 4 PMOS transistors are respectively denoted as P0 to P3, the 4 capacitors are respectively denoted as C0 to C3, and the 4 transmission gates are respectively denoted as TG0 to TG3;

[0045] The left column word line WLL0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the left column word line WLL0 output by the column word line selection module, the right column word line WLR0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the right column word line WLR0 output by the column word line selection module, the left row word line WLL_VICE0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the left row word line WLL_VICE0 output by the row word line selection module, and the right row word line WLR_VICE0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the right row word line WLR_VICE0 output by the row word line selection module;

[0046] The left column word line WLL1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the left column word line WLL1 output by the column word line selection module, the right column word line WLR1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the right column word line WLR1 output by the column word line selection module, the left row word line WLL_VICE1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the left row word line WLL_VICE1 output by the row word line selection module, and the right row word line WLR_VICE1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the right row word line WLR_VICE1 output by the row word line selection module;

[0047] The left column word line WLL2 of the four-word line four-bit line 8-transistor SRAM cell CELL2 is connected to the left column word line WLL2 output by the column word line selection module, the right column word line WLR2 of the four-word line four-bit line 8-transistor SRAM cell CELL2 is connected to the right column word line WLR2 output by the column word line selection module, the left row word line WLL_VICE2 of the four-word line four-bit line 8-transistor SRAM cell CELL2 is connected to the left row word line WLL_VICE2 output by the column row line selection module, and the right row word line WLR_VICE2 of the four-word line four-bit line 8-transistor SRAM cell CELL2 is connected to the right row word line WLR_VICE2 output by the row word line selection module;

[0048] The left column word line WLL3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the left column word line WLL3 output by the column word line selection module, the right column word line WLR3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the right column word line WLR3 output by the column word line selection module, the left row word line WLL_VICE3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the left row word line WLL_VICE3 output by the row word line selection module, and the right row word line WLR_VICE3 of the four-word line four-bit line 8-transistor SRAM cell CELL3 is connected to the right row word line WLR_VICE3 output by the column row line selection module;

[0049] The left column bit line BL terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local left column bit line LBL, the right column bit line BLB terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local right column bit line LBLB, the left row bit line RBL terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local left row bit line LRBL, and the right row bit line RBLB terminals of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local right row bit line LRBLB;

[0050] The source of PMOS transistor P0 is connected to power supply VDD, the drain of PMOS transistor P0 is connected to global left column bit line GBL, the gate of PMOS transistor P0 is connected to precharge signal PRE, and the precharge signal PRE is generated by a precharge control timing generation circuit (the precharge control timing generation circuit is a common precharge control timing generation circuit in SRAM memory in the prior art); the source of PMOS transistor P1 is connected to power supply VDD, the drain of PMOS transistor P1 is connected to global right column bit line GBLB, the gate of PMOS transistor P1 is connected to precharge signal PRE; the source of PMOS transistor P2 is connected to power supply VDD, the drain of PMOS transistor P2 is connected to global left row bit line GRBL, the gate of PMOS transistor P2 is connected to precharge signal PRE; the source of PMOS transistor P3 is connected to power supply VDD, the drain of PMOS transistor P3 is connected to global right row bit line GRBLB, the gate of PMOS transistor P3 is connected to precharge signal PRE;

[0051] One end of capacitor C0 is connected to local left column bit line LBL, and the other end of capacitor C0 is connected to GND; one end of capacitor C1 is connected to local right column bit line LBLB, and the other end of capacitor C1 is connected to GND; one end of capacitor C2 is connected to local left row bit line LRBL, and the other end of capacitor C2 is connected to GND; one end of capacitor C3 is connected to local right row bit line LRBLB, and the other end of capacitor C3 is connected to GND;

[0052] Transfer gate TG0 connects global left column bit line GBL and local left column bit line LBL; transfer gate TG1 connects global right column bit line GBLB and local right column bit line LBLB; transfer gate TG2 connects global left row bit line GRBL and local left row bit line LRBL; transfer gate TG3 connects global right row bit line GRBLB and local right row bit line LRBLB; both global left column bit line GBL and global right column bit line GBLB are connected to the column output module; both global left row bit line GRBL and global right row bit line GRBLB are connected to the row output module.

[0053] Each four-word line four-bit line 8T SRAM cell is simultaneously connected to a pair of local row bit lines and a pair of local column bit lines. This pair of local row bit lines or this pair of local column bit lines are discharged to obtain different voltages according to the differences between the input data and the data in the four-word line four-bit line 8T SRAM cell. The calculation result is obtained by comparing the voltage differences between two global row bit lines or between two global column bit lines, thereby realizing in-row subtraction calculation or in-column subtraction calculation in the 8T SRAM memory.

[0054] Specifically, the subtraction calculation circuit based on the in-row and in-column bidirectional of the 8T SRAM memory may include the following implementation schemes:

[0055] (1) The row word line selection module provides one left row word line and one right row word line for each four-word line four-bit line 8-transistor SRAM cell, and the column word line selection module provides one left column word line and one right column word line for each four-word line four-bit line 8-transistor SRAM cell.

[0056] (2) The structure of the four-word line four-bit line 8-transistor SRAM cell includes: six NMOS transistors and two PMOS transistors. The six NMOS transistors are respectively denoted as N0 to N5, and the two PMOS transistors are respectively denoted as P4 to P5.

[0057] PMOS transistor P4 and NMOS transistor N0 form the first inverter, and PMOS transistor P5 and NMOS transistor N1 form the second inverter. These two inverters are cross-coupled, that is, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. This can lock and save the output states of the two inverters, that is, store the state of 1 bit.

[0058] NMOS transistors N2, N3, N4, and N5 serve as transmission transistors. Among them, the source of NMOS transistor N2 is connected to the BL terminal of the left column bit line, the gate of NMOS transistor N2 is connected to the left column word line WLL, and the drain of NMOS transistor N2 is connected to the storage node Q; the source of NMOS transistor N3 is connected to the BLB terminal of the right column bit line, the gate of NMOS transistor N3 is connected to the right column word line WLR, and the drain of NMOS transistor N2 is connected to the storage node QB; the source of NMOS transistor N4 is connected to the RBL terminal of the left row bit line, the gate of NMOS transistor N4 is connected to the left row word line WLL_VICE, and the drain of NMOS transistor N4 is connected to the storage node Q; the source of NMOS transistor N5 is connected to the RBLB terminal of the right row bit line, the gate of NMOS transistor N5 is connected to the right row word line WLR_VICE, and the drain of NMOS transistor N5 is connected to the storage node QB.

[0059] (3) Each of the transmission gates is controlled by transmission gate control signals TGE and TGEB, and the transmission gate control signals TGE and TGEB are generated by the corresponding control timing generation circuit (the control timing generation circuit is a common control timing generation circuit in SRAM memory in the prior art).

[0060] (4) By adjusting the width-to-length ratio of the word line transmission transistors of each four-word line four-bit line 8-transistor SRAM cell, the weight of each four-word line four-bit line 8-transistor SRAM cell can be controlled, so as to realize subtraction calculation. The width-to-length ratios of the word line transmission transistors of the four-word line four-bit line 8-transistor SRAM cells CELL0 to CELL3 are 1:2:4:8.

[0061] (5) The row word line selection module may adopt a plurality of row word line selection sub - modules. The overall timing control module is respectively connected to each row word line selection sub - module. Each row word line selection sub - module is responsible for providing a left row word line and a right row word line for each row of subtraction calculation unit modules Block4B. The column word line selection module may adopt a plurality of column word line selection sub - modules. The overall timing control module is respectively connected to each column word line selection sub - module. Each column word line selection sub - module is responsible for providing a left column word line and a right column word line for each column of subtraction calculation unit modules Block4B.

[0062] Furthermore, based on making full use of the structure of the four - word - line four - bit - line 8 - transistor SRAM cell, the subtraction calculation circuit structure with bidirectional row and column in - memory of the present invention can form a complementary structure of a row bistable latch 6 - transistor memory cell and can also form a complementary structure of a column bistable latch 6 - transistor memory cell by using the four - word - line four - bit - line 8 - transistor SRAM cell. It converts the single - word - line circuit in the traditional SRAM operation into two pairs of complementary double - word - line circuits, and realizes controlling two pairs of local bit lines to discharge to different degrees. As Figure 4 shown, in the embodiment of the present invention, when the four - word - line four - bit - line 8 - transistor SRAM cell performs row subtraction, the column word line is turned off and the row word line is turned on. As Figure 5As shown, when the four-word-line four-bit-line 8-transistor SRAM cell in the embodiment of the present invention performs column subtraction, the row word line is turned on and the column word line is turned off. By adjusting the multiple increase of the width-to-length ratio of the control word line transmission transistor, a proportionally increased bit line voltage change is obtained under the condition that the turn-on voltage remains unchanged during the unit turn-on time. The width-to-length ratios of the word line transmission transistors of the four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are 1:2:4:8, so as to store 4-bit binary data in the four 8-transistor SRAM cells CELL0 to CELL3 in sequence according to the different high and low bits. The four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are simultaneously connected to the local bit lines, and the local bit lines will discharge to different voltages according to the differences between the input data and the data in each storage cell. Finally, the calculation result is obtained by comparing the voltage differences of the bit line pairs. When the four-word-line four-bit-line 8-transistor SRAM cell performs row subtraction, through the overall timing control module, the row address decoding module is turned on, the column address decoding module is turned off, and the row word line selection module and the row output module are turned on; when the four-word-line four-bit-line 8-transistor SRAM cell performs column subtraction, through the overall timing control module, the column address decoding module is turned on, the row address decoding module is turned off, and the column word line selection module and the column output module are turned on. Compared with the SRAM operation where only one word line is turned on each time, in the embodiment of the present invention, the word lines of all units are turned on simultaneously in multiple rows during the subtraction calculation, so that the row-column bidirectional subtraction calculation is realized without an additional weight modulation circuit, and the data processing efficiency is greatly improved, and the operation time-consuming is short.

[0063] Taking the column subtraction calculation as an example, the following is an illustration. Figure 2Column subtraction calculation principle of the 4-bit binary subtraction calculation unit module Block4B provided by the embodiment of the present invention: Before the calculation stage, binary data for calculation is stored in the four-word line and four-bit line 8-transistor SRAM cells CELL0 to CELL3. In the precharge stage, the transmission gates TG0 and TG1 are turned on, the precharge signal PRE is at a low level, the PMOS transistors P0 and P1 are turned on, and the global left column bit line GBL, the local left column bit line LBL, the global right column bit line GBLB, and the local right column bit line LBLB are all precharged to VDD, and the upper ends of the capacitors C0 and C1 are precharged to VDD; the transmission gates TG2 and TG3 are not turned on, the precharge signal PRE is at a low level, the PMOS transistors P2 and P3 are turned on, but the global left row bit line GRBL, the local left row bit line LRBL, the global right row bit line GRBLB, and the local right row bit line LRBLB are not precharged. After the precharge stage, a 4-bit binary number to be subtracted is input to the left column word lines WLL0 to WLL3, the complement of the 4-bit binary number is input to the right column word lines WLR0 to WLR3, and the left row word lines WLL_VICE0 to WLL_VICE3 and the right row word lines WLR_VICE0 to WLR_VICE3 are all connected to VSS. In the calculation stage, the four-word line and four-bit line 8-transistor SRAM cells CELL0 to CELL3 correspond to the column word line width-to-length ratios of 1:2:4:8 respectively, and are turned on within the same turn-on voltage per unit time, which corresponds to the binary 8421 code, where T is the unit turn-on time of the word line turn-on. Taking the local left column bit line LBL as an example, if the storage node Q of the four-word line and four-bit line 8-transistor SRAM cell CELL0 is 0 and the input left column word line WLL0 is 1, the local left column bit line LBL discharges a charge of ΔV; if the storage node Q of the four-word line and four-bit line 8-transistor SRAM cell CELL1 is 0 and the input left column word line WLL1 is 1, the local left column bit line LBL discharges a charge of 2ΔV; if the storage node Q of the four-word line and four-bit line 8-transistor SRAM cell CELL2 is 0 and the input left column word line WLL2 is 1, the local left column bit line LBL discharges a charge of 4ΔV; if the storage node Q of the four-word line and four-bit line 8-transistor SRAM cell CELL3 is 0 and the input left column word line WLL3 is 1, the local left column bit line LBL discharges a charge of 8ΔV; if the storage nodes Q of the four-word line and four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all 0 or the input left column word lines WLL of the four-word line and four-bit line 8-transistor SRAM cells CELL0 to CELL3 are all 0, the local left column bit line LBL does not discharge. Finally, the transmission gates TG0 and TG1 are turned on, the voltage of the local left column bit line LBL is transmitted to the global left column bit line GBL, the voltage of the local right column bit line LBLB is transmitted to the global right column bit line GBLB, and the output result is converted by the sense amplifier and analog-to-digital converter in the column output module.The above subtraction calculation circuit uses bit-line discharge to achieve subtraction calculation, which can complete the subtraction calculation within one cycle, improve the operation efficiency and energy efficiency, and reduce the energy consumption during the transmission process.

[0064] In summary, the embodiment of the present invention can achieve row subtraction and column subtraction calculations in the 8T SRAM memory without an additional weight modulation circuit, reduce the consumption during the transmission process, greatly reduce the power consumption, and can simultaneously turn on the word lines of all SRAM cells for parallel calculation during the subtraction calculation, greatly improving the data throughput rate during the calculation and shortening the operation time.

[0065] In order to more clearly show the technical solution provided by the present invention and the technical effects produced, the following uses specific embodiments to describe in detail the subtraction calculation circuit structure based on the 8T SRAM memory in both rows and columns of the present invention.

[0066] Embodiment 1

[0067] As Figure 1 、 Figure 2 、 Figure 6 and Figure 7 shown, the subtraction calculation circuit structure based on the 8T SRAM memory in both rows and columns provided by the embodiment of the present invention is subjected to 4-bit binary column subtraction calculation simulation verification, and the process is as follows:

[0068] Taking the calculation of 4-bit binary data 1010 - 0101 as an example, the simulation verification is based on the 28nm CMOS transistor process, and the power supply voltage is 0.9V. The minuend 1010 is stored in 4 four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 in 1 subtraction calculation unit module Block4B from bottom to top in sequence. The storage nodes Q of these 4 four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 respectively correspond to 1010; the subtrahend 0101 is converted into corresponding column word-line control signals (that is, the subtrahend 0101 is input to the left column word lines WLL0 to WLL3, and the complement of the subtrahend 0101 is input to the right column word lines WLR0 to WLR3), controlling the opening of 8 column word lines. The voltage of each column word line is 0.25V, and the opening time is 2ns. As Figure 6As shown, WLL0 and WLL2 in the WLL control signal are turned on, and WLR1 and WLR3 in the WLR control signal are turned on. The turn-on voltage is 0.25V and the time is 2ns. At the beginning of the calculation phase, the minuend 0101 simultaneously turns on the column word lines WLL0, WLL2, WLR1, and WLR3 through the column word line selection module, and the remaining column word lines are turned off. When these four column word lines (i.e., column word lines WLL0, WLL2, WLR1, and WLR3) are turned on simultaneously, the storage node Q of the four-word line four-bit line 8T SRAM cell CELL0 is 0, the input left column word line WLL0 is 1, and the local left column bit line LBL discharges a charge of ΔV; the storage node QB of the four-word line four-bit line 8T SRAM cell CELL1 is 0, the input right column word line WLR1 is 1, and the local right column bit line LBLB discharges a charge of 2ΔV; the storage node Q of the four-word line four-bit line 8T SRAM cell CELL2 is 0, the input left column word line WLL2 is 1, and the local left column bit line LBL discharges a charge of 4ΔV; the storage node QB of the four-word line four-bit line 8T SRAM cell CELL3 is 0, the input right column word line WLR3 is 1, and the local right column bit line LBLB discharges a charge of 8ΔV. Finally, the discharge amount of the local left column bit line LBL is 5ΔV, the discharge amount of the local right column bit line LBLB is 10ΔV, and the discharge amount of the local right column bit line LBLB is 5ΔV more than that of the local left column bit line BLB, so as to convert the difference between 1010 and 0101 into a 5ΔV voltage difference to represent the final calculation result. As Figure 7 shown, when calculating the absolute value of the column difference of 4-bit binary data, as the data is different, the voltage difference between the two column bit lines changes, from which it can be seen that the final output result has good linearity.

[0069] In summary, the embodiment of the present invention can implement row subtraction and column subtraction calculations in an 8T SRAM memory without an additional weight modulation circuit, reduce the consumption during the transmission process, greatly reduce the power consumption, and can simultaneously turn on the word lines of all SRAM cells for parallel calculation during subtraction, greatly improving the data throughput rate during calculation and shortening the operation time.

[0070] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art.

Claims

1. An 8T SRAM in-memory row-column bidirectional subtraction calculation circuit structure, characterized in that, the subtraction calculation circuit includes: an overall timing control module, a row address decoding module, a column address decoding module, a row word line selection module, a column word line selection module, an SRAM storage array, a row output module, and a column output module; among which: the overall timing control module is respectively connected to the row address decoding module, the column address decoding module, the row word line selection module, the column word line selection module, the SRAM storage array, the row output module, and the column output module; the row address decoding module is connected to the row word line selection module, and the column address decoding module is connected to the column word line selection module; the SRAM storage array is composed of a number of subtraction calculation unit modules Block4B; the subtraction calculation unit module Block4B includes 4 four-word-line four-bit-line 8-transistor SRAM cells, 4 PMOS transistors, 4 capacitors, 4 transmission gates, 1 local left column bit line LBL, 1 local right column bit line LBLB, 1 local left row bit line LRBL, and 1 local right row bit line LRBLB; the 4 four-word-line four-bit-line 8-transistor SRAM cells are respectively denoted as CELL0 to CELL3, the 4 PMOS transistors are respectively denoted as P0 to P3, the 4 capacitors are respectively denoted as C0 to C3, and the 4 transmission gates are respectively denoted as TG0 to TG3; the left column word line WLL0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the left column word line WLL0 output by the column word line selection module, the right column word line WLR0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the right column word line WLR0 output by the column word line selection module, the left row word line WLL_VICE0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the left row word line WLL_VICE0 output by the row word line selection module, and the right row word line WLR_VICE0 of the four-word-line four-bit-line 8-transistor SRAM cell CELL0 is connected to the right row word line WLR_VICE0 output by the row word line selection module; the left column word line WLL1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the left column word line WLL1 output by the column word line selection module, the right column word line WLR1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the right column word line WLR1 output by the column word line selection module, the left row word line WLL_VICE1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the left row word line WLL_VICE1 output by the row word line selection module, and the right row word line WLR_VICE1 of the four-word-line four-bit-line 8-transistor SRAM cell CELL1 is connected to the right row word line WLR_VICE1 output by the row word line selection module; The left column word line WLL2 of the four-word-line four-bit-line 8-transistor SRAM cell CELL2 is connected to the left column word line WLL2 output by the column word line selection module. The right column word line WLR2 of the four-word-line four-bit-line 8-transistor SRAM cell CELL2 is connected to the right column word line WLR2 output by the column word line selection module. The left row word line WLL_VICE2 of the four-word-line four-bit-line 8-transistor SRAM cell CELL2 is connected to the left row word line WLL_VICE2 output by the row word line selection module. The right row word line WLR_VICE2 of the four-word-line four-bit-line 8-transistor SRAM cell CELL2 is connected to the right row word line WLR_VICE2 output by the row word line selection module; The left column word line WLL3 of the four-word-line four-bit-line 8-transistor SRAM cell CELL3 is connected to the left column word line WLL3 output by the column word line selection module. The right column word line WLR3 of the four-word-line four-bit-line 8-transistor SRAM cell CELL3 is connected to the right column word line WLR3 output by the column word line selection module. The left row word line WLL_VICE3 of the four-word-line four-bit-line 8-transistor SRAM cell CELL3 is connected to the left row word line WLL_VICE3 output by the row word line selection module. The right row word line WLR_VICE3 of the four-word-line four-bit-line 8-transistor SRAM cell CELL3 is connected to the right row word line WLR_VICE3 output by the row word line selection module; The left column bit line BL terminals of the four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local left column bit line LBL. The right column bit line BLB terminals of the four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local right column bit line LBLB. The left row bit line RBL terminals of the four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local left row bit line LRBL. The right row bit line RBLB terminals of the four-word-line four-bit-line 8-transistor SRAM cells CELL0 to CELL3 are all connected to the local right row bit line LRBLB; The source of the PMOS transistor P0 is connected to the power supply VDD. The drain of the PMOS transistor P0 is connected to the global left column bit line GBL. The gate of the PMOS transistor P0 is connected to the precharge signal PRE. The source of the PMOS transistor P1 is connected to the power supply VDD. The drain of the PMOS transistor P1 is connected to the global right column bit line GBLB. The gate of the PMOS transistor P1 is connected to the precharge signal PRE. The source of the PMOS transistor P2 is connected to the power supply VDD. The drain of the PMOS transistor P2 is connected to the global left row bit line GRBL. The gate of the PMOS transistor P2 is connected to the precharge signal PRE. The source of the PMOS transistor P3 is connected to the power supply VDD. The drain of the PMOS transistor P3 is connected to the global right row bit line GRBLB. The gate of the PMOS transistor P3 is connected to the precharge signal PRE; One end of capacitor C0 is connected to the local left column bit line LBL, and the other end of capacitor C0 is connected to GND; one end of capacitor C1 is connected to the local right column bit line LBLB, and the other end of capacitor C1 is connected to GND; one end of capacitor C2 is connected to the local left row bit line LRBL, and the other end of capacitor C2 is connected to GND; one end of capacitor C3 is connected to the local right row bit line LRBLB, and the other end of capacitor C3 is connected to GND; The transmission gate TG0 connects the global left column bit line GBL and the local left column bit line LBL; the transmission gate TG1 connects the global right column bit line GBLB and the local right column bit line LBLB; the transmission gate TG2 connects the global left row bit line GRBL and the local left row bit line LRBL; the transmission gate TG3 connects the global right row bit line GRBLB and the local right row bit line LRBLB; both the global left column bit line GBL and the global right column bit line GBLB are connected to the column output module; both the global left row bit line GRBL and the global right row bit line GRBLB are connected to the row output module.

2. The in-memory row-column bidirectional subtraction calculation circuit structure based on 8T SRAM according to claim 1, characterized in that, The structure of the four-word line and four-bit line 8-transistor SRAM cell includes: 6 NMOS transistors and 2 PMOS transistors. The 6 NMOS transistors are respectively denoted as N0 to N5, and the 2 PMOS transistors are respectively denoted as P4 to P5; PMOS transistor P4 and NMOS transistor N0 form the first inverter, and PMOS transistor P5 and NMOS transistor N1 form the second inverter, and these two inverters are cross-coupled; NMOS transistors N2, N3, N4, and N5 serve as word line transfer transistors; wherein, the source of NMOS transistor N2 is connected to the BL end of the left column bit line, the gate of NMOS transistor N2 is connected to the left row word line WLL, and the drain of NMOS transistor N2 is connected to the storage node Q; the source of NMOS transistor N3 is connected to the BLB end of the right column bit line, the gate of NMOS transistor N3 is connected to the right row word line WLR, and the drain of NMOS transistor N2 is connected to the storage node QB; the source of NMOS transistor N4 is connected to the RBL end of the left row bit line, the gate of NMOS transistor N4 is connected to the left column word line WLL_VICE, and the drain of NMOS transistor N4 is connected to the storage node Q; the source of NMOS transistor N5 is connected to the RBLB end of the right row bit line, the gate of NMOS transistor N5 is connected to the right column word line WLR_VICE, and the drain of NMOS transistor N5 is connected to the storage node QB.

3. The in-memory row-column bidirectional subtraction calculation circuit structure based on 8T SRAM according to claim 1 or 2, characterized in that, Each of the transmission gates is controlled by transmission gate control signals TGE and TGEB, and the control signals TGE and TGEB are generated by the corresponding control timing generation circuit.

4. The in-memory row-column bidirectional subtraction calculation circuit structure based on 8T SRAM according to claim 1 or 2, characterized in that, by adjusting the width-to-length ratio of the word-line transfer transistors of each four-word-line four-bit-line 8T SRAM cell, the weight of each four-word-line four-bit-line 8T SRAM cell can be controlled, thereby realizing subtraction calculation.

5. The in-memory row-column bidirectional subtraction calculation circuit structure based on 8T SRAM according to claim 1 or 2, characterized in that, the width-to-length ratios of the word-line transfer transistors of the four four-word-line four-bit-line 8T SRAM cells CELL0, CELL1, CELL2, and CELL3 are 1:2:4:

8.

6. The in-memory row-column bidirectional subtraction calculation circuit structure based on 8T SRAM according to claim 1 or 2, characterized in that, the row word-line selection module adopts multiple row word-line selection sub-modules, the overall timing control module is respectively connected to each row word-line selection sub-module, and each row word-line selection sub-module is responsible for providing a left row word-line and a right row word-line for each row subtraction calculation unit module Block4B; the column word-line selection module adopts multiple column word-line selection sub-modules, the overall timing control module is respectively connected to each column word-line selection sub-module, and each column word-line selection sub-module is responsible for providing a left column word-line and a right column word-line for each column subtraction calculation unit module Block4B.

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