Comparator circuit and electronic device with dynamic offset calibration circuit

Abstract

The present invention provides a comparator circuit and an electronic device with a dynamic offset calibration circuit. The offset voltages outputted from an inverting output terminal and a non-inverting output terminal are calibrated respectively by a first dynamic offset calibration circuit and a second dynamic offset calibration circuit, thereby eliminating the influence of the offset voltage in the comparator circuit and ensuring high accuracy and precision of the comparison of the comparator circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of comparators, and more particularly to a comparator circuit and electronic equipment with a dynamic offset calibration circuit. Background Art

[0002] Analog to Digital Converter (ADC) is a bridge connecting analog signals and digital signals, playing an important role in electronic countermeasures, optical communications, high-frequency measuring instruments, biomedicine, voice and image processing, and other fields. As the core part of the analog-to-digital converter, the accuracy and precision of the comparison of the comparator circuit often determine the accuracy and integrity of the output signal of the analog-to-digital converter, and even higher requirements are required in ultra-high-speed analog-to-digital converters. However, in the actual manufacturing process, due to the uncertainty of each process, devices with the same nominal value have mismatches, which seriously affects the accuracy and precision of the comparison of the comparator circuit. Therefore, it is particularly important to eliminate the influence of offset voltage in the comparator circuit. Summary of the invention

[0003] In view of this, the present invention provides a comparator circuit and an electronic device with a dynamic offset calibration circuit, which effectively solves the technical problems existing in the prior art. Through the first dynamic offset calibration circuit and the second dynamic offset calibration circuit, the offset voltages outputted from the inverting output terminal and the non-inverting output terminal are calibrated respectively, thereby ensuring the high accuracy and precision of the comparison of the comparator circuit.

[0004] To achieve the above purpose, the technical solution provided by the present invention is as follows:

[0005] A comparator circuit with a dynamic offset calibration circuit comprises: a preamplifier, a first dynamic offset calibration circuit, a second dynamic offset calibration circuit and a comparator;

[0006] The non-phase output terminal of the pre-amplifier is electrically connected to the first input terminal of the comparator, and the inverting output terminal of the pre-amplifier is electrically connected to the second input terminal of the comparator;

[0007] Furthermore, the output end of the first dynamic offset calibration circuit is electrically connected to the inverting output end of the pre-amplifier, and the output end of the second dynamic offset calibration circuit is electrically connected to the non-inverting output end of the pre-amplifier; wherein the first dynamic offset calibration circuit is used to determine a target first calibration current from a plurality of different first calibration currents and output it to the inverting output end, so as to calibrate the offset inverting output voltage of the inverting output end to the target inverting output voltage, and the second dynamic offset calibration circuit is used to determine a target second calibration current from a plurality of different second calibration currents and output it to the non-inverting output end, so as to calibrate the offset non-inverting output voltage of the non-inverting output end to the target non-inverting output voltage.

[0008] Optionally, the pre-amplifier includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a first current source, and a second current source;

[0009] The gate of the first transistor is connected to a positive input voltage, the first end of the first transistor is electrically connected to the first end of the first current source, the second end of the first transistor is electrically connected to the inverting output end, and the second end of the first current source is grounded;

[0010] The gate of the second transistor is connected to a positive phase reference voltage, the first end of the second transistor is electrically connected to the first end of the first current source, and the second end of the second transistor is electrically connected to the positive phase output end;

[0011] The gate of the third transistor is connected to the inverting reference voltage, the first end of the third transistor is electrically connected to the first end of the second current source, the second end of the third transistor is electrically connected to the inverting output end, and the second end of the second current source is grounded;

[0012] The gate of the fourth transistor is connected to the inverting input voltage, the first end of the fourth transistor is electrically connected to the first end of the second current source, and the second end of the fourth transistor is electrically connected to the non-inverting output end;

[0013] The first end of the first resistor is electrically connected to the power supply voltage end, the second end of the first resistor is electrically connected to the inverting output end, the first end of the second resistor is electrically connected to the power supply voltage end, and the second end of the second resistor is electrically connected to the non-inverting output end.

[0014] Optionally, the pre-amplifier further includes: a fifth transistor and a sixth transistor;

[0015] A first terminal of the fifth transistor is electrically connected to the inverting output terminal, a second terminal of the fifth transistor is electrically connected to the second terminals of the first transistor and the third transistor, and a gate of the fifth transistor is electrically connected to the power supply voltage terminal;

[0016] The first end of the sixth transistor is electrically connected to the positive phase output end, the second end of the sixth transistor is electrically connected to the second ends of the second transistor and the fourth transistor, and the gate of the sixth transistor is electrically connected to the power supply voltage end.

[0017] Optionally, the prevention amplifier further comprises: a seventh transistor;

[0018] The first end of the seventh transistor is electrically connected to the inverting output end, the second end of the seventh transistor is electrically connected to the non-inverting output end, and the gate of the seventh transistor is connected to a normally-on control signal.

[0019] Optionally, the first resistor and the second resistor have the same resistance value.

[0020] Optionally, the first current source and the second current source output the same current.

[0021] Optionally, the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors.

[0022] Optionally, any one of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit comprises: a first mirror transistor, a second mirror transistor and a digital-to-analog converter;

[0023] The input side of the digital-to-analog converter is respectively connected to a plurality of control codes, and the output end of the digital-to-analog converter is electrically connected to the second end of the first mirror transistor;

[0024] The second end of the first mirror transistor is electrically connected to the gate of the first mirror transistor and the gate of the second mirror transistor, the first end of the first mirror transistor and the first end of the second mirror transistor are both electrically connected to the power supply voltage terminal, and the second end of the second mirror transistor is the output end of the dynamic offset calibration circuit.

[0025] Optionally, any one of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit comprises: a first mirror transistor, a second mirror transistor, a third mirror transistor, a fourth mirror transistor and a digital-to-analog converter;

[0026] The input side of the digital-to-analog converter is respectively connected to a plurality of control codes, the output end of the digital-to-analog converter is electrically connected to the second end of the third mirror transistor, the second end of the third mirror transistor is electrically connected to the gate of the third mirror transistor and the gate of the fourth mirror transistor, the first end of the third mirror transistor is electrically connected to the second end of the first mirror transistor, the first end of the fourth mirror transistor is electrically connected to the second end of the second mirror transistor, and the second end of the fourth mirror transistor is the output end of the dynamic offset calibration circuit;

[0027] The second end of the first mirror transistor is electrically connected to the gate of the first mirror transistor and the gate of the second mirror transistor, and the first end of the first mirror transistor and the first end of the second mirror transistor are both electrically connected to a power supply voltage terminal.

[0028] Correspondingly, the present invention further provides an electronic device, wherein the electronic device comprises the above-mentioned comparator circuit with the dynamic offset calibration circuit.

[0029] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0030] The present invention provides a comparator circuit and an electronic device with a dynamic offset calibration circuit, comprising: a preamplifier, a first dynamic offset calibration circuit, a second dynamic offset calibration circuit and a comparator; the positive phase output terminal of the preamplifier is electrically connected to the first input terminal of the comparator, and the negative phase output terminal of the preamplifier is electrically connected to the second input terminal of the comparator; and the output terminal of the first dynamic offset calibration circuit is electrically connected to the negative phase output terminal of the preamplifier, and the output terminal of the second dynamic offset calibration circuit is electrically connected to the positive phase output terminal of the preamplifier; wherein the first dynamic offset calibration circuit is used to determine a target first calibration current from a plurality of different first calibration currents and output it to the negative phase output terminal, so as to calibrate the offset negative phase output voltage of the negative phase output terminal to the target negative phase output voltage, and the second dynamic offset calibration circuit is used to determine a target second calibration current from a plurality of different second calibration currents and output it to the positive phase output terminal, so as to calibrate the offset positive phase output voltage of the positive phase output terminal to the target positive phase output voltage. It can be seen from the above content that the technical solution provided by the present invention calibrates the offset voltages outputted from the inverting output terminal and the non-inverting output terminal respectively through the first dynamic offset calibration circuit and the second dynamic offset calibration circuit, thereby eliminating the influence of the offset voltage in the comparator circuit, thereby ensuring the high accuracy and precision of the comparison of the comparator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0032] Figure 1 A schematic structural diagram of a comparator circuit with a dynamic offset calibration circuit provided by an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the structure of a pre-amplifier provided by an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of the structure of another pre-amplifier provided in an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the structure of a dynamic offset calibration circuit provided by an embodiment of the present invention;

[0036] Figure 5A schematic diagram of the structure of another dynamic offset calibration circuit provided by an embodiment of the present invention;

[0037] Figure 6 A schematic structural diagram of another comparator circuit with a dynamic offset calibration circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] As described in the background technology, the comparator circuit is the core part of the analog-to-digital converter. The accuracy and precision of its comparison often determine the accuracy and integrity of the analog-to-digital converter output signal, and the requirements are even higher in ultra-high-speed analog-to-digital converters. However, in the actual manufacturing process, due to the uncertainty of each process, the nominally same devices have mismatches, which seriously affects the accuracy and precision of the comparison of the comparator circuit. Therefore, it is particularly important to eliminate the influence of the offset voltage in the comparator circuit.

[0040] Based on this, the embodiments of the present invention provide a comparator circuit and an electronic device with a dynamic offset calibration circuit, which effectively solves the technical problems existing in the prior art. Through the first dynamic offset calibration circuit and the second dynamic offset calibration circuit, the offset voltages outputted from the inverting output terminal and the non-inverting output terminal are calibrated respectively, thereby ensuring the high accuracy and precision of the comparison of the comparator circuit.

[0041] To achieve the above purpose, the technical solution provided by the embodiment of the present invention is as follows, specifically combined with Figures 1 to 6 The technical solution provided by the embodiment of the present invention is described in detail.

[0042] refer to Figure 1 , which is a schematic diagram of the structure of a comparator circuit with a dynamic offset calibration circuit provided by an embodiment of the present invention, wherein the comparator circuit with a dynamic offset calibration circuit includes: a pre-amplifier 100, a first dynamic offset calibration circuit 210, a second dynamic offset calibration circuit 220 and a comparator 300.

[0043] The non-phase output terminal OUTP of the pre-amplifier 100 is electrically connected to the first input terminal of the comparator 300 , and the inverting output terminal OUTN of the pre-amplifier 100 is electrically connected to the second input terminal of the comparator 300 .

[0044] Furthermore, the output end of the first dynamic offset calibration circuit 210 is electrically connected to the inverting output end OUTN of the pre-amplifier 100, and the output end of the second dynamic offset calibration circuit 220 is electrically connected to the non-inverting output end OUTP of the pre-amplifier 100; wherein the first dynamic offset calibration circuit 210 is used to determine a target first calibration current from a plurality of different first calibration currents and output it to the inverting output end OUTN, so as to calibrate the offset inverting output voltage of the inverting output end OUTN to the target inverting output voltage, and the second dynamic offset calibration circuit 220 is used to determine a target second calibration current from a plurality of different second calibration currents and output it to the non-inverting output end OUTP, so as to calibrate the offset non-inverting output voltage of the non-inverting output end OUTP to the target non-inverting output voltage.

[0045] The preamplifier 100 provided in the embodiment of the present invention is connected to a positive phase input voltage VINP, a negative phase input voltage VINN, a positive phase reference voltage REFP and a negative phase reference voltage REFN, and outputs a positive phase output voltage from a positive phase output terminal OUTP to a comparator 300, and outputs a negative phase output voltage from a negative phase output terminal OUTN to the comparator 300. The positive phase input voltage VINP and the negative phase input voltage VINN are differential input signals of the comparator circuit, and the positive phase reference voltage REFP and the negative phase reference voltage REFN are respectively a positive phase comparison voltage and a negative phase comparison voltage of the comparator circuit.

[0046] The preamplifier of the embodiment of the present invention is electrically connected before the comparator. Firstly, it can amplify the differential input signal input to the comparator circuit, reduce the offset voltage, and improve the comparison speed of the comparator circuit; secondly, it can isolate the input signal and output signal of the comparator to avoid the influence of the kickback noise on the output signal. In addition, the technical solution provided by the embodiment of the present invention calibrates the offset voltage outputted from the inverting output terminal and the non-inverting output terminal respectively through the first dynamic offset calibration circuit and the second dynamic offset calibration circuit, eliminates the influence of the offset voltage in the comparator circuit, and thus ensures the high accuracy and precision of the comparison of the comparator circuit.

[0047] like Figure 2 As shown, it is a structural schematic diagram of a pre-amplifier provided in an embodiment of the present invention, wherein the pre-amplifier includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first resistor R1, a second resistor R2, a first current source I1 and a second current source I2.

[0048] The gate of the first transistor M1 is connected to the positive input voltage VINP, the first end of the first transistor M1 is electrically connected to the first end of the first current source I1, the second end of the first transistor M1 is electrically connected to the inverting output end OUTN, and the second end of the first current source I1 is grounded.

[0049] A gate of the second transistor M2 is connected to a positive phase reference voltage REFP, a first end of the second transistor M2 is electrically connected to a first end of the first current source I1, and a second end of the second transistor M2 is electrically connected to the positive phase output end OUTP.

[0050] The gate of the third transistor M3 is connected to the inverting reference voltage REFN, the first end of the third transistor M3 is electrically connected to the first end of the second current source I2, the second end of the third transistor M3 is electrically connected to the inverting output end OUTN, and the second end of the second current source I2 is grounded.

[0051] A gate of the fourth transistor M4 is connected to the inverting input voltage VINN, a first end of the fourth transistor M4 is electrically connected to a first end of the second current source I2, and a second end of the fourth transistor M4 is electrically connected to the positive output end OUTP.

[0052] The first end of the first resistor R1 is electrically connected to the power supply voltage terminal VDD, the second end of the first resistor R1 is electrically connected to the inverting output terminal OUTN, the first end of the second resistor R2 is electrically connected to the power supply voltage terminal VDD, and the second end of the second resistor R2 is electrically connected to the positive output terminal OUTP.

[0053] Furthermore, when the voltage outputted by the power supply voltage terminal provided by the embodiment of the present invention is relatively large, the preamplifier provided by the embodiment of the present invention may also be provided with related devices for voltage division. Figure 3 FIG. 1 is a schematic diagram of the structure of another preamplifier provided by an embodiment of the present invention, wherein Figure 2 On the basis of the pre-amplifier structure shown, the pre-amplifier further includes: a fifth transistor M5 and a sixth transistor M6.

[0054] A first end of the fifth transistor M5 is electrically connected to the inverting output terminal OUTN, a second end of the fifth transistor M5 is electrically connected to the second ends of the first transistor M1 and the third transistor M3, and a gate of the fifth transistor M5 is electrically connected to the power supply voltage terminal VDD.

[0055] A first end of the sixth transistor M6 is electrically connected to the positive phase output terminal OUTP, a second end of the sixth transistor M6 is electrically connected to the second ends of the second transistor M2 and the fourth transistor M4, and a gate of the sixth transistor M6 is electrically connected to the power supply voltage terminal VDD.

[0056] It can be understood that when the voltage outputted from the power supply voltage terminal is relatively large, the fifth transistor and the sixth transistor are used for voltage division to prevent the relatively large voltage from damaging the first transistor, the second transistor, the third transistor and the fourth transistor in the pre-amplifier. The gates of the fifth transistor and the sixth transistor are both connected to the power supply voltage terminal, and the power supply voltage terminal keeps the fifth transistor and the sixth transistor in a normally open state, so that the pre-amplifier can work normally.

[0057] In one embodiment of the present invention, the first resistor and the second resistor provided by the present invention may have the same resistance value. The first current source and the second current source provided by the present invention are constant current sources and output the same current. And, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor provided by the present invention may all be N-type transistors.

[0058] like Figure 2 and 3 As shown, the prevention amplifier provided in the embodiment of the present invention further includes: a seventh transistor M7. The first end of the seventh transistor M7 is electrically connected to the inverting output terminal OUTN, the second end of the seventh transistor M7 is electrically connected to the non-inverting output terminal OUTP, and the gate of the seventh transistor M7 is connected to the normally open control signal VS.

[0059] It can be understood that the present invention connects a normally-on seventh transistor between the positive-phase output terminal and the negative-phase output terminal of the preamplifier, and the seventh transistor is used to balance the swing of the positive-phase output terminal and the negative-phase output terminal, ensuring that the swing of the output terminal is small, and further improving the precision and accuracy of the comparator circuit. Among them, the seventh transistor can be a P-type transistor, and the normally-on control signal is a low-level signal; or the seventh transistor can be an N-type transistor, and the normally-on control signal is a high-level signal.

[0060] like Figure 4 , which is a schematic diagram of the structure of a dynamic offset calibration circuit provided by an embodiment of the present invention, wherein any one of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit provided by an embodiment of the present invention comprises: a first mirror transistor PM1, a second mirror transistor PM2 and a digital-to-analog converter DAC.

[0061] The input side of the digital-to-analog converter DAC is respectively connected to multiple control codes (for example, if the current provided to the mirror transistor is provided by a 5-bit DAC control circuit, the multiple control codes are B0-B4), and the output end of the digital-to-analog converter DAC is electrically connected to the second end of the first mirror transistor PM1.

[0062] The second end of the first mirror transistor PM1 is electrically connected to the gate of the first mirror transistor PM1 and the gate of the second mirror transistor PM2, the first end of the first mirror transistor PM1 and the first end of the second mirror transistor PM2 are both electrically connected to the power supply voltage terminal VDD, and the second end of the second mirror transistor PM2 is the output end of the dynamic offset calibration circuit.

[0063] Or Figure 5 , which is a schematic diagram of the structure of another dynamic offset calibration circuit provided by an embodiment of the present invention, wherein any one of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit provided by an embodiment of the present invention comprises: a first mirror transistor PM1, a second mirror transistor PM2, a third mirror transistor PM3, a fourth mirror transistor PM4 and a digital-to-analog converter DAC.

[0064] The input side of the digital-to-analog converter DAC is respectively connected to a plurality of control codes (for example, if the current provided to the mirror transistor is provided by a 5-bit DAC control circuit, the plurality of control codes are B0-B4), the output end of the digital-to-analog converter DAC is electrically connected to the second end of the third mirror transistor PM3, the second end of the third mirror transistor PM3 is electrically connected to the gate of the third mirror transistor PM3 and the gate of the fourth mirror transistor PM4, the first end of the third mirror transistor PM3 is electrically connected to the second end of the first mirror transistor PM1, the first end of the fourth mirror transistor PM4 is electrically connected to the second end of the second mirror transistor PM2, and the second end of the fourth mirror transistor PM4 is the output end of the dynamic offset calibration circuit.

[0065] The second end of the first mirror transistor PM1 is electrically connected to the gate of the first mirror transistor PM1 and the gate of the second mirror transistor PM2, and the first end of the first mirror transistor PM1 and the first end of the second mirror transistor PM2 are both electrically connected to the power supply voltage terminal VDD.

[0066] It can be understood that the first dynamic offset calibration circuit and the second dynamic offset calibration circuit provided in the embodiment of the present invention include a common source and common gate mirror current circuit and a DAC. The DAC is used to select a target calibration current output from a plurality of calibration currents according to the control of a plurality of control codes, and output it after mirroring through the common source and common gate mirror current circuit. The control code can control the output current when the DAC steps, such as including the first control code to the fifth control code, the first control code acts on the DAC to output a unit calibration current, the first control code and the second control code act on the DAC at the same time to output the sum of the unit calibration current and the step calibration current, the first control code to the third control code act on the DAC at the same time to output the unit calibration current and the sum of the two step calibration currents, and so on; wherein the higher the number of bits of the control code, the finer the control step, thereby being able to expand the dynamic calibration range. Optionally, the first mirror transistor, the second mirror transistor, the third mirror transistor and the fourth mirror transistor provided in the embodiment of the present invention can all be P-type transistors.

[0067] Combination Figure 6 The working principle of the comparator circuit provided by the embodiment of the present invention is described in detail. Figure 6 A schematic diagram of the structure of another comparator circuit with a dynamic offset calibration circuit provided by an embodiment of the present invention, wherein the present invention does not limit the size ratio of the first mirror transistor PM1, the second mirror transistor PM2, the third mirror transistor PM3 and the fourth mirror transistor PM4 corresponding to the first dynamic offset calibration circuit and the second dynamic offset calibration circuit, and the control code accessed by the digital converter corresponding to the first dynamic offset calibration circuit and the second dynamic offset calibration circuit is independently controlled according to actual application (that is, the DAC of the first dynamic offset calibration circuit accesses the control code BN0 to BN4, and the DAC of the second dynamic offset calibration circuit accesses the control code BP0 to BP4), and the number of bits of the control code accessed by the first dynamic offset calibration circuit and the second dynamic offset calibration circuit can be the same or different, and the calibration range of the dynamic offset calibration circuit is determined by the control code of the digital-to-analog converter DAC and the size of the mirror transistors.

[0068] Under normal circumstances, when the differential input signal of VINP and VINN is 0 and their common modes are respectively equal to the voltages of REFP and REFN, the output differential modes of OUTP and OUTN are 0. Due to the existence of offset, under the above input conditions, the output differential modes of OUTP and OUTN are not 0. Therefore, the output conditions of OUTP and OUTN can be adjusted by respectively outputting the first calibration current and the second calibration current of the first dynamic offset calibration circuit and / or the second dynamic offset calibration circuit, so that the output differential modes of OUTP and OUTN are 0, thereby eliminating the influence of the offset.

[0069] In the initial state, the control codes of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit are all 0 (a control code of 0 means no control output to the DAC), indicating that the DACs are all turned off. For the cascode mirror current circuit (i.e., the circuit composed of the first mirror transistor PM1, the second mirror transistor PM2, the third mirror transistor PM3, and the fourth mirror transistor PM4), the current is 0 (i.e., the output currents of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit are both 0). Taking the first dynamic offset calibration circuit on the OUTN side as an example: when the outputs of OUTN and OUTP are not equal, i.e., OUTN common mode ≠ OUTP common mode, assume the output voltage of OUTN < the output voltage of OUTP. Adjust the magnitude of the control code of the first dynamic offset calibration circuit, set the corresponding bit to 1, indicating that it acts on the DAC to turn it on. Then the magnitude of the current output by the DAC will change with the adjustment of the number of bits set to 1 in the control code. According to the optimized setting of the size ratio of the mirror transistors, the current output by the DAC can be accurately replicated and output to OUTN and defined as I3. At this time, I3 is not 0 and is greater than 0. Since the current sources I1 and I2 are constant at the lower part of the circuit, the current I1' provided by the current source I1 to OUTN is constant. I1' = I4 + I3 (I4 is the current provided by the first resistor R1 to OUTN). Due to the change in I3, the magnitude of I4 is affected. According to the circuit relationship, the output voltage of OUTN = the voltage of VDD - I4 * R1, and I4 = I1' - I3. In the initial state, I3 is 0 and I4 = I1'. When the control code of the first dynamic offset calibration circuit changes, I3 increases and is not 0, and I4 decreases. Therefore, the output of OUTN increases. Adjusting the control code of the first dynamic offset calibration circuit to an appropriate value can make the output of OUTN = the output of OUTP, thus completing the offset calibration.

[0070] Correspondingly, an embodiment of the present invention further provides an electronic device, and the electronic device includes the comparator circuit with a dynamic offset calibration circuit provided in any of the above embodiments.

[0071] The embodiment of the present invention provides a comparator circuit and an electronic device with a dynamic offset calibration circuit, comprising: a preamplifier, a first dynamic offset calibration circuit, a second dynamic offset calibration circuit and a comparator; the non-phase output terminal of the preamplifier is electrically connected to the first input terminal of the comparator, and the inverting output terminal of the preamplifier is electrically connected to the second input terminal of the comparator; and the output terminal of the first dynamic offset calibration circuit is electrically connected to the inverting output terminal of the preamplifier, and the output terminal of the second dynamic offset calibration circuit is electrically connected to the non-phase output terminal of the preamplifier; wherein the first dynamic offset calibration circuit is used to determine a target first calibration current from a plurality of different first calibration currents and output it to the inverting output terminal, so as to calibrate the offset inverting output voltage of the inverting output terminal to the target inverting output voltage, and the second dynamic offset calibration circuit is used to determine a target second calibration current from a plurality of different second calibration currents and output it to the non-phase output terminal, so as to calibrate the offset positive output voltage of the positive output terminal to the target positive output voltage. It can be seen from the above content that the technical solution provided by the embodiment of the present invention calibrates the offset voltages outputted from the inverting output terminal and the non-inverting output terminal respectively through the first dynamic offset calibration circuit and the second dynamic offset calibration circuit, thereby eliminating the influence of the offset voltage in the comparator circuit, thereby ensuring the high accuracy and precision of the comparison of the comparator circuit.

[0072] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A comparator circuit with a dynamic offset calibration circuit, characterized in that: include: A preamplifier, a first dynamic offset calibration circuit, a second dynamic offset calibration circuit and a comparator; The non-phase output terminal of the pre-amplifier is electrically connected to the first input terminal of the comparator, and the inverting output terminal of the pre-amplifier is electrically connected to the second input terminal of the comparator; And, the output end of the first dynamic offset calibration circuit is electrically connected to the inverting output end of the pre-amplifier, and the output end of the second dynamic offset calibration circuit is electrically connected to the non-inverting output end of the pre-amplifier; wherein the first dynamic offset calibration circuit is used to determine a target first calibration current from a plurality of different first calibration currents and output it to the inverting output end, so as to calibrate the offset inverting output voltage of the inverting output end to the target inverting output voltage, and the second dynamic offset calibration circuit is used to determine a target second calibration current from a plurality of different second calibration currents and output it to the non-inverting output end, so as to calibrate the offset non-inverting output voltage of the non-inverting output end to the target non-inverting output voltage; The pre-amplifier includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a first current source, and a second current source; The gate of the first transistor is connected to a positive input voltage, the first end of the first transistor is electrically connected to the first end of the first current source, the second end of the first transistor is electrically connected to the inverting output end, and the second end of the first current source is grounded; The gate of the second transistor is connected to a positive phase reference voltage, the first end of the second transistor is electrically connected to the first end of the first current source, and the second end of the second transistor is electrically connected to the positive phase output end; The gate of the third transistor is connected to the inverting reference voltage, the first end of the third transistor is electrically connected to the first end of the second current source, the second end of the third transistor is electrically connected to the inverting output end, and the second end of the second current source is grounded; The gate of the fourth transistor is connected to the inverting input voltage, the first end of the fourth transistor is electrically connected to the first end of the second current source, and the second end of the fourth transistor is electrically connected to the non-inverting output end; The first end of the first resistor is electrically connected to the power supply voltage terminal, the second end of the first resistor is electrically connected to the inverting output terminal, the first end of the second resistor is electrically connected to the power supply voltage terminal, and the second end of the second resistor is electrically connected to the non-inverting output terminal; The pre-amplifier further includes: a fifth transistor and a sixth transistor; A first terminal of the fifth transistor is electrically connected to the inverting output terminal, a second terminal of the fifth transistor is electrically connected to the second terminals of the first transistor and the third transistor, and a gate of the fifth transistor is electrically connected to the power supply voltage terminal; The first end of the sixth transistor is electrically connected to the positive phase output end, the second end of the sixth transistor is electrically connected to the second end of the second transistor and the second end of the fourth transistor, and the gate of the sixth transistor is electrically connected to the power supply voltage end; The pre-amplifier further includes: a seventh transistor; The first end of the seventh transistor is electrically connected to the inverting output end, the second end of the seventh transistor is electrically connected to the non-inverting output end, and the gate of the seventh transistor is connected to a normally-on control signal.

2. The comparator circuit with a dynamic offset calibration circuit according to claim 1, characterized in that: The first resistor and the second resistor have the same resistance value.

3. The comparator circuit with a dynamic offset calibration circuit according to claim 1, characterized in that: The first current source and the second current source output the same current.

4. The comparator circuit with a dynamic offset calibration circuit according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors.

5. The comparator circuit with a dynamic offset calibration circuit according to claim 1, characterized in that: Any one of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit comprises: a first mirror transistor, a second mirror transistor and a digital-to-analog converter; The input side of the digital-to-analog converter is respectively connected to a plurality of control codes, and the output end of the digital-to-analog converter is electrically connected to the second end of the first mirror transistor; The second end of the first mirror transistor is electrically connected to the gate of the first mirror transistor and the gate of the second mirror transistor, the first end of the first mirror transistor and the first end of the second mirror transistor are both electrically connected to the power supply voltage terminal, and the second end of the second mirror transistor is the output end of the dynamic offset calibration circuit.

6. The comparator circuit with a dynamic offset calibration circuit according to claim 1, characterized in that: Any one of the first dynamic offset calibration circuit and the second dynamic offset calibration circuit comprises: a first mirror transistor, a second mirror transistor, a third mirror transistor, a fourth mirror transistor and a digital-to-analog converter; The input side of the digital-to-analog converter is respectively connected to a plurality of control codes, the output end of the digital-to-analog converter is electrically connected to the second end of the third mirror transistor, the second end of the third mirror transistor is electrically connected to the gate of the third mirror transistor and the gate of the fourth mirror transistor, the first end of the third mirror transistor is electrically connected to the second end of the first mirror transistor, the first end of the fourth mirror transistor is electrically connected to the second end of the second mirror transistor, and the second end of the fourth mirror transistor is the output end of the dynamic offset calibration circuit; The second end of the first mirror transistor is electrically connected to the gate of the first mirror transistor and the gate of the second mirror transistor, and the first end of the first mirror transistor and the first end of the second mirror transistor are both electrically connected to a power supply voltage terminal.

7. An electronic device, characterized in that: The electronic device comprises the comparator circuit with a dynamic offset calibration circuit as claimed in any one of claims 1 to 6.

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