Memory cell and memory device having the same

Abstract

A memory device includes: a substrate; bit lines that are horizontally oriented and parallel to the substrate; transistors that include two channels horizontally oriented from the bit lines and a word line vertically oriented and surrounding the two channels; and capacitors that are horizontally oriented from the transistors.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0134018, filed on October 16, 2020, the entire contents of which are incorporated herein by reference. Technical field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a memory cell having a higher degree of integration and a semiconductor device including the memory cell. Background art

[0004] Since the integration of two - dimensional (2D) semiconductor devices mainly depends on the area occupied by memory cells, the integration is greatly affected by the formation of fine patterns. Since expensive equipment is required to form fine patterns, there are still practical limitations in the degree of integration of two - dimensional semiconductor devices although it has increased. To solve this problem, memory devices having memory cells arranged in a three - dimensional manner have been proposed. Summary of the invention

[0005] Embodiments of the present invention relate to a memory cell having a higher degree of integration and a memory device including the memory cell.

[0006] According to an embodiment of the present invention, a memory device includes: a substrate; bit lines horizontally oriented parallel to the substrate; transistors including two channels horizontally oriented from the bit lines and a word line vertically oriented and surrounding the two channels; and capacitors horizontally oriented from the transistors.

[0007] According to another embodiment of the present invention, a memory device includes: a substrate including a peripheral circuit portion; and a memory cell array including a plurality of memory cells vertically stacked with respect to the peripheral circuit portion, wherein each of the memory cells includes: a bit line horizontally oriented parallel to the substrate; a transistor including two nanosheet channels horizontally oriented from the bit line and a word line vertically oriented and surrounding the two nanosheet channels; and a capacitor horizontally oriented from the transistor. Brief description of the drawings

[0008] Figure 1 is a perspective view schematically showing the structure of a memory device according to an embodiment of the present invention.

[0009] Figure 2A is along Figure 1 the cross - sectional view taken along line A - A' shown.

[0010] Figure 2B is along Figure 1A cross-sectional view taken along line B-B' as shown.

[0011] Figures 3A to 6 The schematic structure of a storage device according to other embodiments of the present invention is shown. Detailed implementation manners

[0012] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, in the various drawings and embodiments of the present invention, the same reference numerals refer to the same parts.

[0013] The drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When the first layer is referred to as being "on the second layer" or "on the substrate", it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where there is a third layer between the first layer and the second layer or the substrate.

[0014] Figure 1 is a perspective view showing the schematic structure of a storage device 100 according to an embodiment of the present invention. Figure 2A is along Figure 1 A cross-sectional view taken along line A-A' as shown. Figure 2B is along Figure 1 A cross-sectional view taken along line B-B' as shown.

[0015] Referring to Figures 1 to 2B , the storage device 100 may include a plurality of storage cells MC. The storage cells MC may be located above a substrate structure LS. According to an embodiment of the present invention, the storage device 100 may include a storage cell array MCA in which two storage cells MC are stacked in the vertical direction. Each storage cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include a word line WL vertically oriented in a first direction D1. The bit line BL may be parallel to the substrate structure. The bit line BL may be horizontally oriented in a third direction D3. The transistor TR may be horizontally oriented in a second direction D2. The capacitor CAP may be horizontally oriented from the transistor TR in the second direction D2.

[0016] The substrate structure LS can be any material suitable for semiconductor processing. The substrate structure LS can include at least one of a conductive material, a dielectric material, and a semiconductor material. Various materials can be formed in the substrate structure LS. The substrate structure LS can include a semiconductor substrate, and the semiconductor substrate can be formed of a silicon-containing material. For example, the substrate structure LS can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers thereof. The substrate structure LS can include other semiconductor materials, such as germanium. The substrate structure LS can include a III / V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate structure LS can include a silicon-on-insulator (SOI) substrate.

[0017] According to another embodiment of the present invention, the substrate structure LS can include a semiconductor substrate, a plurality of integrated circuits formed on the semiconductor substrate, and a multi-level metal line MLM or a combination thereof. For example, the substrate structure LS can include a peripheral circuit portion PC, and the peripheral circuit portion PC can include a plurality of control circuits for controlling the memory cell MC. The peripheral circuit portion PC can include a sense amplifier SA coupled to the bit line BL and a sub-word line driver coupled to the word line WL.

[0018] According to an embodiment of the present invention, the memory cell array MCA can be positioned at a higher level than the peripheral circuit portion PC. The bit line BL and the word line WL can be coupled to the peripheral circuit portion PC by using a multi-level metal line MLM (not shown). The memory cell array MCA can include memory cells MC stacked in a vertical direction above the peripheral circuit portion PC. The bit line BL of the memory cell array MCA can extend laterally in a third direction D3 above the peripheral circuit portion PC.

[0019] According to another embodiment of the present invention, the memory cell array MCA can be located at a lower level than the peripheral circuit portion PC. In this case, the memory cell array MCA can include memory cells MC stacked in a vertical direction below the peripheral circuit portion PC. The bit line BL of the memory cell array MCA can extend laterally in a third direction D3 below the peripheral circuit portion PC.

[0020] The bit line BL can include laterally oriented columns. The bit line BL can include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL can include polycrystalline silicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL can include polycrystalline silicon doped with an N-type impurity or titanium nitride (TiN). The bit line BL can include a stack of titanium nitride and tungsten (TiN / W). The bit line BL can include laterally oriented metal columns.

[0021] The transistor TR may include a lateral transistor. The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be laterally oriented in a second direction D2 from a bit line BL. The word line WL may be vertically oriented in a first direction D1. The active layer ACT may include a first doped portion SR, second doped portions DR1 and DR2, and channel portions CH1 and CH2. The channel portions CH1 and CH2 may be located between the first doped portion SR and the second doped portions DR1 and DR2. The first doped portion SR may provide a first edge of the active layer ACT, and the second doped portions DR1 and DR2 may provide a second edge of the active layer ACT. The active layer ACT may include a silicon-containing material. The active layer ACT may include a semiconductor material, a single-crystalline semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the active layer ACT may include single-crystalline silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS 2 or WS 2 . The first doped portion SR and the second doped portions DR1 and DR2 may include an N-type impurity or a P-type impurity. The first doped portion SR and the second doped portions DR1 and DR2 may include phosphorus (P), arsenic (As), boron (B), indium (In), or a combination thereof. The first doped portion SR and the second doped portions DR1 and DR2 may be doped with the same impurity. The first doped portion SR and the second doped portions DR1 and DR2 may be respectively referred to as a first source / drain and a second source / drain. The channel portions CH1 and CH2 may include an impurity different from the impurities of the first doped portion SR and the second doped portions DR1 and DR2. The first doped portion SR, the channel portions CH1 and CH2, and the second doped portions DR1 and DR2 may be in an integrated form, so that the active layer ACT may have shape. The first doped portion SR may have an integrated source / drain structure commonly coupled to the first edges of the two channel portions CH1 and CH2, and the second doped portions DR1 and DR2 may have a split source / drain structure. The second doped portions DR1 and DR2 are respectively coupled to the second edges of the two channel portions CH1 and CH2.

[0022] The channel portions CH1 and CH2 can be laterally oriented in the second direction D2. The channel portions CH1 and CH2 can be laterally oriented in the second direction D2 between the first doped portion SR and the second doped portions DR1 and DR2. The channel portions CH1 and CH2 can have a lateral flat plate shape. The length of the channel portions CH1 and CH2 in the second direction D2 can be greater than the length in the third direction D3. The channel portions CH1 and CH2 can be referred to as nano sheets or nano sheet channels. Since the channel portions CH1 and CH2 are laterally oriented in the second direction D2, the channel portions CH1 and CH2 can be referred to as "lateral nano sheets". The channel portions CH1 and CH2 can include at least two channel portions, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 can be vertically arranged in the first direction D1. A part of the word line WL can fill the space between the first channel portion CH1 and the second channel portion CH2. The thickness of the first channel portion CH1 and the thickness of the second channel portion CH2 can be the same. Here, the thickness can be the thickness in the first direction D1. The channel portions CH1 and CH2 can include a semiconductor material, a single crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the channel portions CH1 and CH2 can include single crystal silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS 2 or WS 2 . The active layer ACT including the channel portions CH1 and CH2 can be formed by atomic layer deposition (ALD).

[0023] The first doped portion SR can be coupled to the bit line BL. The first doped portion SR can be commonly coupled with the first edges of the channel portions CH1 and CH2. The first doped portion SR can be vertically oriented in the first direction D1.

[0024] The second doped portions DR1 and DR2 can be coupled to the capacitor CAP. The second doped portions DR1 and DR2 can be coupled to the storage node SN of the capacitor CAP. The second doped portions DR1 and DR2 can include a lower second doped portion DR1 and an upper second doped portion DR2. The lower second doped portion DR1 and the upper second doped portion DR2 can be spaced apart from each other in the vertical direction. The lower second doped portion DR1 can be coupled to the second edge of the first channel portion CH1, while the upper second doped portion DR2 can be coupled to the second edge of the second channel portion CH2.

[0025] The word line WL can be vertically oriented in the first direction D1 and can have a surrounding shape around the channel portions CH1 and CH2. The word line WL having the surrounding shape can be referred to as a gate-all-around (GAA) word line.

[0026] The word line WL may include a silicon-containing material, a metal-containing material, or a combination thereof. The word line WL may include polysilicon, metal, metal silicide, metal nitride, or a combination thereof. For example, the word line WL may include a stack of titanium nitride and tungsten.

[0027] The gate dielectric layer GD may be formed between the word line WL and the channel portions CH1 and CH2. The gate dielectric layer GD may surround the channel portions CH1 and CH2. The word line WL may surround the channel portions CH1 and CH2, while the gate dielectric layer GD is interposed between the word line WL and the channel portions CH1 and CH2. The gate dielectric layer GD may have an encircling shape that conformally surrounds the channel portions CH1 and CH2. The gate dielectric layer GD may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0028] The capacitor CAP may be arranged laterally from the transistor TR. The capacitor CAP may be oriented laterally in the second direction D2. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged laterally in the second direction D2. In one embodiment, the storage node SN may have a laterally oriented cylindrical shape. In one embodiment, the plate node PN may have a shape of a cylindrical shape surrounding the storage node SN. The dielectric layer DE may have a shape covering the cylindrical surface of the storage node SN. The plate node PN may be coupled to the plate line PL. According to another embodiment of the present invention, the plate node PN and the plate line PL are integrated, and the plate node PN may be a part of the plate line PL.

[0029] The storage node SN may have a three-dimensional structure, and the storage node SN having a three-dimensional structure may have a lateral three-dimensional structure parallel to the second direction D2. As an example of the three-dimensional structure, the storage node SN may have a cylindrical shape, a columnar shape, or a pylinder shape that combines a columnar shape and a cylindrical shape. In one embodiment, the storage node SN may have a cylindrical shape. The dielectric layer DE may be formed between the storage node SN and the plate node PN. The dielectric layer DE may directly contact the plate node PN. The storage node SN may be commonly coupled to the second doping portions DR1 and DR2.

[0030] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO 2) may have a dielectric constant of about 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of about 4 or higher. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). According to another embodiment of the present invention, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0031] The dielectric layer DE may be formed of a zirconium-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO 2 ). The stacked structure including zirconium oxide (ZrO 2 ) may include a ZA (ZrO 2 / Al 2 O 3 ) stack or a ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) stack. The ZA stack may have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on zirconium oxide (ZrO 2 ). The ZAZ stack may have a structure in which zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide (ZrO 2 ) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as zirconium-based layers (ZrO 2 -based layers). According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO 2 ). The stacked structure including hafnium oxide (HfO 2 ) may include a HA (HfO 2 / Al 2 O 3 ) stack or a HAH (HfO 2 / Al 2 O3 / HfO 2 ) stack. The HA stack may have a structure in which aluminum oxide (Al 2 O 3 ) is laminated on hafnium oxide (HfO 2 ). The HAH stack may have a structure in which hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) are sequentially laminated. The HA stack and the HAH stack may be referred to as hafnium oxide-based layers (HfO 2 -based layers). In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, aluminum oxide (Al 2 O 3 ) may have a larger bandgap than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Aluminum oxide (Al 2 O 3 ) may have a lower dielectric constant than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a larger bandgap than the high-k material. In addition to aluminum oxide (Al 2 O 3 ), the dielectric layer DE may include silicon oxide (SiO 2 ) as the high-bandgap material. Since the dielectric layer DE contains a high-bandgap material, leakage current can be suppressed. The high-bandgap material may be very thin. The thickness of the high-bandgap material is in the range of to . The high-bandgap material may be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a laminated structure in which the high-k material and the high-bandgap material are alternately laminated. For example, ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ), ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ), HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) or HAHAH(HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ). In the above lamination structure, aluminum oxide (Al 2 O 3 ) can be very thin. The thickness of the aluminum oxide is in the range of to .

[0032] According to another embodiment of the present invention, the dielectric layer DE may include a laminated structure, a lamination structure or a hybrid structure containing zirconium oxide, hafnium oxide and aluminum oxide.

[0033] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO 2 ). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0034] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) laminate and a tungsten nitride / tungsten (WN / W) laminate. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a laminate of titanium nitride / germanium silicon / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / germanium silicon / tungsten nitride (TiN / SiGe / WN) laminate, the germanium silicon may be a gap-filling material filling the cylindrical interior of the storage node SN, while the titanium nitride (TiN) may be used as the important plate node PN and the tungsten nitride may be a low-resistance material.

[0035] The plate line PL may be laterally oriented in the third direction D3 while being vertically oriented in the first direction D1. The plate line PL may have a vertical flat plate shape. The plate node PN and the plate line PL may include the same material.

[0036] In the memory device 100, memory cells MC may form a memory cell array MCA. The memory cell array MCA may include a stack of memory cells MC. The memory cells MC may be vertically stacked above the substrate structure LS along a first direction D1, and the memory cell array MCA may include memory cells MC that are laterally arranged in a second direction D2 and a third direction D3.

[0037] Figure 3A and Figure 3B FIG. shows a schematic structure of a memory device 200 according to another embodiment of the present invention. Figure 3B is a cross-sectional view taken along the Figure 3A line A-A' shown. In Figure 3A and Figure 3B , the same reference numerals as in Figures 1 to 2B denote the same constituent elements. Hereinafter, the same constituent elements will not be described again.

[0038] Referring to Figure 3A and Figure 3B , the memory device 200 may include a plurality of memory cells MC. The plurality of memory cells MC may be located above the substrate structure LS. Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include a word line WL that is vertically oriented in a first direction D1. The bit line BL may be laterally oriented in a third direction D3. The transistor TR may be laterally oriented in a second direction D2. The capacitor CAP may be laterally oriented from the transistor TR in a second direction D2. The substrate structure LS may include a peripheral circuit portion PC, and the peripheral circuit portion PC may include a plurality of control circuits for controlling the memory cells MC. The peripheral circuit portion PC may include a sense amplifier SA coupled to the bit line BL and a sub-word line driver coupled to the word line WL.

[0039] The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be laterally oriented from the bit line BL in a second direction D2. The word line WL may be vertically oriented in a first direction D1. The active layer ACT may include a first doped portion SR, a second doped portion DR, and channel portions CH1 and CH2. The channel portions CH1 and CH2 may be located between the first doped portion SR and the second doped portion DR. The first doped portion SR may provide a first edge of the active layer ACT, and the second doped portion DR may provide a second edge of the active layer ACT.

[0040] The channel portions CH1 and CH2 can be laterally oriented in the second direction D2. The channel portions CH1 and CH2 can be laterally oriented in the second direction D2 between the first doped portion SR and the second doped portion DR. The channel portions CH1 and CH2 can have a lateral flat plate shape. The length of the channel portions CH1 and CH2 in the second direction D2 can be greater than the length in the third direction D3. The channel portions CH1 and CH2 can be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are laterally oriented in the second direction D2, the channel portions CH1 and CH2 can be referred to as "lateral nanosheets". The channel portions CH1 and CH2 can be, for example, two channel portions including a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 can be vertically arranged in the first direction D1. A part of the word line WL can fill the space between the first channel portion CH1 and the second channel portion CH2. The thickness of the first channel portion CH1 and the thickness of the second channel portion CH2 can be the same. Here, the thickness can be the thickness in the first direction D1. The channel portions CH1 and CH2 can include a semiconductor material, a single crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the channel portions CH1 and CH2 can include single crystal silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS 2 and WS 2 .

[0041] The first doped portion SR can be coupled to the bit line BL. The first doped portion SR can be commonly coupled with the first edges of the channel portions CH1 and CH2. The first doped portion SR can be vertically oriented in the first direction D1. The second doped portion DR can be coupled to the capacitor CAP. The second doped portion DR can be coupled to the storage node SN of the capacitor CAP. The second doped portion DR can be commonly coupled with the second edges of the channel portions CH1 and CH2. The second doped portion DR can be vertically oriented in the first direction D1. The first doped portion SR, the channel portions CH1 and CH2, and the second doped portion DR can be integrally formed, and thus, the active layer ACT can be in an annular shape with an internal gap. The first doped portion SR can have an integrated source / drain structure commonly coupled with the first edges of the two channel portions CH1 and CH2, and the second doped portion DR can have an integrated source / drain structure commonly coupled with the second edges of the two channel portions CH1 and CH2.

[0042] The word line WL can have a surrounding shape that vertically surrounds the channel portions CH1 and CH2 simultaneously in the first direction D1. The word line WL having such a surrounding shape can be referred to as a gate-all-around (GAA) word line.

[0043] In the storage device 200, memory cells MC may form a memory cell array MCA. The memory cell array MCA may include a stack of memory cells MC. The memory cells MC may be vertically stacked above a substrate structure LS along a first direction D1, and the memory cell array MCA may include memory cells MC that are laterally arranged in a second direction D2 and a third direction D3.

[0044] Figure 4A and Figure 4B FIG. shows a schematic structure of a storage device 300 according to another embodiment of the present invention. Figure 4B is a cross-sectional view taken along line A-A' of Figure 4A . Referring to Figure 4A and Figure 4B , the same reference numerals as in Figures 1 to 3B may represent the same components. Hereinafter, the same components will not be described again.

[0045] Referring to Figure 4A and Figure 4B , the storage device 300 may include a plurality of memory cells MC. The memory cells MC may be located above a substrate structure LS. Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include a word line WL vertically oriented in a first direction D1. The bit line BL may be laterally oriented in a third direction D3. The transistor TR may be laterally oriented in a second direction D2. The capacitor CAP may be laterally oriented from the transistor TR in a second direction D2. The substrate structure LS may include a peripheral circuit portion PC, and the peripheral circuit portion PC may include a plurality of control circuits for controlling the memory cells MC. The peripheral circuit portion PC may include a sense amplifier SA coupled to the bit line BL and a sub-word line driver coupled to the word line WL.

[0046] The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be laterally oriented from the bit line BL in a second direction D2. The word line WL may be vertically oriented in a first direction D1. The active layer ACT may include first doped portions SR1 and SR2, a second doped portion DR, and channel portions CH1 and CH2. The channel portions CH1 and CH2 may be located between the first doped portions SR1 and SR2 and the second doped portion DR. The first doped portions SR1 and SR2 may provide first edges of the active layer ACT, and the second doped portion DR may provide a second edge of the active layer ACT.

[0047] The channel portions CH1 and CH2 can be laterally oriented in the second direction D2. The channel portions CH1 and CH2 can be laterally oriented in the second direction D2 between the first doping portions SR1 and SR2 and the second doping portion DR. The channel portions CH1 and CH2 can have a lateral flat shape. The length of the channel portions CH1 and CH2 in the second direction D2 can be greater than the length in the third direction D3. The channel portions CH1 and CH2 can be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are laterally oriented in the second direction D2, the channel portions CH1 and CH2 can be referred to as "lateral nanosheets". The channel portions CH1 and CH2 can include two channels, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 can be vertically arranged in the first direction D1. A portion of the word line WL can fill the space between the first channel portion CH1 and the second channel portion CH2. The thickness of the first channel portion CH1 and the thickness of the second channel portion CH2 can be the same. Here, the thickness can be the thickness in the first direction D1. The channel portions CH1 and CH2 can include a semiconductor material, a single-crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the channel portions CH1 and CH2 can include single-crystalline silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS 2 and WS 2 .

[0048] The first doping portions SR1 and SR2 can be coupled to the bit lines BL. The first doping portions SR1 and SR2 can be respectively coupled to the first edges of the channel portions CH1 and CH2. The first doping portions SR1 and SR2 can be vertically spaced apart in the first direction D1. The second doping portion DR can be coupled to the capacitor CAP. The second doping portion DR can be coupled to the storage node SN of the capacitor CAP. The second doping portion DR can be commonly coupled to the second edges of the channel portions CH1 and CH2. The second doping portion DR can be vertically oriented in the first direction D1. The first doping portions SR1 and SR2, the channel portions CH1 and CH2, and the second doping portion DR can be integrally formed. Thus, the active layer ACT can include an annular shape with an internal gap. The first doping portions SR1 and SR2 can have a split source / drain structure in which the first doping portions SR1 and SR2 are respectively coupled to the first edges of the two channel portions CH1 and CH2, and the second doping portion DR can have an integrated source / drain structure that is commonly coupled to the second edges of the two channel portions CH1 and CH2.

[0049] The word line WL may have a surrounding shape that vertically aligns in the first direction D1 around the channel portions CH1 and CH2. The word line WL having the surrounding shape may be referred to as a gate-all-around (GAA) word line.

[0050] In the memory device 300, memory cells MC may form a memory cell array MCA. The memory cell array MCA may include a stack of memory cells MC. The memory cells MC may be vertically stacked above the substrate structure LS in the first direction D1, and the memory cell array MCA may include memory cells MC that are laterally arranged in the second direction D2 and the third direction D3.

[0051] Figure 5A and Figure 5B FIG. shows a schematic structure of a memory device 400 according to another embodiment of the present invention. Figure 5B is a cross-sectional view taken along the Figure 5A line A-A' shown. Referring to Figure 5A and Figure 5B , the same reference numerals as in Figures 1 to 4B may represent the same constituent elements. Hereinafter, the same constituent elements will not be described again.

[0052] Referring to Figure 5A and Figure 5B , the memory device 400 may include a plurality of memory cells MC. The memory cells MC may be located above the substrate structure LS. Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include a word line WL that vertically aligns in the first direction D1. The bit line BL may be parallel to the substrate structure. The bit line BL may be laterally oriented in the third direction D3. The transistor TR may be laterally oriented in the second direction D2. The capacitor CAP may be laterally oriented from the transistor TR in the second direction D2. The substrate structure LS may include a peripheral circuit portion PC, and the peripheral circuit portion PC may include a plurality of control circuits for controlling the memory cells MC. The peripheral circuit portion PC may include a sense amplifier SA coupled to the bit line BL and a sub-word line driver coupled to the word line WL.

[0053] The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be laterally oriented in a second direction D2 from a bit line BL. The word line WL may be vertically oriented in a first direction D1. The active layer ACT may include first doped portions SR1 and SR2, second doped portions DR1 and DR2, and channel portions CH1 and CH2. The channel portions CH1 and CH2 may be located between the first doped portions SR1 and SR2 and the second doped portions DR1 and DR2. The first doped portions SR1 and SR2 may provide a first edge of the active layer ACT, and the second doped portions DR1 and DR2 may provide a second edge of the active layer ACT. The first doped portions SR1 and SR2 may have split source / drain structures respectively coupled to first edges of the two channel portions CH1 and CH2, and the second doped portions DR1 and DR2 may have split source / drain structures respectively coupled to second edges of the two channel portions CH1 and CH2.

[0054] The channel portions CH1 and CH2 may be laterally oriented in the second direction D2. The channel portions CH1 and CH2 may be laterally oriented in the second direction D2 between the first doped portions SR1 and SR2 and the second doped portions DR1 and DR2. The channel portions CH1 and CH2 may have a lateral flat plate shape. The length of the channel portions CH1 and CH2 in the second direction D2 may be greater than the length in a third direction D3. The channel portions CH1 and CH2 may be referred to as nanosheets or nanosheet channels. Since the channel portions CH1 and CH2 are laterally oriented in the second direction D2, the channel portions CH1 and CH2 may be referred to as "lateral nanosheets". The channel portions CH1 and CH2 may include two channels, for example, a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 may be vertically arranged in the first direction D1. A portion of the word line WL may fill the space between the first channel portion CH1 and the second channel portion CH2. The thickness of the first channel portion CH1 and the thickness of the second channel portion CH2 may be the same. Here, the thickness may be the thickness in the first direction D1. The channel portions CH1 and CH2 may include a semiconductor material, a single-crystalline semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the channel portions CH1 and CH2 may include single-crystalline silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS 2 and WS 2 .

[0055] The first doped portions SR1 and SR2 can be coupled to the bit line BL. The first doped portions SR1 and SR2 can be respectively coupled to the first edges of the channel portions CH1 and CH2. The first doped portions SR1 and SR2 can be vertically spaced apart in the first direction D1. The second doped portions DR1 and DR2 can be commonly coupled to the capacitor CAP. The second doped portions DR1 and DR2 can be coupled to the storage node SN of the capacitor CAP. The second doped portions DR1 and DR2 can be respectively coupled to the second edges of the channel portions CH1 and CH2. The second doped portions DR1 and DR2 can be vertically spaced apart in the first direction D1. The first doped portion SR1, the channel portion CH1, and the second doped portion DR1 can be integrated, and the first doped portion SR2, the channel portion CH2, and the second doped portion DR2 can be integrated. Thus, the active layer ACT can include a pair of nanosheets. For example, the lower first doped portion SR1, the first channel portion CH1, and the lower second doped portion DR1 can form a lower nanosheet, and the upper first doped portion SR2, the second channel portion CH2, and the upper second doped portion DR2 can form an upper nanosheet.

[0056] The word line WL can have a surrounding shape that surrounds the channel portions CH1 and CH2 and is vertically oriented in the first direction D1. The WL having the surrounding shape can be referred to as a gate-all-around (GAA) word line.

[0057] In the memory device 400, the memory cells MC can form a memory cell array MCA. The memory cell array MCA can include a stack of the memory cells MC. The memory cells MC can be vertically stacked above the substrate structure LS in the first direction D1, and the memory cell array MCA can include the memory cells MC arranged laterally in the second direction D2 and the third direction D3.

[0058] Figure 6 FIG. is a schematic diagram showing the structure of a memory device 500 according to another embodiment of the present invention. In Figure 6 In, the same reference numerals as in Figures 1 to 5B can denote the same constituent elements. Hereinafter, the same constituent elements will not be described again.

[0059] Refer to Figure 6, the memory device 500 may include a plurality of memory cells MC. The memory cells MC may be located above the substrate structure LS. Each memory cell MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include a word line WL vertically oriented in a first direction D1. The bit line BL may be horizontally oriented in a third direction D3. The transistor TR may be horizontally oriented in a second direction D2. The capacitor CAP may be horizontally oriented from the transistor TR in the second direction D2. The substrate structure LS may include a peripheral circuit portion PC, and the peripheral circuit portion PC may include a plurality of control circuits for controlling the memory cells MC. The peripheral circuit portion PC may include a sense amplifier SA coupled to the bit line BL and a sub-word line driver coupled to the word line WL.

[0060] The transistor TR may include a gate-all-around (GAA) transistor. The transistor TR may include an active layer ACTW and a word line WL. The active layer ACTW may be horizontally oriented from the bit line BL in the second direction D2. The word line WL may be vertically oriented in the first direction D1. The active layer ACTW may include a first doped portion SRW, a second doped portion DRW, and a channel portion CHW. The channel portion CHW may be located between the first doped portion SRW and the second doped portion DRW. The first doped portion SRW may provide a first edge of the active layer ACTW, and the second doped portion DRW may provide a second edge of the active layer ACTW.

[0061] The channel portion CHW may include at least two channels horizontally oriented in the second direction D2. The channel portion CHW may be horizontally oriented between the first doped portion SRW and the second doped portion DRW in the second direction D2. The channel portion CHW may have a horizontal line shape. The channel portion CHW may be referred to as "nano wires" or "nano wire channels". Since the channel portion CHW is horizontally oriented in the second direction D2, the channel portion CHW may be referred to as a "horizontal nano wire". The channel portion CHW may include at least two channel portions. The at least two channel portions CHW may be vertically arranged in the first direction D1. A portion of the word line WL may fill the space between the channel portions CHW. The channel portion CHW may include a semiconductor material, a single crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor, a metal compound, or a combination thereof. For example, the channel portion CHW may include single crystal silicon, polycrystalline silicon, germanium silicon, indium gallium zinc oxide (IGZO), MoS 2 or WS 2 .

[0062] The first doped portion SRW can be coupled to the bit line BL. The first doped portion SRW can be coupled to the first edges of the channel portions CHW respectively. The first doped portion SRW can be vertically spaced apart in the first direction D1. The second doped portion DRW can be commonly coupled to the capacitor CAP. The second doped portion DRW can be coupled to the storage node SN of the capacitor CAP. The second doped portion DRW can be coupled to the second edges of the channel portions CHW respectively. The second doped portion DRW can be vertically spaced apart in the first direction D1. The active layer ACTW can include a pair of nanowires. The first doped portion SRW can have a split source / drain structure in which the first doped portion SRW is coupled to the first edges of two channel portions CHW respectively, and the second doped portion DRW can have a split source / drain structure in which the second doped portion DRW is coupled to the second edges of two channel portions CHW respectively.

[0063] The word line WL can have a surrounding shape that surrounds the channel portion CHW and is vertically oriented in the first direction D1. The word line WL having the surrounding shape can be referred to as a gate-all-around (GAA) word line.

[0064] In the memory device 500, the memory cells MC can form a memory cell array MCA. The memory cell array MCA can include a stack of memory cells MC. The memory cells MC can be vertically stacked above the substrate structure LS along the first direction D1, and the memory cell array MCA can include memory cells MC that are laterally arranged in the second direction D2 and the third direction D3.

[0065] The memory devices 100 to 500 of the above embodiments can include memory cells MC, and each memory cell MC includes two channels, a vertical word line WL, and a lateral bit line BL to improve the on-current and gate controllability of the transistor TR.

[0066] Doubling the width of one channel results in a decrease in cell density. On the other hand, two channels enable the channel width to be doubled without reducing the cell density, and the area overlapping with the word line WL can be increased, which can improve the gate controllability. By applying the vertical word line of the gate-all-around (GAA) structure, the stacking height of the memory cells MC can be reduced.

[0067] In an embodiment of the present invention, the peripheral circuit portion PC can be located at a higher level than the memory cell array MCA.

[0068] According to an embodiment of the present invention, a memory device can include a transistor and a capacitor stacked in a three-dimensional manner above a substrate. In this way, the integration of the memory device can be improved.

[0069] According to an embodiment of the present invention, since the memory cell includes two channels, a vertical word line, and a horizontal bit line, the on-current and gate controllability of the transistor can be improved.

[0070] According to an embodiment of the present invention, since the transistor of the memory cell includes two nanosheet channels, the channel width can be doubled without reducing the cell density, and the area of overlap with the word line can be increased, thereby improving the gate controllability.

[0071] According to an embodiment of the present invention, the memory cell array can reduce the stacking height of the memory cell MC by applying a vertical word line of a gate-all-around (GAA) structure.

[0072] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A memory device, comprising: a substrate; bit lines that are horizontally oriented and parallel to the substrate; transistors that include two channels horizontally oriented from the bit lines and a word line vertically oriented and surrounding the two channels; and capacitors that are horizontally oriented from the transistors; wherein the two channels include two nanosheets horizontally oriented from the bit lines.

2. The memory device according to claim 1, wherein the two channels include single-crystalline semiconductor material, polycrystalline semiconductor material, oxide semiconductor, or metal compound.

3. The memory device according to claim 1, wherein The two channels include single-crystalline silicon, polycrystalline silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS 2 or WS 2 .

4. The memory device according to claim 1, further comprising: a first source / drain between a first edge of the two channels and the bit line; and a second source / drain between a second edge of the two channels and the capacitor.

5. The memory device according to claim 4, wherein the first source / drain has an integrated source / drain structure such that the first source / drain is commonly coupled to the first edge of the two channels, and wherein the second source / drain has a split source / drain structure such that the second source / drain is divided into two parts respectively coupled to the second edge of the two channels.

6. The memory device according to claim 4, wherein the first source / drain has an integrated source / drain structure such that the first source / drain is commonly coupled to the first edge of the two channels, and wherein the second source / drain has an integrated source / drain structure such that the second source / drain is commonly coupled to the second edge of the two channels.

7. The memory device according to claim 4, wherein the first source / drain has a split source / drain structure such that the first source / drain is divided into two parts respectively coupled to the first edge of the two channels, and wherein the second source / drain has an integrated source / drain structure such that the second source / drain is commonly coupled to the second edge of the two channels.

8. The memory device according to claim 4, wherein the first source / drain has a split source / drain structure such that the first source / drain is divided into two parts respectively coupled to the first edge of the two channels, and wherein the second source / drain has a split source / drain structure such that the second source / drain is divided into two parts respectively coupled to the second edge of the two channels.

9. The memory device according to claim 1, which further comprises: a gate dielectric layer surrounding the two channels.

10. The memory device according to claim 1, wherein the capacitor comprises: a cylindrical storage node coupled to the two channels and horizontally oriented; a dielectric layer over the cylindrical storage node; and a plate node over the dielectric layer.

11. The memory device according to claim 1, wherein the word line includes a metal-based material.

12. The memory device according to claim 1, wherein, the bit line comprises a metal-based material.

13. A memory device, comprising: a substrate; a bit line that is laterally oriented parallel to the substrate; a transistor that includes two channels laterally oriented from the bit line and a word line vertically oriented and surrounding the two channels; and a capacitor that is laterally oriented from the transistor; wherein the two channels include two nanowires laterally oriented from the bit line.

14. A memory device, comprising: a substrate that includes a peripheral circuit portion; and a memory cell array that includes a plurality of memory cells stacked vertically with respect to the peripheral circuit portion, wherein each of the memory cells includes: a bit line that is laterally oriented parallel to the substrate; a transistor that includes two nanosheet channels laterally oriented from the bit line and a word line vertically oriented and surrounding the two nanosheet channels; and a capacitor that is laterally oriented from the transistor.

15. The memory device according to claim 14, wherein, the two nanosheet channels include single-crystalline semiconductor material, polycrystalline semiconductor material, oxide semiconductor, or metal compound.

16. The memory device according to claim 14, wherein, The two nanosheet channels include single-crystalline silicon, polycrystalline silicon, silicon germanium, IGZO, MoS 2 or WS 2 .

17. The memory device according to claim 14, further comprising: a first source / drain between the first edge of the two nanosheet channels and the bit line; and a second source / drain between the second edge of the two nanosheet channels and the capacitor.

18. The memory device according to claim 17, wherein, the first source / drain has an integrated source / drain structure such that the first source / drain is commonly coupled to the first edge of the two nanosheet channels, and wherein the second source / drain has a split source / drain structure such that the second source / drain is divided into two portions respectively coupled to the second edge of the two nanosheet channels.

19. The memory device according to claim 17, wherein, the first source / drain has an integrated source / drain structure such that the first source / drain is commonly coupled to the first edge of the two nanosheet channels, and wherein the second source / drain has an integrated source / drain structure such that the second source / drain is commonly coupled to the second edge of the two nanosheet channels.

20. The memory device according to claim 17, wherein, the first source / drain has a split source / drain structure such that the first source / drain is divided into two portions respectively coupled to the first edge of the two nanosheet channels, and wherein the second source / drain has an integrated source / drain structure such that the second source / drain is commonly coupled to the second edge of the two nanosheet channels.

21. The memory device according to claim 17, wherein, the first source / drain has a split source / drain structure such that the first source / drain is divided into two portions respectively coupled to the first edge of the two nanosheet channels, and Wherein, the second source / drain has a split source / drain structure such that the second source / drain is divided into two parts respectively coupled to the second edges of the two nanosheet channels.

22. The memory device according to claim 14, further comprising: a gate dielectric layer surrounding the two nanosheet channels.

23. The memory device according to claim 14, wherein, the capacitor comprises: a cylindrical storage node coupled to the two nanosheet channels and oriented laterally; a dielectric layer over the cylindrical storage node; and a plate node over the dielectric layer.

24. The memory device according to claim 14, wherein, the memory cell array is located at a level higher than or lower than the level of the peripheral circuit portion.

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