A decision feedback equalizer and PAM-4 receiver

Abstract

The present invention provides a decision feedback equalizer and a PAM‑4 receiver. On the one hand, the parasitic capacitance is reduced by reducing the number of interfaces of the equalization taps, thereby reducing the summer settling time. On the other hand, the delay caused by the sampling decision device is reduced by increasing the bandwidth of the sampling stage and the input amplitude of the latch. Furthermore, the loop delay of the DFE is reduced comprehensively from two aspects, thereby solving the problem of tight timing margin.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more specifically, to a decision feedback equalizer and a PAM-4 receiver. Background Art

[0002] In recent years, with the development of the Internet and digital integrated circuits, especially the continuous increase in the speed of CPU (Central Processing Unit), the relatively low data transmission rate between chips, between backplanes, and even between local area networks has increasingly become a performance bottleneck for digital communication systems.

[0003] The serial interface has gradually replaced the parallel interface and become the mainstream high-speed interface because of its advantages such as fewer I / O pins, strong anti-interference ability, and no synchronization problems.

[0004] Among them, the serial interface consists of a transmitter and a receiver. The transmitter is used to convert the low-speed parallel signal into a high-speed serial signal and then send it to the channel. After receiving the signal, the receiver uses a clock data recovery device to recover the clock, then retimes and samples the input signal, and finally recovers the signal emitted by the emitter.

[0005] Due to the non-ideality of the channel and the continuous increase in data rate, factors such as skin effect, discontinuous transmission line impedance and dielectric loss cause serious distortion of the transmitted data, resulting in inter-symbol crosstalk. Then, the opening of the signal eye diagram received by the receiving end often cannot meet the system performance indicators, and the original signal cannot be restored, increasing the bit error rate. The inventors found that an important measure to solve this problem is to use equalization technology to compensate for the non-ideal characteristics of the channel and expand the bandwidth of the channel.

[0006] As an important equalization structure at the receiving end, the decision feedback equalizer (DFE) has analog input and digital output, and has the advantage of amplifying only the signal but not the noise.

[0007] As PAM-4 (Four-level Plus Amplitude Modulation) modulation replaces NRZ (Non-Retrun to Zero) modulation and becomes the mainstream modulation method for serial ports, DFE design also faces new challenges. Specifically, the DFE loop delay must be controlled within 1UI (Unit Interval) to ensure the correct timing relationship.

[0008] However, in the traditional structure, the equalization tap of the DFE needs to receive three-way data, the summer load is large, which limits the data increase, and the bandwidth of the traditional sampling and decision maker is limited, making it difficult to sample and decide on high-speed data streams. Summary of the invention

[0009] In view of this, in order to solve the above problems, the present invention provides a decision feedback equalizer and a PAM-4 receiver, and the technical solutions are as follows:

[0010] A decision feedback equalizer, comprising: first to fourth groups of sampling decision devices; each group of sampling decision devices is composed of three sampling decision devices; the first to fourth groups of sampling decision devices are driven by a four-phase clock;

[0011] In any group of sampling decision devices, the main tap inputs of the three sampling decision devices are used to respectively correspond to the three data after receiving level shift;

[0012] The outputs of the three sampling decision devices in the first group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the second group of sampling decision devices respectively;

[0013] The outputs of the three sampling decision devices in the second group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the first group of sampling decision devices respectively;

[0014] The outputs of the three sampling decision devices in the third group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the fourth group of sampling decision devices respectively;

[0015] The outputs of the three sampling decision devices in the fourth group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the third group of sampling decision devices respectively;

[0016] The first group of sampling decision makers and the second group of sampling decision makers are a data sampling decision maker group, and the third group of sampling decision makers and the fourth group of sampling decision makers are an edge sampling decision maker group.

[0017] Preferably, in the above decision feedback equalizer, the first to fourth groups of sampling decision devices are driven by a four-phase clock, including:

[0018] The first group of sampling decision devices is driven by a first clock signal, the third group of sampling decision devices is driven by a second clock signal, the second group of sampling decision devices is driven by a third clock signal, and the fourth group of sampling decision devices is driven by a fourth clock signal;

[0019] The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are four-phase clocks, and the phases thereof differ by 90° respectively.

[0020] Preferably, in the above decision feedback equalizer, the sampling decision device comprises: a summer, a sampling and holding module and a latch;

[0021] Wherein, the main tap input of the summer is used to receive one path of data among the three paths of data after level shifting;

[0022] The balanced tap input of the summer is used to receive the output of the corresponding sampling decision device in the other groups of sampling decision devices;

[0023] The first equalization strength control terminal of the summer is used to receive a first control signal;

[0024] The second equalization strength control terminal of the summer is used to receive a second control signal;

[0025] The first input end of the sampling and holding module is connected to the first output end of the summer, and the second input end of the sampling and holding module is connected to the second output end of the summer;

[0026] The voltage terminal of the sampling and holding module is used to receive a voltage signal;

[0027] The first control end of the sampling and holding module is used to receive the fifth clock signal, the second control end is used to receive the sixth clock signal, and the third control end is used to receive the seventh clock signal;

[0028] The voltage terminal of the latch is used to receive the voltage signal;

[0029] The first input end of the latch is connected to the first output end of the sampling and holding module, and the second input end of the latch is connected to the second output end of the sampling and holding module;

[0030] The control end of the latch is used to receive the fifth clock signal;

[0031] The first output terminal and the second output terminal of the latch serve as output terminals of the sampling decision device;

[0032] Wherein, the fifth clock signal and the sixth clock signal are used to control the working state of the sampling and holding module, and further control the working state of the latch;

[0033] The seventh clock signal is used to control the sampling speed of the sample and hold module.

[0034] Preferably, in the above decision feedback equalizer, the summer comprises: first to sixth field effect transistors;

[0035] The gate of the first field effect transistor and the gate of the second field effect transistor are used to correspond to one path of data among the three paths of data after receiving level shift;

[0036] The first electrode terminal of the first field effect transistor is connected to the first electrode terminal of the second field effect transistor, and the connection node is connected to the second electrode terminal of the fifth field effect transistor;

[0037] The first electrode terminal of the fifth field effect transistor is grounded, and the gate is used to receive the first control signal;

[0038] The second electrode terminal of the second field effect tube is connected to the second electrode terminal of the third field effect tube, and the connection node serves as the second output terminal of the summer;

[0039] The second electrode terminal of the first field effect transistor is connected to the second electrode terminal of the fourth field effect transistor, and the connection node serves as the first output terminal of the summer;

[0040] The gate of the third field effect tube and the gate of the fourth field effect tube are used to receive the output of the corresponding sampling decision device in the other groups of sampling decision devices;

[0041] The first electrode terminal of the third field effect transistor is connected to the first electrode terminal of the fourth field effect transistor, and the connection node is connected to the second electrode terminal of the sixth field effect transistor;

[0042] The first electrode terminal of the sixth field effect transistor is grounded, and the gate is used to receive the second control signal.

[0043] Preferably, in the above-mentioned decision feedback equalizer, the first to sixth field effect transistors are all N-type field effect transistors.

[0044] Preferably, in the above-mentioned decision feedback equalizer, the sampling and holding module includes: seventh to twelfth field effect transistors;

[0045] The first electrode end of the seventh field effect transistor, the first electrode end of the eighth field effect transistor, the first electrode end of the ninth field effect transistor and the first electrode end of the tenth field effect transistor are connected, and the connection node is used to receive the voltage signal;

[0046] The gate of the eighth field effect transistor is connected to the gate of the ninth field effect transistor, and the connection node is used to receive the fifth clock signal;

[0047] The second electrode end of the seventh field effect tube is connected to the second electrode end of the eighth field effect tube, and the connection node serves as the second output end of the sampling and holding module, and the connection node is connected to the second electrode end of the eleventh field effect tube;

[0048] The second electrode terminal of the ninth field effect tube is connected to the second electrode terminal of the tenth field effect tube, and the connection node serves as the first output terminal of the sampling and holding module, and the connection node is connected to the second electrode terminal of the twelfth field effect tube;

[0049] The gate of the eleventh field effect transistor is connected to the gate of the twelfth field effect transistor, and the connection node is used to receive the sixth clock signal;

[0050] The gate of the seventh field effect transistor and the gate of the tenth field effect transistor are used to receive the seventh clock signal;

[0051] The first electrode terminal of the eleventh field effect transistor serves as the first input terminal of the sampling and holding module;

[0052] The first electrode terminal of the twelfth field effect transistor serves as the second input terminal of the sampling and holding module.

[0053] Preferably, in the above decision feedback equalizer, the seventh to tenth field effect transistors are P-type field effect transistors;

[0054] The eleventh field effect transistor and the twelfth field effect transistor are N-type field effect transistors.

[0055] Preferably, in the above decision feedback equalizer, the latch comprises: thirteenth to seventeenth field effect transistors;

[0056] The first electrode terminal of the thirteenth field effect transistor is connected to the first electrode terminal of the fourteenth field effect transistor, and the connection node is used to receive the voltage signal;

[0057] The gate of the thirteenth field effect transistor is connected to the gate of the fifteenth field effect transistor, and the connection node serves as the second output terminal of the latch;

[0058] The second electrode terminal of the thirteenth field effect transistor is connected to the second electrode terminal of the fifteenth field effect transistor, and the connection node serves as the first output terminal of the latch;

[0059] The gate of the fourteenth field effect transistor is connected to the gate of the sixteenth field effect transistor, and the connection node also serves as the first output terminal of the latch;

[0060] The second electrode terminal of the fourteenth field effect transistor is connected to the second electrode terminal of the sixteenth field effect transistor, and the connection node also serves as the second output terminal of the latch;

[0061] The first electrode terminal of the fifteenth field effect transistor is connected to the first electrode terminal of the sixteenth field effect transistor, and the connection node is connected to the second electrode terminal of the seventeenth field effect transistor;

[0062] The first electrode terminal of the seventeenth field effect transistor is grounded, and the gate is used to receive the fifth clock signal.

[0063] Preferably, in the above decision feedback equalizer, the thirteenth field effect transistor and the fourteenth field effect transistor are P-type field effect transistors;

[0064] The fifteenth to seventeenth field effect transistors are N-type field effect transistors.

[0065] A PAM-4 receiver, the PAM-4 receiver comprising any one of the decision feedback equalizers described above.

[0066] Compared with the prior art, the present invention has the following beneficial effects:

[0067] A decision feedback equalizer provided by the present invention reduces parasitic capacitance and summer settling time by reducing the number of interfaces of equalization taps on the one hand; reduces the delay caused by the sampling decision device on the other hand by increasing the bandwidth of the sampling stage and increasing the input amplitude of the latch; thereby reducing the loop delay of the DFE from two aspects, solving the problem of tight timing margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0069] Figure 1 It is a schematic diagram of the principle of a traditional decision feedback equalizer;

[0070] Figure 2 It is a circuit structure diagram of a data sampling decision maker in a traditional decision feedback equalizer;

[0071] Figure 3 A schematic diagram of the principle of a decision feedback equalizer provided by an embodiment of the present invention;

[0072] Figure 4 A schematic diagram of the circuit structure of a sampling decision device provided by an embodiment of the present invention;

[0073] Figure 5 A schematic diagram of signal waveforms with and without introducing the seventh clock signal provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0074] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0075] During the invention process of the present application, the inventors discovered that the traditional DFE continued the architecture of NRZ modulation, and a half-speed two-tap DFE is used as an example for explanation.

[0076] refer to Figure 1 , Figure 1 Schematic diagram of the principle of a traditional decision feedback equalizer.

[0077] The decision feedback equalizer is composed of three sampling decision devices (corresponding to three data paths DH / D0 / DL after level shifting), each of which is driven by a four-phase clock CK0 / CK90 / CK180 / CK270.

[0078] Among them, VA0-VB0-VC0 are the three-bit thermometer codes output by the three-way sampling decision device driven by CK0; VA0 corresponds to data DH, VB0 corresponds to data D0, and VC0 corresponds to data DL.

[0079] VA90-VB90-VC90 are the three-bit thermometer codes output by the three-way sampling decision device driven by CK90; VA90 corresponds to data DH, VB90 corresponds to data D0, and VC90 corresponds to data DL.

[0080] VA180-VB180-VC180 are three-bit thermometer codes output by the three-way sampling decision device driven by CK180; VA180 corresponds to data DH, VB180 corresponds to data D0, and VC180 corresponds to data DL.

[0081] VA270-VB270-VC270 are the three-bit thermometer codes output by the three-way sampling decision device driven by CK270; VA270 corresponds to data DH, VB270 corresponds to data D0, and VC270 corresponds to data DL.

[0082] Because the decision feedback equalizer adopts a half-speed structure and the clock frequency is half of the baud rate, the CK0 and CK10 clocks correspond to the sampling decisions of two adjacent bits of data, and CK90 and CK270 correspond to the sampling of the transition edge.

[0083] The data sampling decision makers driven by CK0 and CK180 are cross-coupled, and the edge sampling decision makers driven by CK90 and CK270 are cross-coupled, that is, their respective outputs are used as inputs of each other's equalizing taps. In this way, the function of subtracting the weighted previous data from the current data can be realized, that is, a two-tap decision feedback equalizer is realized.

[0084] refer to Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a data sampling decision maker in a traditional decision feedback equalizer.

[0085] The data sampling decision device corresponding to VA0 is taken as an example for explanation, which is composed of a summer and a comparator.

[0086] The summer is used to subtract the weighted decision result (VA180 / VB180 / VC180) of the previous data from the current data DH to achieve an equalization operation.

[0087] The current data DH is the main tap data, the judgment result of the previous data is the balanced tap data, and the weight coefficient of the balanced tap is determined by the ratio of the tail current controlled by Vbm and Vbp.

[0088] The comparator determines the result of the level given by the output of the summer. If Vxp>Vxn, then VA0P>VA0N, otherwise VA0P<VA0N.

[0089] based on Figure 1 and Figure 2 The inventors found that in order to ensure the correct timing relationship in the DFE, the weighted summation of the current data and the previous data must be completed before the next sampling phase arrives. In other words, the loop delay of the DFE must be controlled within 1UI. This is the main challenge of the DFE design.

[0090] Among them, the inventors found that the main factors affecting the DFE loop delay are the setup time of the summer and the clock data delay of the comparator.

[0091] exist Figure 1 In the traditional decision feedback equalizer structure shown, the three-bit thermometer code obtained by the previous data judgment needs to be returned to the summer. Therefore, the equalization tap requires three interfaces, which greatly increases the load capacitance of the summer and prolongs the settling time.

[0092] The clock data delay of the comparator is mainly affected by the bandwidth and gain of the sampling stage. The wider the bandwidth, the faster the sampling speed. The higher the gain, the higher the signal amplitude at the end of sampling, and the faster the decision speed.

[0093] Improving bandwidth and gain can reduce latency, but bandwidth and gain restrict each other and are difficult to optimize effectively.

[0094] Based on this, the present invention provides a novel decision feedback equalizer, which reduces parasitic capacitance and summer settling time by reducing the number of interfaces of the equalization taps on the one hand; and reduces the delay caused by the sampling decision device by increasing the bandwidth of the sampling stage and increasing the input amplitude of the latch on the other hand; thereby reducing the loop delay of the DFE from two aspects and solving the problem of tight timing margin.

[0095] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0096] refer to Figure 3 , Figure 3 A schematic diagram of the principle of a decision feedback equalizer provided by an embodiment of the present invention.

[0097] The decision feedback equalizer comprises: first to fourth groups of sampling decision devices; each group of sampling decision devices is composed of three sampling decision devices; the first to fourth groups of sampling decision devices are driven by four-phase clocks CK0 / CK90 / CK180 / CK270;

[0098] In any group of sampling decision devices, the main tap inputs of the three sampling decision devices are used to respectively correspond to the three data DH / D0 / DL after receiving level shift;

[0099] The outputs of the three sampling decision devices in the first group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the second group of sampling decision devices respectively;

[0100] The outputs of the three sampling decision devices in the second group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the first group of sampling decision devices respectively;

[0101] The outputs of the three sampling decision devices in the third group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the fourth group of sampling decision devices respectively;

[0102] The outputs of the three sampling decision devices in the fourth group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the third group of sampling decision devices respectively;

[0103] The first group of sampling decision makers and the second group of sampling decision makers are a data sampling decision maker group, and the third group of sampling decision makers and the fourth group of sampling decision makers are an edge sampling decision maker group.

[0104] The first to fourth groups of sampling decision devices are driven by a four-phase clock and include:

[0105] The first group of sampling decision devices is driven by the first clock signal CK0, the third group of sampling decision devices is driven by the second clock signal CK90, the second group of sampling decision devices is driven by the third clock signal CK180, and the fourth group of sampling decision devices is driven by the fourth clock signal CK270;

[0106] The first clock signal CK0 , the second clock signal CK90 , the third clock signal CK180 , and the fourth clock signal CK270 are four-phase clocks, and the phases thereof differ by 90°.

[0107] In this embodiment, if Figure 1 As shown, no matter it is a data sampling decision device group or an edge sampling decision device group, in each group of sampling decision devices, the main tap of the first sampling decision device is used to receive the first data DH after level shifting, the main tap of the second sampling decision device is used to receive the second data D0 after level shifting, and the main tap of the third sampling decision device is used to receive the third data DL after level shifting;

[0108] Among them, VA0-VB0-VC0 are the three-bit thermometer codes output by the three-way sampling decision device driven by CK0; VA0 corresponds to data DH, VB0 corresponds to data D0, and VC0 corresponds to data DL.

[0109] VA90-VB90-VC90 are the three-bit thermometer codes output by the three-way sampling decision device driven by CK90; VA90 corresponds to data DH, VB90 corresponds to data D0, and VC90 corresponds to data DL.

[0110] VA180-VB180-VC180 are three-bit thermometer codes output by the three-way sampling decision device driven by CK180; VA180 corresponds to data DH, VB180 corresponds to data D0, and VC180 corresponds to data DL.

[0111] VA270-VB270-VC270 are the three-bit thermometer codes output by the three-way sampling decision device driven by CK270; VA270 corresponds to data DH, VB270 corresponds to data D0, and VC270 corresponds to data DL.

[0112] Further, such as Figure 3 As shown, the decision result of the equalization tap of each sampling decision device is returned as a single channel instead of Figure 1 As shown in the figure, only one equalization tap is needed for each sampling decision maker, thereby greatly reducing the parasitic capacitance and the settling time required for the summer in the sampling decision maker.

[0113] Optionally, in another embodiment of the present invention, reference Figure 4 , Figure 4 A schematic diagram of the circuit structure of a sampling decision device provided by an embodiment of the present invention.

[0114] The sampling decision device comprises: a summer, a sampling and holding module and a latch;

[0115] The main tap input of the summer is used to receive one path of the three paths of data corresponding to the level-shifted data; for example, the received data DH.

[0116] The equalization tap input of the summer is used to receive the output of the corresponding sampling decision maker in other groups of sampling decision makers; for example, the output of VA180.

[0117] The first equalization strength control terminal of the summer is used to receive a first control signal Vbm;

[0118] The second equalization strength control terminal of the summer is used to receive a second control signal Vbp;

[0119] The first input end of the sampling and holding module is connected to the first output end of the summer, and the second input end of the sampling and holding module is connected to the second output end of the summer;

[0120] The voltage terminal of the sampling and holding module is used to receive a voltage signal VDD;

[0121] The first control end of the sampling and holding module is used to receive the fifth clock signal φ1, the second control end is used to receive the sixth clock signal φ2, and the third control end is used to receive the seventh clock signal φ3;

[0122] The voltage terminal of the latch is used to receive the voltage signal VDD;

[0123] The first input end of the latch is connected to the first output end of the sampling and holding module, and the second input end of the latch is connected to the second output end of the sampling and holding module;

[0124] The control end of the latch is used to receive the fifth clock signal φ1;

[0125] The first output terminal VA0p and the second output terminal VA0n of the latch serve as output terminals of the sampling decision device;

[0126] Wherein, the fifth clock signal φ1 and the sixth clock signal φ2 are used to control the working state of the sampling and holding module, and further control the working state of the latch;

[0127] The seventh clock signal φ3 is used to control the sampling speed of the sample and hold module.

[0128] Optional, such as Figure 4 As shown, the summer includes: first to sixth field effect transistors;

[0129] The gate of the first field effect transistor M1 and the gate of the second field effect transistor M2 are used to correspond to receive one path of data DH among the three paths of data after level shifting;

[0130] The first electrode end of the first field effect transistor M1 is connected to the first electrode end of the second field effect transistor M2, and the connection node is connected to the second electrode end of the fifth field effect transistor M5;

[0131] The first electrode terminal of the fifth field effect transistor M5 is grounded, and the gate is used to receive the first control signal Vbm;

[0132] The second electrode end of the second field effect transistor M2 is connected to the second electrode end of the third field effect transistor M3, and the connection node serves as the second output end Vxn of the summer;

[0133] The second electrode end of the first field effect transistor M1 is connected to the second electrode end of the fourth field effect transistor M4, and the connection node serves as the first output end Vxp of the summer;

[0134] The gate of the third field effect transistor M3 and the gate of the fourth field effect transistor M4 are used to receive the output VA180 of the corresponding sampling decision device in the other groups of sampling decision devices;

[0135] The first electrode end of the third field effect transistor M3 is connected to the first electrode end of the fourth field effect transistor M4, and the connection node is connected to the second electrode end of the sixth field effect transistor M6;

[0136] The first electrode terminal of the sixth field effect transistor M6 is grounded, and the gate is used to receive the second control signal Vbp.

[0137] Among them, the first to sixth field effect transistors are all N-type field effect transistors.

[0138] Optional, such as Figure 4 As shown, the sampling and holding module includes: seventh to twelfth field effect transistors;

[0139] The first electrode end of the seventh field effect transistor M7, the first electrode end of the eighth field effect transistor M8, the first electrode end of the ninth field effect transistor M9 and the first electrode end of the tenth field effect transistor M10 are connected, and the connection node is used to receive the voltage signal VDD;

[0140] The gate of the eighth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9, and the connection node is used to receive the fifth clock signal φ1;

[0141] The second electrode end of the seventh field effect transistor M7 is connected to the second electrode end of the eighth field effect transistor M8, and the connection node serves as the second output end of the sampling and holding module, and the connection node is connected to the second electrode end of the eleventh field effect transistor M11;

[0142] The second electrode end of the ninth field effect transistor M9 is connected to the second electrode end of the tenth field effect transistor M10, and the connection node serves as the first output end of the sampling and holding module, and the connection node is connected to the second electrode end of the twelfth field effect transistor M12;

[0143] The gate of the eleventh field effect transistor M11 is connected to the gate of the twelfth field effect transistor M12, and the connection node is used to receive the sixth clock signal φ2;

[0144] The gate of the seventh field effect transistor M7 and the gate of the tenth field effect transistor M10 are used to receive the seventh clock signal φ3;

[0145] The first electrode terminal of the eleventh field effect transistor M11 serves as the first input terminal of the sampling and holding module;

[0146] The first electrode terminal of the twelfth field effect transistor M12 serves as the second input terminal of the sampling and holding module.

[0147] Wherein, the seventh to tenth field effect transistors are P-type field effect transistors;

[0148] The eleventh field effect transistor and the twelfth field effect transistor are N-type field effect transistors.

[0149] Optional, such as Figure 4 As shown, the latch includes: thirteenth to seventeenth field effect transistors;

[0150] The first electrode end of the thirteenth field effect transistor M13 is connected to the first electrode end of the fourteenth field effect transistor M14, and the connection node is used to receive the voltage signal VDD;

[0151] The gate of the thirteenth field effect transistor M13 is connected to the gate of the fifteenth field effect transistor M15, and the connection node serves as the second output terminal of the latch;

[0152] The second electrode terminal of the thirteenth field effect transistor M13 is connected to the second electrode terminal of the fifteenth field effect transistor M15, and the connection node serves as the first output terminal of the latch;

[0153] The gate of the fourteenth field effect transistor M14 is connected to the gate of the sixteenth field effect transistor M16, and the connection node also serves as the first output terminal of the latch;

[0154] The second electrode terminal of the fourteenth field effect transistor M14 is connected to the second electrode terminal of the sixteenth field effect transistor M16, and the connection node also serves as the second output terminal of the latch;

[0155] The first electrode terminal of the fifteenth field effect transistor M15 is connected to the first electrode terminal of the sixteenth field effect transistor M16, and the connection node is connected to the second electrode terminal of the seventeenth field effect transistor M17;

[0156] The first electrode terminal of the seventeenth field effect transistor M17 is grounded, and the gate is used for receiving the fifth clock signal φ1.

[0157] Wherein, the thirteenth field effect transistor and the fourteenth field effect transistor are P-type field effect transistors;

[0158] The fifteenth to seventeenth field effect transistors are N-type field effect transistors.

[0159] It should be noted that Figure 4 The circuit structure diagram of the sampling decision maker shown is illustrated by taking the sampling decision maker corresponding to VA0 as an example.

[0160] like Figure 4 As shown, in the summer, the main tap data is the level-shifted data DH, the balanced tap data has only one channel VA180, and the balanced strength is determined by the ratio of the tail current controlled by the first control signal Vbm and the second control signal Vbp.

[0161] When the fifth clock signal φ1 is at a low level and the sixth clock signal φ2 is at a high level, the eighth field effect transistor M8, the ninth field effect transistor M9, the eleventh field effect transistor M11 and the twelfth field effect transistor M12 are turned on, and the latch is in a non-working state. At this time, it is a sampling state, and the difference between the data DH and the data VA180 is amplified and sent to the output end.

[0162] When the fifth clock signal φ1 is at a high level and the sixth clock signal φ2 is at a low level, the eighth field effect transistor M8, the ninth field effect transistor M9, the eleventh field effect transistor M11 and the twelfth field effect transistor M12 are turned off, and the latch is in a working state, which is a judgment state.

[0163] The cross-coupling inside the latch is a positive feedback loop. If the difference between DH and VA180 is greater than 0 at the end of the sampling period, the positive feedback will pull VOP up to VDD and VON down to ground. Otherwise, VOP will be pulled down to ground and VON will be pulled down to VDD to achieve correct level judgment.

[0164] From the above description, it can be seen that a sampling and holding module is added to the sampling decision device, and its own working state is controlled by the eleventh field effect transistor M11 and the twelfth field effect transistor M12. Then, firstly, in the decision stage, the first field effect transistor M1 and the second field effect transistor M2 are separated from the output node by the eleventh field effect transistor M11 and the twelfth field effect transistor M12, and the parasitic capacitance of the first field effect transistor M1 and the second field effect transistor M2 does not affect the decision speed of the latch, so large-sized first field effect transistors M1 and second field effect transistors M2 can be selected to improve the gain.

[0165] Secondly, the control clock is full swing, so the small-sized eleventh field effect transistor M11 and the twelfth field effect transistor M12 can well control the transition of the working state of the sampling and holding module, reduce the parasitic capacitance at the output end, increase the bandwidth, and thus increase the sampling speed.

[0166] Finally, the kick-back noise of the latch is isolated by the eleventh field effect transistor M11 and the twelfth field effect transistor M12, reducing the noise impact.

[0167] Furthermore, the seventh clock signal φ3 is introduced in the sampling stage to expand the bandwidth and improve the sampling speed. The fifth clock signal φ1 and the sixth clock signal φ2 are a pair of half-speed differential clocks, and the seventh clock signal φ3 is a clock signal with a 90° phase difference between the fifth clock signal φ1 and the clock signal, which is generated by a NAND gate after each inversion. The seventh clock signal φ3 is a 25% duty cycle clock, which differs from the fifth clock signal φ1 by about two inverters of delay 2T. inv .

[0168] refer to Figure 5 , Figure 5 A schematic diagram of signal waveforms with and without introducing the seventh clock signal provided in an embodiment of the present invention.

[0169] The sampling phase can be divided into two phases: invalid sampling (Invalid Tracking) and valid sampling (Valid Tracking).

[0170] The period from the falling edge of the fifth clock signal φ1 to the time when the output signals Vxp and Vxn of the summer jump to the 0V crossing point is an invalid sampling phase, because this section of the signal has been sampled by another sampling decision device driven by an inverted clock.

[0171] The period from when the output signals Vxp and Vxn of the summer jump to 0V to the rising edge of the fifth clock signal φ1 is the effective sampling phase.

[0172] When the fifth clock signal φ1 is at a low level, the latch is in an inoperative state and the sampling phase begins.

[0173] If the seventh clock signal φ3 is not used, the effective sampling phase is divided into t r1 and t a1 Two stages.

[0174] t r1 Refers to the time required from Vxp and Vxn jumping to 0V to the time required for output VA0P and VA0N jumping to 0V, t a1 Refers to the time required from the output jumping to 0V to the rising edge of the fifth clock signal φ1.

[0175] t r1 The sampling phase really starts at the end of the period, reducing t r1 It means that the output signal can reach the 0V crossover point faster, thereby increasing the sampling speed and reducing the DFE loop delay.

[0176] If the seventh clock signal φ3 is introduced into the sampling decision device, the falling edge of the fifth clock signal φ1 is delayed by 2T. inv After that, the seventh clock signal φ3 has a falling edge, at which time the seventh field effect transistor M7 and the tenth field effect transistor M10 are turned on, the output impedance is reduced, the bandwidth is expanded, and the speed of the output jumping to 0V is accelerated, t r1 Reduced to t r2 , and t a1 Increase to t a2 .

[0177] t a2 It can be divided into t 1a2 and t 2a2 Two parts, in t 1a2 During the phase, the seventh clock signal φ3 remains at a low level to provide a wide bandwidth to increase the operating speed. 2a2 In the stage, the seventh clock signal φ3 becomes high level, the seventh field effect transistor M7 and the tenth field effect transistor M10 are turned off, the output impedance increases, and the gain is improved.

[0178] At the end of the sampling phase, the output amplitude rises from A1 to A2, increasing the input amplitude of the latch and thus reducing the time required for latching.

[0179] From the above description, it can be seen that the decision feedback equalizer reduces the parasitic capacitance and the summer settling time by reducing the number of interfaces of the equalization taps on the one hand; on the other hand, it reduces the delay caused by the sampling decision device by increasing the bandwidth of the sampling stage and increasing the input amplitude of the latch; and thus reduces the loop delay of the DFE from two aspects, solving the problem of tight timing margin.

[0180] Further, based on all the above embodiments of the present invention, a PAM-4 receiver is provided in another embodiment of the present invention. The PAM-4 receiver includes the decision feedback equalizer described in the above embodiments.

[0181] The above is a detailed introduction to a decision feedback equalizer and a PAM-4 receiver provided by the present invention. In this article, specific examples are used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

[0182] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0183] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0184] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A decision feedback equalizer, characterized in that: The decision feedback equalizer comprises: first to fourth groups of sampling decision devices; each group of sampling decision devices is composed of three sampling decision devices; the first to fourth groups of sampling decision devices are driven by a four-phase clock; In any group of sampling decision devices, the main tap inputs of the three sampling decision devices are used to respectively correspond to the three data after receiving level shift; The outputs of the three sampling decision devices in the first group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the second group of sampling decision devices respectively; The outputs of the three sampling decision devices in the second group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the first group of sampling decision devices respectively; The outputs of the three sampling decision devices in the third group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the fourth group of sampling decision devices respectively; The outputs of the three sampling decision devices in the fourth group of sampling decision devices correspond to the inputs of the equalization taps of the three sampling decision devices in the third group of sampling decision devices respectively; The first group of sampling decision makers and the second group of sampling decision makers are a data sampling decision maker group, and the third group of sampling decision makers and the fourth group of sampling decision makers are an edge sampling decision maker group.

2. The decision feedback equalizer according to claim 1, characterized in that: The first to fourth groups of sampling decision devices are driven by a four-phase clock and include: The first group of sampling decision devices is driven by a first clock signal, the third group of sampling decision devices is driven by a second clock signal, the second group of sampling decision devices is driven by a third clock signal, and the fourth group of sampling decision devices is driven by a fourth clock signal; The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are four-phase clocks, and the phases thereof differ by 90° respectively.

3. The decision feedback equalizer according to claim 1, characterized in that: The sampling decision device comprises: a summer, a sampling and holding module and a latch; The main tap input of the summer is used to receive one path of data among the three paths of data after level shifting. The balanced tap input of the summer is used to receive the output of the corresponding sampling decision device in the other groups of sampling decision devices; The first equalization strength control terminal of the summer is used to receive a first control signal; The second equalization strength control terminal of the summer is used to receive a second control signal; The first input end of the sampling and holding module is connected to the first output end of the summer, and the second input end of the sampling and holding module is connected to the second output end of the summer; The voltage terminal of the sampling and holding module is used to receive a voltage signal; The first control end of the sampling and holding module is used to receive the fifth clock signal, the second control end is used to receive the sixth clock signal, and the third control end is used to receive the seventh clock signal; The voltage terminal of the latch is used to receive the voltage signal; The first input end of the latch is connected to the first output end of the sampling and holding module, and the second input end of the latch is connected to the second output end of the sampling and holding module; The control end of the latch is used to receive the fifth clock signal; The first output terminal and the second output terminal of the latch serve as output terminals of the sampling decision device; Wherein, the fifth clock signal and the sixth clock signal are used to control the working state of the sampling and holding module, and further control the working state of the latch; The seventh clock signal is used to control the sampling speed of the sample and hold module.

4. The decision feedback equalizer according to claim 3, characterized in that: The summer includes: first to sixth field effect transistors; The gate of the first field effect transistor and the gate of the second field effect transistor are used to correspond to one path of data among the three paths of data after receiving level shift; The first electrode terminal of the first field effect transistor is connected to the first electrode terminal of the second field effect transistor, and the connection node is connected to the second electrode terminal of the fifth field effect transistor; The first electrode terminal of the fifth field effect transistor is grounded, and the gate is used to receive the first control signal; The second electrode terminal of the second field effect tube is connected to the second electrode terminal of the third field effect tube, and the connection node serves as the second output terminal of the summer; The second electrode terminal of the first field effect transistor is connected to the second electrode terminal of the fourth field effect transistor, and the connection node serves as the first output terminal of the summer; The gate of the third field effect tube and the gate of the fourth field effect tube are used to receive the output of the corresponding sampling decision device in the other groups of sampling decision devices; The first electrode terminal of the third field effect transistor is connected to the first electrode terminal of the fourth field effect transistor, and the connection node is connected to the second electrode terminal of the sixth field effect transistor; The first electrode terminal of the sixth field effect transistor is grounded, and the gate is used to receive the second control signal.

5. The decision feedback equalizer according to claim 4, characterized in that: The first to sixth field effect transistors are all N-type field effect transistors.

6. The decision feedback equalizer according to claim 3, characterized in that: The sampling and holding module includes: seventh to twelfth field effect transistors; The first electrode end of the seventh field effect transistor, the first electrode end of the eighth field effect transistor, the first electrode end of the ninth field effect transistor and the first electrode end of the tenth field effect transistor are connected, and the connection node is used to receive the voltage signal; The gate of the eighth field effect transistor is connected to the gate of the ninth field effect transistor, and the connection node is used to receive the fifth clock signal; The second electrode end of the seventh field effect tube is connected to the second electrode end of the eighth field effect tube, and the connection node serves as the second output end of the sampling and holding module, and the connection node is connected to the second electrode end of the eleventh field effect tube; The second electrode terminal of the ninth field effect tube is connected to the second electrode terminal of the tenth field effect tube, and the connection node serves as the first output terminal of the sampling and holding module, and the connection node is connected to the second electrode terminal of the twelfth field effect tube; The gate of the eleventh field effect transistor is connected to the gate of the twelfth field effect transistor, and the connection node is used to receive the sixth clock signal; The gate of the seventh field effect transistor and the gate of the tenth field effect transistor are used to receive the seventh clock signal; The first electrode terminal of the eleventh field effect transistor serves as the first input terminal of the sampling and holding module; The first electrode terminal of the twelfth field effect transistor serves as the second input terminal of the sampling and holding module.

7. The decision feedback equalizer according to claim 6, characterized in that: The seventh to tenth field effect transistors are P-type field effect transistors; The eleventh field effect transistor and the twelfth field effect transistor are N-type field effect transistors.

8. The decision feedback equalizer according to claim 3, characterized in that: The latch comprises: thirteenth to seventeenth field effect transistors; The first electrode terminal of the thirteenth field effect transistor is connected to the first electrode terminal of the fourteenth field effect transistor, and the connection node is used to receive the voltage signal; The gate of the thirteenth field effect transistor is connected to the gate of the fifteenth field effect transistor, and the connection node serves as the second output terminal of the latch; The second electrode terminal of the thirteenth field effect transistor is connected to the second electrode terminal of the fifteenth field effect transistor, and the connection node serves as the first output terminal of the latch; The gate of the fourteenth field effect transistor is connected to the gate of the sixteenth field effect transistor, and the connection node also serves as the first output terminal of the latch; The second electrode terminal of the fourteenth field effect transistor is connected to the second electrode terminal of the sixteenth field effect transistor, and the connection node also serves as the second output terminal of the latch; The first electrode terminal of the fifteenth field effect transistor is connected to the first electrode terminal of the sixteenth field effect transistor, and the connection node is connected to the second electrode terminal of the seventeenth field effect transistor; The first electrode terminal of the seventeenth field effect transistor is grounded, and the gate is used to receive the fifth clock signal.

9. The decision feedback equalizer according to claim 8, characterized in that: The thirteenth field effect transistor and the fourteenth field effect transistor are P-type field effect transistors; The fifteenth to seventeenth field effect transistors are N-type field effect transistors.

10. A PAM-4 receiver, characterized in that: The PAM-4 receiver comprises the decision feedback equalizer according to any one of claims 1-9.

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