Light emitting diode and method of forming a light emitting diode

Abstract

A method of forming a light emitting diode (LED) precursor includes forming a first semiconductor layer including a Group III nitride on a substrate, selectively removing portions of the first semiconductor layer to form a mesa structure, and forming a monolithic LED structure. According to the method, the first semiconductor layer has a growth surface on a side of the first semiconductor layer opposite the substrate. According to the method, the first semiconductor layer is selectively removed to form the mesa structure such that the growth surface of the first semiconductor layer includes a mesa surface and a bulk semiconductor surface. Further, the monolithic LED structure is formed on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface, the monolithic LED structure includes multiple layers, each layer including a Group III nitride, the monolithic LED structure includes a second semiconductor layer, an active layer disposed on the second semiconductor layer, the active layer configured to produce light, and a p-type semiconductor layer disposed on the active layer. A potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface. The potential barrier surrounds the first portion of the p-type semiconductor layer covering the mesa surface.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to Group III nitride semiconductors. In particular, the present disclosure relates to Light Emitting Diodes (LEDs) comprising Group III nitride semiconductors. BACKGROUND

[0002] Micro-LED arrays are typically defined as arrays of LEDs with a size of 100 x 100 pm 2 or less. Micro-LED arrays are self-emissive components in micro-displays / projectors, suitable for use in a variety of devices, such as smart watches, head-mounted displays, head-up displays, video cameras, viewfinders, multi-point excitation sources, and micro-projectors.

[0003] One class of micro-LED arrays comprises a plurality of LEDs formed from Group III nitrides. Group III nitride LEDs are inorganic semiconductor LEDs, comprising, for example, GaN and alloys thereof, with InN and AlN in the active light-emitting region. In contrast to conventional large-area LEDs, such as organic light emitting diodes (OLEDs), in which the light-emitting layer is an organic compound, Group III nitride LEDs can be driven at significantly higher current densities, and emit higher optical power densities. As a result, the higher luminosity (brightness), defined as the amount of light emitted per unit area of a light source in a given direction, makes micro-LEDs suitable for applications that require or benefit from high brightness. For example, applications that benefit from high brightness can include displays in high brightness environments, or projectors. Furthermore, Group III nitride micro-LED arrays are known to have a relatively high luminous efficiency (expressed in lumens per watt (lm / W)) compared to other conventional large-area LEDs. The relatively high luminous efficiency of Group III nitride micro-LED arrays compared to other light sources reduces power consumption, and makes micro-LEDs particularly suitable for use in portable devices.

[0004] One method of forming micro-LEDs, and in particular arrays of micro-LEDs, from group III nitrides is selective area growth (SAG), such as described in US-B-7,087,932. In the selective area growth technique, a mask is patterned on a buffer layer. The material in the mask is such that, under the growth conditions, additional material does not grow directly on the mask, but only in holes that expose part of the surface of the underlying buffer layer. Another noteworthy feature of the selective area growth of group III nitrides growing in the

[0001] direction is that, depending on growth parameters such as growth temperature, pressure and V / III ratio, tilted facets relative to the (0001) plane (also known as the c-plane) are obtained around the periphery of the growing portion of the c-plane semiconductor defined by the opening areas of the patterned mask. The tilted facets are typically along the

[0001] direction of the wurtzite crystal. or plane orientation and exhibits a reduced polarization field compared to a c-plane surface (semipolar surface).

[0005] It is an object of the present invention to provide an improved method for forming LED precursors, and improved LED precursors that address at least one problem associated with prior art methods and arrays, or at least provide a commercially viable alternative thereto. Summary of the Invention

[0006] The present inventors have recognized that the SAG method is highly dependent on the geometry of the layers / devices being fabricated. Consequently, performing the same SAG fabrication process on substrates with different mask geometries can result in undesirable local variations in doping profiles and layer compositions due to local variations in aperture size. Furthermore, doping profiles and layer compositions can also vary across substrates due to layout differences. That is, the doping profile / alloy composition of each layer of an LED device formed using SAG can depend on the device geometry. Consequently, slight variations in device geometry or device arrays can require recalibration of the SAG process for each layer of the device.

[0007] Furthermore, the inventors have recognized that, in the SAG process, the material of the mask layer may be incorporated into the deposited structure. For example, during the manufacturing process, elements within the mask layer may diffuse into the material grown by SAG, thereby causing undesirable doping of the grown LED structure. In particular, materials including Si or O (e.g., SiN x , SiO2) can provide a Si or O dopant source for the III-nitride layer grown by SAG.

[0008] According to a first aspect of the present disclosure, a method for forming a light-emitting diode precursor is provided. The method comprises:

[0009] (a) forming a first semiconductor layer comprising a Group III nitride on a substrate, the first semiconductor layer having a growth surface on a side of the first semiconductor layer opposite the substrate;

[0010] (b) selectively removing part of the first semiconductor layer to form a mesa structure such that the growth surface of the first semiconductor layer comprises a mesa surface and a bulk semiconductor surface;

[0011] (c) forming a monolithic LED structure on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising a plurality of layers, each layer comprising a Group III nitride, the monolithic LED structure comprising:

[0012] - a second semiconductor layer;

[0013] - an active layer disposed on the second semiconductor layer, the active layer being configured to generate light; and

[0014] - a p-type semiconductor layer disposed on the active layer,

[0015] wherein a potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface.

[0016] In the SAG method, the monolithic LED structure can be grown on the exposed portion of the buffer layer. The monolithic LED structure is not grown on the portion of the buffer layer covered by the mask layer. In the method of the first aspect, the monolithic LED structure is overgrown on the substrate in the absence of a mask layer. In view of this, the method of manufacturing the monolithic LED structure is a maskless overgrowth method. Accordingly, the monolithic LED structure is formed on the growth surface of the first semiconductor layer. Thus, the layers of the monolithic LED structure are formed on the growth surface to cover the mesa surface and the bulk semiconductor surface of the first semiconductor layer.

[0017] The mesa structure formed on the growth surface helps to define the geometry of the monolithic LED structure. Thus, in contrast to the known SAG method, a mask layer is not required to define an aperture for selective growth of the LED structure. Instead, the monolithic LED structure is grown over the growth surface to cover the mesa structure. By covering the mesa structure, the monolithic LED structure formed can have a tilted facet similar to a monolithic LED structure grown by the SAG method known in the art.

[0018] Advantageously, the method of the first aspect allows the monolithic LED structure to be formed on the growth surface in the absence of a mask layer. Thus, the method of the first aspect reduces or eliminates problems associated with material recovery and mask layer contamination.

[0019] It will be appreciated that the method of the first aspect results in a monolithic LED structure having a substantially planar upper surface surrounded by a tilted sidewall. In view of this, the monolithic LED structure can have a substantially trapezoidal cross-section. Such a trapezoidal cross-section can have increased light extraction efficiency as the tilted sidewall of the trapezoidal cross-section can direct a greater proportion of light towards the light emitting surface of the LED precursor.

[0020] Furthermore, the method of the first aspect involves forming a layer of a monolithic LED structure on a growth surface, the growth surface comprising a mesa surface and a bulk semiconductor surface. The layer of the monolithic LED structure can be formed using a manufacturing process similar to SAG. However, in the method of the first aspect, the layer of the monolithic LED structure is formed across the entire growth surface (i.e. there is no mask layer). As such, the formation of the layer of the monolithic LED structure is less sensitive to changes in the geometry of the LED precursor to be formed. As such, the method of forming the LED precursor can reduce or eliminate the calibration process performed each time the geometry of the device is changed for forming the layer of the monolithic LED precursor.

[0021] In particular, in the method of the first aspect, the geometry of the LED precursor can be influenced by the geometry of the mesa structure formed. For example, when forming an LED precursor having a trapezoidal cross-section, the height and surface area of the mesa structure can be altered to control the desired height and surface area of the LED precursor formed. In view of this, the aspect ratio of the LED precursor formed can be adjusted using a selective removal step. Regardless of the aspect ratio of the LED precursor, the subsequent step of depositing a monolithic LED structure on the mesa structure can remain constant. In contrast, in a SAG process, changes in the aspect ratio of the LED structure trapezoidal cross-section can require re-calibration of one or more deposition steps.

[0022] It will be appreciated that, unlike SAG techniques, the monolithic LED structure is grown across the growth surface, including across the bulk semiconductor surface. In order to confine charge carriers within the portion of the monolithic LED structure defined by the mesa structure, a potential barrier is provided in a p-type layer of the monolithic LED structure. The p-type layer is disposed between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface to confine charge carriers flowing through the first portion of the p-type layer (i.e. to confine charge carriers within the mesa structure).

[0023] The term “precursor” in the LED precursor, it is noted that the LED precursors described do not necessarily include electrical contacts for the LEDs, for example, to allow light emission, nor associated circuitry. Of course, the method of forming the LED precursor of the first aspect does not preclude the addition of further electrical contacts and associated circuitry. In view of this, the use of the term precursor in this disclosure is intended to include the final product (i.e. the LED, LED array, etc.).

[0024] In some embodiments, the first semiconductor layer can be an n-type doped semiconductor layer. That is, the first semiconductor layer can include electron donor dopants.

[0025] In some embodiments, the second semiconductor layer can be an n-type doped semiconductor layer. In some embodiments in which the first semiconductor layer includes an n-type doped semiconductor layer, the second semiconductor layer can include a lower density of electron donors.

[0026] Alternatively, in some embodiments, the second semiconductor layer includes an undoped III-nitride. By providing the second semiconductor layer as an undoped layer (i.e., not including any intentional doping) (or a lower charge carrier density), the resistivity of the resulting monolithic LED structure can be increased in the sidewall region of the LED structure. As a result, charge carriers can be more effectively confined in the mesa structure and through the multiple layers provided on the mesa surface, thereby improving the efficiency of the LED.

[0027] In some embodiments, the second semiconductor layer is formed on the growth surface to provide a sloped sidewall extending between a portion of the second semiconductor layer on the mesa surface of the first semiconductor layer and a portion of the second semiconductor layer on the bulk semiconductor surface of the first semiconductor layer. Thus, the second semiconductor layer can be overgrown on the mesa structure of the first semiconductor layer to provide a III-nitride semiconductor layer including a mesa surface and surrounded by a sloped sidewall, on which an active layer of an LED can be formed. Importantly, such a structure can be formed without a mask layer.

[0028] In some embodiments, the active layer is configured to generate light of a first wavelength. For example, the active layer can be configured to generate light having a wavelength of at least 400 nm. In view of this, the active layer can generate visible light suitable for use in an LED display. In some embodiments, the active layer can generate light having a wavelength of no more than 700 nm. In some embodiments, the active layer can include a plurality of quantum wells (a multiple quantum well layer).

[0029] According to embodiments of the present disclosure, the potential barrier in the p-type layer for confining charge carriers within the mesa structure can be provided in a number of ways.

[0030] In some embodiments, the p-type semiconductor layer includes Al and is formed such that a concentration of Al included in a sidewall portion of the p-type semiconductor layer is higher than a concentration of Al included in a first portion of the p-type semiconductor layer covering the mesa surface, such that a potential barrier is provided between the first portion of the p-type semiconductor layer and the second portion of the p-type semiconductor layer.

[0031] In some embodiments, portions of the p-type semiconductor layer are selectively removed that surround the first portions of the p-type semiconductor layer that overlie the mesa structures. For example, the portions of the p-type semiconductor layer can be selectively removed by etching. In some embodiments, the portions of the p-type semiconductor layer (that are selectively removed) that surround the mesa structures can extend only part way through the thickness of the p-type semiconductor layer. In view of this, the remaining portions of the p-type semiconductor layer can comprise a relatively thin portion having a higher electrical resistance, thereby providing a barrier. In some embodiments, the portions of the p-type semiconductor layer (that are selectively removed) that surround the mesa structures can extend through at least the thickness of the p-type semiconductor layer. Thus, the barrier formed can be defined by the void created, or the void can be subsequently filled by an insulating material.

[0032] According to a second aspect of the present disclosure, there is provided a method of forming an LED array precursor. The method comprises:

[0033] (a) forming a first semiconductor layer comprising a Group III nitride on a substrate, the first semiconductor layer having a growth surface on a side of the first semiconductor layer opposite the substrate;

[0034] (b) selectively removing portions of the first semiconductor layer to form a plurality of mesa structures, such that the growth surface of the first semiconductor layer comprises a plurality of mesa surfaces and a bulk semiconductor surface;

[0035] (c) forming a monolithic LED array structure on the growth surface of the first semiconductor layer, such that the monolithic LED array structure overlies the mesa surfaces and the bulk semiconductor surface, the monolithic LED array structure comprising a plurality of layers, each layer formed from a Group III nitride, the monolithic LED array structure comprising:

[0036] - an n-type semiconductor layer;

[0037] - an active layer disposed on the n-type semiconductor layer, the active layer being configured to generate light; and

[0038] - a p-type semiconductor layer disposed on the active layer;

[0039] wherein a barrier is provided between each mesa portion of the p-type semiconductor layer overlying each mesa surface and a bulk portion of the p-type semiconductor layer overlying the bulk semiconductor surface, the barrier surrounding each mesa portion of the p-type semiconductor layer overlying the mesa surface.

[0040] The method according to the second aspect of the present invention provides a method of forming a plurality of monolithic LED structures on a substrate, wherein each monolithic structure formed is similar to those formed by the method according to the first aspect of the present invention. Thus, the method according to the second aspect can comprise all of the important features described above in relation to the first aspect.

[0041] An array refers to LEDs formed in which the LEDs are intentionally spaced apart on a monolithic structure and typically form a regular array, such as a hexagonally close-packed array or a square packed array of LEDs.

[0042] According to a third aspect of the application, there is provided an LED precursor. The LED precursor comprises a first semiconductor layer and a monolithic LED structure. The first semiconductor layer comprises a III-nitride, the first semiconductor layer comprising a mesa structure extending from a major surface of the first semiconductor layer to define a growth surface comprising a bulk semiconductor surface and a mesa surface. The monolithic LED structure is disposed on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface. The monolithic LED structure comprises a plurality of layers, each layer comprising a III-nitride, the monolithic LED structure comprising: an n-type semiconductor layer; an active layer disposed on the n-type semiconductor layer, the active layer configured to generate light; and a p-type semiconductor layer disposed on the active layer. A barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface, the barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface.

[0043] The LED precursor according to the third aspect provides an LED precursor that can be formed by the method of the first aspect. Accordingly, the LED precursor according to the third aspect can comprise features corresponding to all the important features of the first aspect described above.

[0044] In some embodiments, the height of the mesa structure (perpendicular to the bulk semiconductor surface 26) is equal to or greater than the cross-sectional width of the mesa surface. That is, in at least one plane perpendicular to the bulk semiconductor surface 26, the height of the mesa structure is equal to or greater than the cross-sectional width of the mesa surface. In view of this, the height of the mesa structure relative to the cross-sectional width of the mesa structure can provide an LED precursor with an optimised aspect ratio to increase light extraction efficiency from the LED.

[0045] According to a fourth aspect of the present application, there is provided a LED array precursor. The light emitting diode array precursor comprises a first semiconductor layer and a monolithic LED array structure. The first semiconductor layer comprises a III-nitride, the first semiconductor layer comprising a plurality of mesa structures, each mesa structure extending from a main surface of the first semiconductor layer to define a growth surface comprising a bulk semiconductor surface and a plurality of mesa surfaces. The monolithic LED array structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED array structure covers each mesa surface and the bulk semiconductor surface. The monolithic LED array structure comprises a plurality of layers, each layer comprising a III-nitride, the monolithic LED array structure comprising: an n-type semiconductor layer; an active layer provided on the n-type semiconductor layer, the active layer being configured to generate light; and a p-type semiconductor layer provided on the active layer. A potential barrier is provided between mesa portions of the p-type semiconductor layer covering each mesa surface and a bulk portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding each mesa portion of the p-type semiconductor layer covering a mesa surface.

[0046] The LED precursor array according to the fourth aspect provides a LED precursor array that can be formed by the method according to the second aspect. Hence, the LED precursor array according to the fourth aspect can comprise a plurality of LEDs according to the third aspect. Hence, the LED precursor array can comprise features corresponding to all important features of the first aspect described above. BRIEF DESCRIPTION OF DRAWINGS

[0047] The present disclosure will now be described with respect to the following non-limiting drawings, when taken in conjunction with the following detailed description. Additional advantages and novel features of this disclosure can be set forth in part in the description that follows, and can be taken in conjunction with the accompanying drawings, in which:

[0048] - Figure 1 A schematic representation of an intermediate step of a method according to an embodiment of the present disclosure is shown, wherein a first semiconductor layer comprising mesa structures is provided;

[0049] - Figure 2 A schematic representation of an intermediate step of a method according to an embodiment of the present disclosure is shown, wherein a first semiconductor layer with an overgrowth of a second semiconductor layer is provided;

[0050] - Figure 3 A schematic representation of an intermediate step of a method according to an embodiment of the present disclosure is shown, wherein a monolithic LED structure is provided on the first semiconductor layer;

[0051] - Figure 4 A schematic representation of an intermediate step of a method according to an embodiment of the present disclosure is shown, wherein a mask layer is provided on the intermediate structure of Figure 3 ;

[0052] - Figure 5A schematic diagram of an LED precursor is shown, in accordance with one embodiment of the disclosure;

[0053] - Figure 6 A schematic diagram of an intermediate step of a method is shown, in accordance with one embodiment of the disclosure, in which a monolithic LED structure is provided on a first semiconductor layer;

[0054] - Figure 7 A schematic diagram of an LED precursor is shown, in accordance with another embodiment of the disclosure;

[0055] - Figure 8 a and 8b show SEM images of a mesa structure of a first semiconductor layer;

[0056] - Figure 8 c and 8d show SEM images of an overgrown monolithic LED array structure;

[0057] - Figure 9 An SEM image of an overgrown monolithic LED array structure having a hexagonal arrangement pattern is shown;

[0058] - Figure 10 A cross-sectional SEM image of a first semiconductor layer including a plurality of mesa structures and an overgrown second semiconductor layer is shown;

[0059] - Figure 11 Another cross-sectional SEM image of a first semiconductor layer including a plurality of mesa structures and an overgrown second semiconductor layer is shown. DETAILED DESCRIPTION

[0060] According to embodiments of the disclosure, a method of forming an LED 1 is provided. Reference will now be made to Figures 1 to 4 A method of forming an LED is described.

[0061] As Figure 1 indicated, a substrate 10 can be provided for forming an LED thereon. The substrate can be any substrate 10 suitable for forming a Group III nitride electronic device. For example, the substrate 10 can be a sapphire substrate or a silicon substrate. The substrate can include one or more buffer layers configured to provide a substrate surface suitable for forming a Group III nitride layer.

[0062] A first semiconductor layer 20 can be formed on the substrate surface. The first semiconductor layer 20 includes a Group III nitride. In some embodiments, the first semiconductor layer can be n-type doped. In other embodiments, the semiconductor layer can not be intentionally doped.

[0063] For example, in Figure 1In embodiments, the first semiconductor layer 20 comprises GaN. The GaN can be n-type doped using a suitable dopant, such as Si or Ge. The first semiconductor layer 20 can be deposited using any suitable process for fabricating thin films of III-nitride, such as Metal Organic Chemical Vapour Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The first semiconductor layer 20 has a first surface, which is the surface of the first semiconductor layer 20 on the side of the first semiconductor layer 20 opposite the substrate 10. The first surface is used to form at least part of a growth surface 22 on which layers of the LED structure are deposited.

[0064] In some embodiments, the first semiconductor layer 20 can be formed on a substrate whose (0001) crystal plane is arranged parallel to the surface of the substrate.

[0065] The growth surface 22 of the first semiconductor layer 20 can then be shaped using a selective removal process. In view of this, portions of the first semiconductor layer 20 are selectively removed to form a mesa structure 24 such that the growth surface 22 of the first semiconductor layer 20 comprises a mesa surface 25 and a bulk semiconductor layer surface 26.

[0066] For example, in Figure 1 The growth surface 22 can be shaped using an etching process. In the etching process, a mask layer (not shown) defining the mesa can be deposited on the first surface of the first semiconductor layer 20. The mask layer defining the mesa is configured to mask portions of the first semiconductor layer 20 that are intended to form the mesa surface 25 of the growth surface. The unmasked portions of the first semiconductor layer 20 can then be selectively removed using an etchant. The etchant can etch away portions of the first semiconductor layer 20 to expose the bulk semiconductor layer surface 26 of the first semiconductor layer 20. That is, the etchant can not etch completely through the thickness of the first semiconductor layer 20 to expose the underlying substrate 10. The mask layer defining the mesa can then be removed from the first semiconductor layer. By following the above process, the first semiconductor layer 20 can be shaped to provide a mesa structure 24 that is monolithically arranged on the bulk semiconductor layer surface 26, for example as shown in Figure 1

[0067] ​In some embodiments, the mesa surface portion of the first semiconductor layer 20 may not be selectively removed. Thus, after the selective removal step, the alignment of the mesa surface 25 relative to the substrate 10 may not change. Given this, the mesa surface 25 may be parallel to the surface of the substrate. In some embodiments, the first semiconductor layer is etched such that the bulk semiconductor surface 26 is also substantially parallel to the substrate 10. Thus, the mesa surface 25 and the bulk semiconductor surface 26 of the first semiconductor layer 20 may both be surfaces that are substantially parallel to each other. In some embodiments, the mesa surface 25 and the bulk semiconductor surface 26 may be aligned with the (0001) plane of the Group III nitride forming the first semiconductor layer 20.

[0068] exist Figure 1 , mesa structure 24 is shown as having sidewalls that are substantially perpendicular to bulk semiconductor surface 26 and mesa surface 25. In other embodiments, mesa structure 24 can be formed with sloped sidewalls. For example, different etchants can be used to control the shape of the sidewalls formed during the selective removal process.

[0069] Next, a monolithic LED structure can be formed on growth surface 22 of first semiconductor layer 20. The monolithic LED structure covers mesa surface 25 and bulk semiconductor layer surface 26. The monolithic LED structure includes multiple layers, each of which includes a Group III nitride. In some embodiments, the Group III nitride includes one or more of AlInGaN, AlGaN, InGaN, and GaN.

[0070] The monolithic LED structure refers to providing an LED structure formed as a single piece, that is, the monolithic LED structure is formed as a single piece on the first semiconductor layer.

[0071] In one embodiment of the present invention, Figure 2 As shown, the second semiconductor layer 30 can be deposited on the first semiconductor layer 20. The second semiconductor layer 30 is formed on the first semiconductor layer 20 on the side of the first semiconductor layer 20 opposite to the substrate 10. In this regard, the second semiconductor layer 30 forms the first layer of the multilayer of the monolithic LED structure. For reference, Figure 2 The dashed line schematically shows Figure 1 The profile of the growth surface 22.

[0072] The second semiconductor layer 30 can be formed on the growth surface 22 by any growth method suitable for growing group III nitrides. Figure 2In an embodiment, second semiconductor layer 30 is monolithically formed above growth surface 22 (i.e., an overgrowth method). Second semiconductor layer 30 can be formed as a continuous layer that substantially covers the entire growth surface 22. Second semiconductor layer 30 can be deposited using any suitable process for making Group III nitride thin films, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0073] The second semiconductor layer 30 includes a group III nitride. Figure 2 In the embodiment of the present invention, the second semiconductor layer 30 includes GaN. The second semiconductor layer may be n-type doped. GaN may be n-type doped using a suitable dopant, such as Si or Ge. Figure 2 In the embodiment of FIG. 3 , the second semiconductor layer 30 is not intentionally doped. Given this, the second semiconductor layer 30 can be a (substantially) undoped layer. By substantially undoped, it can be understood that the Group III nitride layer does not include any appreciable amount of doping elements, while understanding that some impurities may be present due to the manufacturing process. Given this, a substantially undoped Group III nitride may not be intentionally doped. By forming the second semiconductor layer 30 from an undoped semiconductor, the flow of charge carriers through the LED can be more effectively confined to the mesa structures 24.

[0074] By growing the second semiconductor layer 30 on the first semiconductor layer 20, the second semiconductor layer can have a crystal structure corresponding to the crystal structure of the first semiconductor layer 20. For example, when the mesa surface 25 of the first semiconductor layer 20 is aligned with the (0001) plane of the group III nitride, the second semiconductor layer 30 can also be grown with a similar crystal orientation.

[0075] exist Figure 2 In an embodiment of the present invention, the second semiconductor layer 30 is formed on the growth surface 22 to provide an inclined sidewall portion 33 extending between a first portion 34 of the second semiconductor layer on the mesa surface 25 of the first semiconductor layer and a second portion 36 of the second semiconductor layer on the bulk semiconductor surface 26 of the first semiconductor layer. Thus, the second semiconductor layer 30 can be overgrown on the mesa structure 24 of the first semiconductor layer 20 to provide a Group III nitride semiconductor layer that includes the second semiconductor layer mesa surface 35 and is surrounded by the inclined sidewall portion 33. In view of this, the second semiconductor layer 30 can be overgrown on the mesa structure 24 to form a pillar having a regular trapezoidal cross-section perpendicular to the substrate, wherein the second semiconductor layer mesa surface 35 forms a substantially flat upper surface of the trapezoidal cross-section portion. The second semiconductor layer mesa surface 35 can be aligned with a plane parallel to the substrate surface on which the layer is formed.

[0076] A“regular trapezoidal cross-section” refers to a pillar that is narrower at the top than at the bottom and that has a substantially flat upper surface with linearly sloped sides. This can result in a frustoconical shape, or more likely a frustropyramidal shape with 3 or more sides, typically 6 sides. The description of a“regular trapezoidal cross-section” refers to the first portion 34 of the second semiconductor layer that grows above the mesa structure 24. The trapezoidal cross-section is a discontinuous portion of the second semiconductor layer that extends above a continuous planar portion of the second semiconductor layer. The tapered sides of the trapezoidal cross-section of the pillar are referred to herein as the sidewall portions 33.

[0077] In some embodiments, the sidewall portions 33 of the pillars have a substantially uniform angle (a) to a plane parallel to the first semiconductor layer. That is, there is no significant variation in the angle between the side of the pillar and a plane parallel to the first semiconductor. For example, the angle a is between 50° and 70°, more preferably between 58° and 64°, and most preferably approximately 62°.

[0078] Accordingly, in some embodiments, the sidewall portions 33 of the pillars can be tilted with respect to the (0001) plane of the crystal structure of the first semiconductor layer 20. The tilted sidewalls can generally follow the or c-plane surface (semipolar surface), similar to the structure produced by SAG.

[0079] In some embodiments, the pillars in the second semiconductor layer 30 are truncated hexagonal pyramids.

[0080] As Figure 2 illustrated, an active layer 40 can then be formed on the second semiconductor layer 30. The active layer 40 is configured to produce light of a first wavelength as part of a monolithic LED structure.

[0081] In Figure 2 embodiments, the active layer 40 can include one or more quantum well layers (not shown). In view of this, the active layer 40 can be a multiple quantum well layer. The quantum well layers within the active layer 40 can include Group III nitride semiconductors, preferably Group III nitride alloys including In. For example, in Figure 2 embodiments, the active layer 40 can include alternating layers of GaN and InzGai-zN, where 0 < Z < 1. The thickness and In content of the quantum well layers can be controlled to control the wavelength of light produced by the active layer. The active layer 40 can be formed as a continuous layer covering a majority (e.g., all) of the exposed surface of the second semiconductor layer 30. The active layer 40 can be deposited using any suitable process for fabricating Group III nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0082] Deposition of the active layer 40 on the second semiconductor layer 30 can occur with a relatively high deposition rate on the first portion 35 of the second semiconductor layer on the mesa surface 25, and a significantly lower deposition rate on the inclined sidewalls. This effect is caused by different facet alignments of the various surfaces, resulting in the active layer 40 being thicker above the mesa surface 25 than on the inclined sidewalls 35. This effect is described in more detail in GB1811109.6.

[0083] Further layers of the monolithic LED structure can then be deposited on the active layer 40 on the side of the active layer 40 opposite the second semiconductor layer 30. Figure 3 An example of the formation of the multiple layers of the monolithic LED structure is shown, which have been formed on the growth surface 22 of the first semiconductor layer 20. The multiple layers of the monolithic LED structure can each be formed as a continuous layer.

[0084] In embodiments of the Figure 3 second semiconductor layer 30 comprising undoped GaN is formed on the first semiconductor layer 20. Figure 3 The first semiconductor layer in comprises n-type doped GaN. As described above, the active layer 40 is disposed on the second semiconductor layer 30.

[0085] In embodiments of the Figure 3 electronic blocking layer 50 is disposed on the active layer 40. The electronic blocking layer 50 is disposed on a side of the active layer 40 opposite the side of the active layer on which the second semiconductor layer 30 is disposed. The electronic blocking layer 50 comprises a III-nitride. The electronic blocking layer 50 can be formed as a continuous layer covering a majority (e.g. all) of the exposed surface of the active layer 40. The electronic blocking layer 50 is configured to reduce the flow of electrons from the active layer 30 into the p-type semiconductor layer 60 of the monolithic LED structure. For example, in embodiments of the Figure 3 electronic blocking layer 50 can comprise Al x Ga 1-x N. Further details of suitable electronic blocking layers 50 can be found in Schubert, E. (2006). Light-Emitting Diodes. Cambridge: Cambridge University Press.

[0086] As Figure 3As shown, a p-type semiconductor layer 60 is disposed over the active layer 40. The p-type semiconductor layer 60 is disposed on a side of the electron blocking layer 50 opposite the side of the electron blocking layer 50 on which the active layer 40 is disposed. The p-type semiconductor layer 60 comprises a Group III nitride. The p-type semiconductor layer is doped with a suitable electron acceptor, such as Mg. The p-type semiconductor layer 60 can be formed as a continuous layer covering most (e.g., all) of the exposed surface of the active layer 40 (or the electron blocking layer 50, if present).

[0087] Accordingly, the p-type semiconductor layer 60 can be provided with a first portion 64 that is substantially aligned with the mesa structure 24. That is, a surface 65 of the aligned first portion of the p-type semiconductor layer is disposed over the mesa surface 25 (i.e., the centers of the respective surfaces are aligned). The p-type semiconductor layer 60 also includes a second portion that covers at least a portion of the bulk semiconductor surface 26 that is remote from the mesa surface 24. In view of this, it is generally considered that a monolithic LED structure can have a first portion disposed over the mesa surface 25 and a second portion that covers at least a portion of the bulk semiconductor surface 26 that is remote from the mesa surface 24.

[0088] To improve charge carrier confinement in the active layer over the mesa surface 25 of the LED, a method according to the present disclosure forms a barrier between a first portion of the monolithic LED structure that covers the mesa surface 25 and a second portion of the monolithic LED structure that covers the bulk semiconductor surface 26, where the barrier surrounds the first portion of the p-type semiconductor layer that covers the mesa surface 25. That is, a method according to the present disclosure provides a barrier between the upper contact surface of a substantially planar surface of a regular trapezoidal shape and a layer formed over the bulk semiconductor surface 26.

[0089] Figure 3 And 4 An embodiment of a method for forming such a barrier is schematically illustrated. Figure 4 And 5 Embodiments of the method of the present disclosure illustrate further processing steps subsequent to the fabrication of a device as shown in Figure 3

[0090] In Figure 4 , a mask layer 70 is formed on a surface of the p-type semiconductor layer 60 on a side of the p-type semiconductor layer 60 opposite the electron blocking layer 50.

[0091] ​A mask layer 70 can be selectively disposed on the p-type semiconductor layer 60. The mask layer 70 can be disposed to define one or more apertures. The apertures can be configured to expose regions of the p-type semiconductor layer 60 to be selectively removed. For example, the apertures can define a third portion 61 of the p-type semiconductor layer that encircles the first portion 64 of the p-type semiconductor layer that covers the mesa structure. The third portion 61 of the p-type semiconductor layer can then be selectively removed, for example by etching, to provide a potential barrier. For example, in embodiments where the p-type semiconductor layer 60 is a III-Nitride layer, the third portion 61 of the p-type semiconductor layer can be selectively removed by etching the III-Nitride layer to expose the underlying layer (e.g., the electron blocking layer 50 in embodiments of the present application). Figure 4 In embodiments where the p-type semiconductor layer 60 is a III-Nitride layer, the third portion 61 of the p-type semiconductor layer can be a slanted sidewall portion of the p-type semiconductor layer 60.

[0092] In embodiments where the p-type semiconductor layer 60 is a III-Nitride layer, the third portion 61 of the p-type semiconductor layer can be a slanted sidewall portion of the p-type semiconductor layer 60. Figure 4 In embodiments where the p-type semiconductor layer 60 is a III-Nitride layer, the third portion 61 of the p-type semiconductor layer can be a slanted sidewall portion of the p-type semiconductor layer 60. 5 In embodiments where the p-type semiconductor layer 60 is a III-Nitride layer, the third portion 61 of the p-type semiconductor layer can be a slanted sidewall portion of the p-type semiconductor layer 60.

[0093] Figure 5 A schematic diagram of the resulting LED precursor after forming the potential barrier by selectively removing the third portion 61 of the p-type semiconductor layer is shown. As shown in FIG. 6, the p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layer (e.g., the electron blocking layer 50 in embodiments of the present application). In view of this, the selective removal step forms a channel in the single piece LED structure that encircles the first portion 64 of the p-type semiconductor layer. Thus, a potential barrier is formed in the p-type semiconductor layer 60 between the first portion 65 of the p-type semiconductor layer that covers the mesa surface 25 and the second portion 66 of the p-type semiconductor layer that covers the body semiconductor surface 26. The potential barrier is provided to increase the confinement of charge carriers in the active layer mesa structure region of the device during operation. Figure 5 Figure 5

[0094] ​​In other embodiments of the method according to the present disclosure, the depth of the channels selectively removed can be varied. For example, in some embodiments, the channels can extend only partially through the thickness of the third portion 61 of the p-type semiconductor layer. By reducing the thickness of the third portion 61 of the p-type semiconductor layer, in combination with the variation in deposition rate on the sidewall surface described above for monolithic LED structures, a significant electrical resistance can exist between the first and second portions 65, 66 of the p-type semiconductor layer, effectively providing a potential barrier. In other embodiments, the channels can extend at least partially through the thickness of one or more of the other layers of the monolithic LED structure.

[0095] Figure 6 and 7 Another method of forming such a potential barrier is schematically illustrated.

[0096] Figure 6 A structure including a first semiconductor layer 20, a second semiconductor layer 30, and an active 40 is shown. Figure 6 The structure of Figures 1-3 may be formed by the method steps discussed above with respect to

[0097] After forming the structure of Figure 6 , a p-type semiconductor layer 60 is formed on the active layer 40, as shown in Figure 7 . The p-type semiconductor layer 60 is formed on a side of the active layer 40 opposite the second semiconductor layer 30. In some embodiments, an electron blocking layer 50 can be provided between the p-type semiconductor layer 60 and the active layer 40, as shown in Figure 3 .

[0098] In embodiments in which Figure 7 , the p-type semiconductor layer 60 includes a Group III nitride including Al. The p-type semiconductor layer 60 can be formed such that the concentration of Al included in a sidewall portion 63 of the p-type semiconductor layer is higher than the concentration of Al included in a first portion 64 of the p-type semiconductor layer covering the mesa surface 25, such that a potential barrier is provided between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 63 and the first portion 64 of the p-type semiconductor layer can be such that the variation in bandgap between the first portion and the sidewall portion at room temperature is greater than kT eV (i.e., greater than about 0.26 eV).

[0099] For example, the sidewall portion 63 of the p-type semiconductor layer can include a p-type Al x Ga 1-x N, where 2 < x < 50%, and the first portion 64 of the p-type semiconductor layer can include a p-type Al y Ga 1-y N, where 1 < y < 15%.

[0100] As discussed above, the sloped sidewalls of the second semiconductor layer 30 result in a variation in the deposition rate of the Ill-nitride, depending on whether the growth surface is a sloped sidewall or substantially parallel to the substrate. For the growth of the p-type semiconductor layer 60, the difference in growth rate also affects the Al incorporation into the p-type semiconductor layer 60. Thus, the same deposition process can be used to form a sloped sidewall portion 63 having a higher Al content than the first portion 64 of the p-type semiconductor layer. In view of this, the desired barrier for confining the current in the first portion 64 of the p-type semiconductor layer of the monolithic LED structure can be formed without any further patterning steps.

[0101] As discussed above, an LED precursor can be provided having multiple layers.

[0102] The thickness of the first semiconductor layer 20 can be between 100 nm and 8 pm and preferably between 3 pm and 5 pm. Portions of the first semiconductor layer 20 can be selectively removed to define a mesa structure having a height perpendicular to the bulk semiconductor surface 26 of at least: 100 nm, 200 nm, 300 nm, or 500 nm. The height of the mesa structure can be no greater than 5 pm. In some embodiments, the height of the mesa structure can be between 1 pm and 3 pm.

[0103] The thickness of the second semiconductor layer 30 on the mesa surface 24 of the first semiconductor layer 20 can be at least 5 nm. The thickness of the second semiconductor layer 30 can be no greater than 4 pm.

[0104] The thickness of the substantially planar first portion 34 of the active layer 30 can be between 30 nm and 150 nm, and in some embodiments between 40 nm and 60 nm.

[0105] The thickness of the substantially planar first portion 44 of the electron blocking layer 50 can be between 5 nm and 50 nm, and in some embodiments between 20 nm and 40 nm. For example, in embodiments where the thickness of the electron blocking layer is 33 nm, the thickness of the electron blocking layer 50 in the sidewall region can be at least 0.5 nm to about 25 nm due to the variation in deposition rate as discussed above. Figure 3 The thickness of the substantially planar first portion 44 of the electron blocking layer 50 can be between 5 nm and 50 nm, and in some embodiments between 20 nm and 40 nm. For example, in embodiments where the thickness of the electron blocking layer is 33 nm, the thickness of the electron blocking layer 50 in the sidewall region can be at least 0.5 nm to about 25 nm due to the variation in deposition rate as discussed above. Figure 3 In embodiments where the thickness of the electron blocking layer 50 is about 7 nm, the thickness of the electron blocking layer 50 in the sidewall region can be about 0.5 nm to about 25 nm.

[0106] The thickness of the substantially planar first portion 64 of the p-type semiconductor layer 60 can be at least 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. The thickness of the substantially planar first portion 64 of the p-type semiconductor layer 60 can be no greater than: 300 nm, 250 nm, or 200 nm. For example, in embodiments where the thickness of the p-type semiconductor layer is 200 nm, the thickness of the p-type semiconductor layer 60 in the sidewall region can be at least 0.5 nm to about 25 nm due to the variation in deposition rate as discussed above. Figure 3In embodiments, the thickness of the substantially planar first portion 64 of the p-type semiconductor layer 60 can be approximately 100 nm.

[0107] In some embodiments, the height of the mesa structure (perpendicular to the bulk semiconductor surface 26) is equal to or greater than the cross-sectional width of the mesa surface. That is, in at least one plane perpendicular to the bulk semiconductor surface 26, the height of the mesa structure is equal to or greater than the cross-sectional width of the mesa surface. In view of this, the height of the mesa structure relative to the cross-sectional width of the mesa structure can provide an LED precursor with an optimized aspect ratio to increase light extraction efficiency from the LED.

[0108] For example, in some embodiments, the mesa surface 25 can be provided with a surface area of no greater than 100 pm x 100 pm. In particular, the mesa surface can have a surface area of no greater than 4 pm x 4 pm. Thus, the height of the mesa structure can be at least 4 pm.

[0109] After the LED precursor is formed as described above, the LED precursor can undergo further processing steps to provide an LED. For example, in some embodiments, the substrate 10 can be removed to expose the light emitting surface 21 of the first semiconductor layer 20.

[0110] Preferably, light extraction features such as lenses (i.e., domed surfaces) can also be provided on the light emitting surface. For example, lenses (or other domed structures) can be formed on the light emitting surface 21 to increase light extraction efficiency from the LED. In some embodiments, the lenses are aligned with each LED on the light emitting surface 21. Each lens can cover a surface area of the light emitting surface 21 corresponding to a surface area of the base (i.e., trapezoidal shaped base) of the monolithic LED structure. In some embodiments, the lenses (domed surfaces) can be formed from the light emitting surface 21 by selectively removing the first semiconductor layer 20 from the light emitting surface 21. By providing the light emitting surface 21 of the LED with light extraction features, light extraction efficiency of the LED can be improved.

[0111] According to embodiments of the present application, a light emitting diode precursor 1 is provided. The LED precursor includes a first semiconductor layer 20, a second semiconductor layer 30, an active layer 40, and a p-type semiconductor layer 60.

[0112] The first semiconductor layer 20 includes a Ill-nitride. As Figure 3As shown, a first semiconductor layer 20 can be disposed on a substrate 10. The substrate 10 can comprise sapphire, silicon, or SiC. The substrate 10 can include one or more buffer layers configured to provide a substrate surface suitable for forming a Group III nitride layer. Of course, in some embodiments, the LED precursor 1 can be fabricated according to the above-described method, after which the substrate 10 can be removed. In some embodiments, the LED precursor 1 can be bonded to a backplane electronic substrate (not shown). The backplane electronic substrate can include circuitry and contacts configured to control and contact the LED precursor 1. In some embodiments, the backplane electronic substrate can be bonded to the p-type semiconductor layer 60.

[0113] According to Figure 5 and 7 As shown, the first semiconductor layer 20 includes mesa structures 24 extending from a major surface of the first semiconductor layer 20 to define a growth surface 22 that includes a bulk semiconductor surface 26 and a mesa surface 25. A major surface is understood to mean a surface of the first semiconductor layer 20 that forms a substantial portion of the total surface area of the first semiconductor layer 20. For example, in Figure 5 and 7 the major surface forming the growth surface 22 is a surface of the first semiconductor layer 20 disposed on an opposite side of the first semiconductor layer 20 from the substrate 10.

[0114] The mesa structures 24 can be considered as pillars extending from the bulk semiconductor surface 26 of the first semiconductor layer 20. The mesa structures 24 are monolithically formed with the bulk semiconductor surface 26 of the first semiconductor layer 20, for example as described in the above-described method. The mesa structures 24 can be pillars having any cross-sectional shape (i.e., the shape of the pillars when the first semiconductor layer 20 is viewed in plan view). For example, the mesa structures 24 can be pillars having a regular polygonal cross-section. In particular, the mesa structures 24 can be elliptical (or circular) pillars, rectangular pillars, or hexagonal pillars. Figure 8 a shows one example of a plurality of mesa structures 24 of the first semiconductor layer 20, wherein each mesa structure 24 is a circular cylinder.

[0115] In Figure 5 and 7 the embodiments shown, the mesa structures 24 are shown as having sidewalls that are substantially perpendicular to the bulk semiconductor surface 26 and the mesa surface 25. In other embodiments, the mesa structures 24 can be formed with sloped sidewalls.

[0116] As shown in Figure 5 and 7 a monolithic LED structure is disposed on the growth surface 22 of the first semiconductor layer 20 such that the monolithic LED structure covers the mesa surface 25 and the bulk semiconductor surface 26.

[0117] As discussed above, the monolithic LED structure includes multiple layers. Each layer is formed of a Group III nitride. The monolithic LED structure includes a second semiconductor layer 30, an active layer 40, and a p-type semiconductor layer 60. In some embodiments, the monolithic LED structure can also include an electron blocking layer 50.

[0118] As discussed above, the second semiconductor layer 30 is disposed on the growth surface 22 to provide an inclined sidewall 33 extending between a first portion 34 of the second semiconductor layer on the mesa surface 25 of the first semiconductor layer and a second portion 36 of the second semiconductor layer on the bulk semiconductor surface 26 of the first semiconductor layer 20. Thus, the second semiconductor layer 30 is overgrown on the mesa structure 24 of the first semiconductor layer 20 to provide a Group III nitride semiconductor layer that includes the first portion 34 and is surrounded by the inclined sidewall 33. In view of this, the second semiconductor layer 30 can be overgrown on the mesa structure 24 to form a pillar having a regular trapezoidal cross-section perpendicular to the substrate, with the surface 35 of the first portion of the second semiconductor layer being substantially planar. The substantially planar surface 35 of the first portion can be in a plane parallel to the surface of the substrate on which the layers are formed.

[0119] The active layer 40, the electron blocking layer 50 (if present), and the p-type semiconductor layer 60 can be disposed on the second semiconductor layer 30 according to the methods described above to form a monolithic LED structure. At least in Figure 5 and 7 Examples of such monolithic LED structures can also be seen in

[0120] To improve charge carrier confinement in the active layer above the mesa surface 25 of the LED, the LED precursor according to the present disclosure includes a potential barrier between the first portion of the monolithic LED structure covering the mesa surface 25 and the second portion of the monolithic LED structure covering the bulk semiconductor surface 26, with the potential barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface 25. That is, the method according to the present disclosure provides a potential barrier between the layers formed on the substantially planar surface of regular trapezoidal shape and the bulk semiconductor surface 26.

[0121] As shown in Figure 5 and 7 the monolithic LED structure is formed such that a potential barrier is provided between the first portion 64 of the p-type semiconductor layer covering the mesa surface and the second portion 66 of the p-type semiconductor layer covering the bulk semiconductor surface. The potential barrier surrounds the first portion 64 of the p-type semiconductor layer covering the mesa surface.

[0122] In Figure 5In the embodiment of FIG. 5 , the potential barrier may be formed by selectively removing the third portion 61 of the p-type semiconductor layer, the third portion 61 of the p-type semiconductor layer surrounding the first portion 64 of the p-type semiconductor layer covering the mesa. Figure 5 As shown, the p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layers ( Figure 5 The electron blocking layer 50 in the embodiment of FIG.

[0123] exist Figure 7 In an embodiment, the potential barrier can be formed by providing a p-type semiconductor layer 60 including a Group III nitride containing Al. The p-type semiconductor layer 60 is provided such that the concentration of Al contained in the sidewall portion 63 of the p-type semiconductor layer is higher than the concentration of Al contained in the first portion 64 of the p-type semiconductor layer covering the mesa surface 25, thereby providing a potential barrier between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 63 and the first portion 64 of the p-type semiconductor layer can cause a change in the band gap at room temperature to be greater than kTeV (i.e., greater than approximately 0.26 eV).

[0124] For example, the sidewall portion of the p-type semiconductor layer may include p-type Al x Ga 1-x N, where 2≤x≤50%, and the mesa surface portion 65 of the p-type semiconductor layer may include p-type Al y Ga 1-y N, where 1≤y≤15%.

[0125] As discussed above, the sloped sidewalls 33 of the second semiconductor layer 30 result in variations in the deposition rate of the Group III nitride, depending on whether the growth surface has a sloped sidewall or is substantially parallel to the substrate. With respect to the growth of the p-type semiconductor layer 60, these differences in growth rate also affect the incorporation of Al into the p-type semiconductor layer 60. Therefore, the same deposition process can be used to form the sloped sidewall portion 63 of the p-type semiconductor layer having a higher Al content than the first portion 65 of the p-type semiconductor layer. Consequently, the desired barrier for confining current in the first portion of the monolithic LED structure can be formed without any further patterning steps.

[0126] Therefore, an LED precursor according to an embodiment of the present disclosure can be provided.

[0127] According to another embodiment of the present disclosure, a method of forming an LED array precursor may be provided.

[0128] According to the method, a first semiconductor layer 20 comprising a Group III nitride is formed on a substrate 10. The first semiconductor layer has a growth surface 22 on a side of the first semiconductor layer 20 opposite the substrate 10. In view of this, the first semiconductor layer 20 can be formed in substantially the same manner as the embodiments of the method described above. Figures 1-5 and Figures 6-7 The method of forming the first semiconductor layer 20 can be substantially the same as the method of forming the first semiconductor layer 20 described above.

[0129] Next, portions of the first semiconductor layer 20 are selectively removed to form a plurality of mesa structures 24 such that the growth surface 22 of the first semiconductor layer 20 comprises a plurality of mesa surfaces 25 and one bulk semiconductor layer surface 26. In view of this, the steps of the method are substantially the same as the corresponding steps of the method of forming the LED precursor, except for the formation of the plurality of mesa structures 24.

[0130] The plurality of mesa structures 24 can be regularly spaced apart on the substrate growth surface 22 of the first semiconductor layer 20. For example, the mesa structures can be provided in a hexagonally close-packed array or a square-packed array of the mesa structures 24. Figure 8 a shows a Scanning Electron Micrograph (SEM) image of the first semiconductor layer comprising the plurality of mesa structures 24. As shown in Figure 8 a, the plurality of mesa structures 24 are provided as part of the first semiconductor layer 20. Each mesa structure 24 is a pillar having a cylindrical shape (circular cross-section). Figure 8 b shows a magnified view of one of the mesa structures 24 shown in Figure 8 a.

[0131] A monolithic LED array structure is then formed on the growth surface of the first semiconductor layer 20 such that a first portion of the monolithic LED array structure covers a respective mesa surface 25 and a second portion of the monolithic LED array structure covers the bulk semiconductor surface 26. The monolithic LED array structure comprises a plurality of layers. Each layer is formed of a Group III nitride. The monolithic array structure comprises a second semiconductor layer 30, an active layer 40 disposed on the second semiconductor layer 30, and a p-type semiconductor layer 60 disposed on the active layer 40. In some embodiments, the monolithic LED structure can further comprise an electron blocking layer 50 disposed between the active layer 40 and the second semiconductor layer 60.

[0132] By monolithic LED array structure, it is meant that the LED array structure is provided as a monolith. That is, the monolithic LED array structure is formed as a monolith on the first semiconductor layer.

[0133] The layers of the monolithic LED array structure can be provided using substantially the same processes as described above for forming the LED precursor. It will be appreciated that substantially the same processes for forming the monolithic LED array structure / monolithic LED structure can be used regardless of the number or shape of LEDs being fabricated. In view of this, the overgrowth method of the present disclosure provides a method of forming an LED array precursor in which a majority of the fabrication processes are independent of the geometry of the LED array.

[0134] Figure 8 c and 8d show SEM images of a plurality of mesa structures of a monolithic LED array structure with overgrowth. The monolithic LED array structure has been formed on a plurality of mesa structures 24 similar to that shown in Figure 8 a. In Figure 8 a-8d, the mesa structures 24 are formed in a square packed array pattern. Figure 9 show SEM images of further arrays of mesa structures of a monolithic LED array structure with overgrowth. In Figure 9 , the mesa structures 24 are arranged in a hexagonal close packed array pattern to provide the array structure shown.

[0135] In some embodiments, the second semiconductor layer 30 can comprise the same material as the first semiconductor layer 20. For example, the first and second semiconductor layers 20, 30 can comprise n-type GaN doped with Si. The second semiconductor layer 30 can therefore be formed monolithically on the growth surface 22 of the first semiconductor layer with substantially the same lattice constant. The resulting structure formed can have a substantially continuous crystal structure at the interface between the first and second semiconductor layers 20, 30. Figure 10 and 11 show SEM images of the first and second semiconductor layers 20, 30 formed according to the method of the present disclosure. In Figure 10 and 11 the SEM images, no interface between the mesa structures 24 of the first semiconductor layer 20 and the second semiconductor layer 30 is detected.

[0136] A barrier is provided between each first portion 64 of the p-type semiconductor layer covering each mesa surface 25 and the bulk portion 66 of the p-type semiconductor layer covering the bulk semiconductor surface 26. The barrier surrounds each first portion 64 of the p-type semiconductor layer covering a respective mesa surface 25.

[0137] To improve charge carrier confinement in the active layer 40 above each mesa surface 25 of each LED, a barrier is formed between a first portion of the monolithic LED structure that covers the mesa surface 25 and a second portion of the monolithic LED structure that covers the bulk semiconductor surface 26, where the barrier surrounds the first portion of the p-type semiconductor layer that covers the mesa surface 25. That is, the method according to the present disclosure provides a barrier between the upper contact surface of the substantially planar surface of regular trapezoidal shape and the layer formed above the bulk semiconductor surface 26.

[0138] The barrier of each monolithic LED structure of the LED array can be formed in a variety of ways. For example, the barrier of each monolithic LED structure can be formed substantially as described above with reference to Figure 5 or substantially as described above with reference to Figure 7 .

[0139] For embodiments of the LED array where the p-type semiconductor layer 60 is a p-type Al-containing III- nitride layer, the barrier can be formed by selectively removing a third portion 61 of the p-type semiconductor layer 60 that surrounds each first portion 64 of the p-type semiconductor layer that covers the mesa surface. Figure 5 As shown in FIG. 6, the p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layer (the electron blocking layer 50 of the embodiments described above). Figure 5 Figure 5 For embodiments of the LED array where the p-type semiconductor layer 60 is a p-type Al-containing III- nitride layer, the barrier can be formed by selectively removing a third portion 61 of the p-type semiconductor layer 60 that surrounds each first portion 64 of the p-type semiconductor layer that covers the mesa surface.

[0140] For embodiments of the LED array where the p-type semiconductor layer 60 is a p-type Al-containing III- nitride layer, the barrier can be formed by selectively removing a third portion 61 of the p-type semiconductor layer 60 that surrounds each first portion 64 of the p-type semiconductor layer that covers the mesa surface. Figure 7 As shown in FIG. 6, the p-type semiconductor layer 60 is selectively removed through the thickness of the layer to expose the underlying layer (the electron blocking layer 50 of the embodiments described above).

[0141] Thus, an LED array precursor is provided.

[0142] The LED array precursor includes a first semiconductor layer 20, a second semiconductor layer 30, an active layer 40, and a p-type semiconductor layer 60.

[0143] The first semiconductor layer 20 includes a III-nitride. As Figure 3 ​As shown, a first semiconductor layer 20 can be disposed on a substrate 10. The substrate 10 can comprise sapphire, silicon, or SiC. The substrate 10 can include one or more buffer layers configured to provide a substrate surface suitable for forming a Group III nitride layer. Of course, in some embodiments, the LED array precursor can be fabricated according to the methods described above, after which the substrate 10 can be removed. In some embodiments, the LED array precursor can be bonded to a backplane electronic substrate. The backplane electronic substrate can include circuitry and contacts configured to control and contact the LEDs of the LED array precursor. In some embodiments, the backplane electronic substrate can be bonded to the p-type semiconductor layer 60. In view of this, the first semiconductor layer can be provided substantially according to the methods outlined above.

[0144] Similar to the embodiments shown in Figure 5 and 7 the first semiconductor layer 20 includes a plurality of mesa structures 24 extending from a major surface of the first semiconductor layer to define a growth surface 22 including bulk semiconductor surfaces 26 and mesa surfaces 25. As discussed above, in Figure 8 a, an example of a first semiconductor layer including a plurality of mesa structures 24 is shown.

[0145] Similar to the embodiments shown in Figure 5 and 7 a monolithic LED array structure is disposed on the growth surface 22 of the first semiconductor layer 20 such that the monolithic LED array structure covers the mesa surfaces 25 and the bulk semiconductor surfaces 26. As discussed above, in Figure 8 c and 8d, examples of a monolithic LED array structure are shown.

[0146] As described above, the monolithic LED array structure includes a plurality of layers. Each layer is formed of a Group III nitride. The monolithic LED array structure includes a second semiconductor layer 30, an active layer 40, and a p-type semiconductor layer 60. In some embodiments, the monolithic LED array structure can also include an electron blocking layer 50. Each layer of the monolithic LED array structure can be formed as a continuous layer. In view of this, each layer of the monolithic LED array structure can be provided in a similar manner to the monolithic LED structures as discussed above. At least in Figure 5 and 7 examples of such monolithic LED structures can also be seen.

[0147] To improve charge carrier confinement in the active layer above each mesa surface 25 of the LED array precursor, each LED precursor of the array includes a barrier between a first portion of each monolithic LED structure covering the respective mesa surface 25 and a second portion of each monolithic LED structure covering the bulk semiconductor surface 26, where the barrier surrounds the first portion of the p-type semiconductor layer covering the respective mesa surface 25. That is, the method according to the present disclosure provides a barrier between the layers formed over each substantially planar surface of the regular trapezoidal shape and the bulk semiconductor surface 26.

[0148] Referring to Figure 5 and 7 each monolithic LED array structure is formed such that a barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface 64 and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface 66, the barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface 65.

[0149] Referring to Figure 5 and the above description, the barrier can be formed by selectively removing a third portion of the p-type semiconductor layer 61 surrounding the first portion of the p-type semiconductor layer covering the mesa surface 64. As Figure 5 shown, the p-type semiconductor layer 60 can be selectively removed through the thickness of the layer to expose the underlying layer (the electron blocking layer 50 of the embodiments). Figure 5

[0150] Referring to Figure 7 the barrier can be formed by providing the p-type semiconductor layer 60 to include a group III nitride containing Al. The p-type semiconductor layer 60 is provided such that the concentration of Al contained in the sidewall portion 63 of the p-type semiconductor layer 60 is higher than the concentration of Al contained in the first portion 64 of the p-type semiconductor layer covering the mesa surface 25, such that the barrier is provided in the LED array precursor between the sidewall portion 63 of the p-type semiconductor layer and the first portion 65 of the p-type semiconductor layer for each LED precursor of the LED array precursor. The difference in Al composition between the sidewall portion 63 of the p-type semiconductor layer and the first portion 64 of the p-type semiconductor layer can be such that the change in bandgap at room temperature is greater than kT eV (i.e., greater than about 0.26 eV).

[0151] For example, the sidewall portion 63 of the p-type semiconductor layer can include a p-type Al x Ga 1-x N, where 2 < x < 50%, and the mesa surface portion 65 of the p-type semiconductor layer can include a p-type Al y Ga 1-y N, where 1 < y < 15%.

[0152] ​As discussed above, the sloped sidewalls of the second semiconductor layer 30 result in a variation of the deposition rate of the Ill-nitride, which depends on whether the growth surface is a sloped sidewall or substantially parallel to the substrate. For the growth of the p-type semiconductor layer 60, the difference in growth rate also affects the Al incorporation into the p-type semiconductor layer 60. Thus, the same deposition process can be used to form the sloped sidewall portion 63 with a higher Al content than the first portion 65 of the p-type semiconductor layer. In view of this, the desired barrier for confining the current in the mesa surface portion of the monolithic LED structure can be formed without any further patterning step.

[0153] Thus, an LED precursor according to embodiments of the present disclosure can be provided.

Claims

1. A method of forming a light emitting diode (LED) precursor, comprising: (a) forming a first semiconductor layer including a Group III nitride on a substrate, the first semiconductor layer having a growth surface on a side of the first semiconductor layer opposite to the substrate; (b) selectively removing a portion of the first semiconductor layer to form a mesa structure, so that a growth surface of the first semiconductor layer includes a mesa surface and a bulk semiconductor surface; (c) forming a monolithic LED structure on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising multiple layers, each layer comprising a Group III nitride, the monolithic LED structure comprising: - a second semiconductor layer; - an active layer disposed on the second semiconductor layer, the active layer being configured to generate light; and - a p-type semiconductor layer, which is provided on the active layer, wherein a potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface; wherein the second semiconductor layer is formed on the growth surface to provide an inclined sidewall portion extending between a first portion of the second semiconductor layer on a mesa surface of the first semiconductor layer and a second portion of the second semiconductor layer on a bulk semiconductor surface of the first semiconductor layer; and The p-type semiconductor layer includes Al, and the p-type semiconductor layer is formed so that the concentration of Al contained in the inclined sidewall portion of the p-type semiconductor layer is higher than the concentration of Al contained in the first portion of the p-type semiconductor layer covering the mesa surface, so that a potential barrier is formed in the inclined sidewall portion of the p-type semiconductor layer between the first portion of the p-type semiconductor layer and the second portion of the p-type semiconductor layer.

2. The method according to claim 1, wherein The second semiconductor layer includes undoped Group III nitride.

3. The method according to claim 1, wherein The inclined sidewall portion of the p-type semiconductor layer includes a p-type Al x Ga 1- x N, where 2%≤x≤50%; and The first portion of the p-type semiconductor layer includes p-type Al y Ga 1-y N, where 1%≤y≤15%.

4. The method according to claim 1 or 2, wherein: A portion of the p-type semiconductor layer surrounding a first portion of the p-type semiconductor layer covering the mesa surface is selectively removed to expose an underlying active layer.

5. The method according to claim 4, wherein A portion of the p-type semiconductor layer surrounding a first portion of the p-type semiconductor layer covering the mesa surface is selectively removed using an anisotropic etchant.

6. The method according to any one of claims 1 to 3 and 5, wherein Selectively removing a portion of the first semiconductor layer to form the mesa structure includes: selectively forming a mask layer defining mesas on the first surface; selectively removing unmasked portions of the first semiconductor layer to expose a bulk semiconductor surface of the first semiconductor layer; and The mask layer defining the mesas is removed.

7. The method according to any one of claims 1 to 3 and 5, wherein The first semiconductor layer includes GaN.

8. The method according to claim 7, wherein: The first semiconductor layer is an n-type semiconductor.

9. The method according to any one of claims 1 to 3, 5 and 8, wherein A height of the mesa structure between the mesa surface and the bulk semiconductor surface is at least 200 nm.

10. A method of forming an LED array precursor, comprising: (a) forming a first semiconductor layer including a Group III nitride on a substrate, the first semiconductor layer having a growth surface on a side of the first semiconductor layer opposite to the substrate; (b) selectively removing a portion of the first semiconductor layer to form a plurality of mesa structures, so that a growth surface of the first semiconductor layer includes a plurality of mesa surfaces and a bulk semiconductor surface; (c) forming a monolithic LED array structure on the growth surface of the first semiconductor layer, such that the monolithic LED array structure covers the mesa surface and the bulk semiconductor surface, the monolithic LED array structure comprising multiple layers, each layer comprising a Group III nitride, the monolithic LED array structure comprising: - a second semiconductor layer; - an active layer disposed on the second semiconductor layer, the active layer being configured to generate light; and - a p-type semiconductor layer, which is arranged on the active layer; wherein a potential barrier is provided between each mesa portion of the p-type semiconductor layer covering each mesa surface and a bulk portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding each mesa portion of the p-type semiconductor layer covering the mesa surface; wherein the second semiconductor layer is formed on the growth surface to provide an inclined sidewall portion extending between each first portion of the second semiconductor layer on a mesa surface of the first semiconductor layer and a second portion of the second semiconductor layer on a bulk semiconductor surface of the first semiconductor layer; and The p-type semiconductor layer includes Al, and the p-type semiconductor layer is formed so that the concentration of Al contained in the inclined sidewall portion of the p-type semiconductor layer is higher than the concentration of Al contained in the mesa portion of the p-type semiconductor layer covering the mesa surface, so that a potential barrier is formed in the inclined sidewall portion of the p-type semiconductor layer between the mesa portion of the p-type semiconductor layer and the main body portion of the p-type semiconductor layer.

11. A light emitting diode (LED) precursor comprising: a first semiconductor layer comprising a Group III nitride, the first semiconductor layer comprising a mesa structure extending from a major surface of the first semiconductor layer to define a growth surface, the growth surface comprising a bulk semiconductor surface and a mesa surface; a monolithic LED structure disposed on a growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising multiple layers, each layer formed to include a Group III nitride, the monolithic LED structure comprising: - a second semiconductor layer; - an active layer disposed on the second semiconductor layer, the active layer being configured to generate light; and - a p-type semiconductor layer, which is arranged on the active layer; wherein a potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface; wherein the second semiconductor layer includes an inclined sidewall portion extending between a first portion of the second semiconductor layer on a mesa surface of the first semiconductor layer and a second portion of the second semiconductor layer on a bulk semiconductor surface of the first semiconductor layer; and The p-type semiconductor layer comprises Al, wherein: The inclined sidewall portion of the p-type semiconductor layer includes a higher concentration of Al than the first portion of the p-type semiconductor layer covering the mesa surface, so that a potential barrier is formed in the inclined sidewall portion of the p-type semiconductor layer between the first portion of the p-type semiconductor layer and the second portion of the p-type semiconductor layer.

12. The light emitting diode (LED) precursor according to claim 11, wherein A portion of the p-type semiconductor layer surrounding a first portion of the p-type semiconductor layer covering the mesa structure is selectively removed to expose the active layer therebelow.

13. The light emitting diode (LED) precursor according to claim 11 or 12, wherein A height of the mesa structure between the mesa surface and the bulk semiconductor surface is at least 200 nm.

14. The light emitting diode (LED) precursor according to claim 11 or 12, wherein The surface area of ​​the mesa surface is no greater than 100 μm×100 μm.

15. The light emitting diode (LED) precursor according to claim 11 or 12, wherein The height of the mesa structure between the mesa surface and the bulk semiconductor surface is at least equal to the cross-sectional width of the mesa surface of the mesa structure.

16. A light emitting diode array precursor, comprising: a first semiconductor layer comprising a Group III nitride, the first semiconductor layer comprising a plurality of mesa structures, each mesa structure extending from a major surface of the first semiconductor layer to define a growth surface comprising a bulk semiconductor surface and the plurality of mesa surfaces; a monolithic LED array structure disposed on the growth surface of the first semiconductor layer such that the monolithic LED array structure covers each of the mesa surfaces and the bulk semiconductor surface, the monolithic LED array structure comprising multiple layers, each layer comprising a Group III nitride, the monolithic LED array structure comprising: - a second semiconductor layer; - an active layer disposed on the second semiconductor layer, the active layer being configured to generate light; and - a p-type semiconductor layer, which is arranged on the active layer; wherein a potential barrier is provided between each mesa portion of the p-type semiconductor layer covering each mesa surface and a bulk portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding each mesa portion of the p-type semiconductor layer covering the mesa surface; wherein the second semiconductor layer is formed on the growth surface to provide an inclined sidewall portion extending between each first portion of the second semiconductor layer on a mesa surface of the first semiconductor layer and a second portion of the second semiconductor layer on a bulk semiconductor surface of the first semiconductor layer; and The p-type semiconductor layer includes Al, and the p-type semiconductor layer is formed so that the concentration of Al contained in the inclined sidewall portion of the p-type semiconductor layer is higher than the concentration of Al contained in the mesa portion of the p-type semiconductor layer covering the mesa surface, so that a potential barrier is formed in the inclined sidewall portion of the p-type semiconductor layer between the mesa portion of the p-type semiconductor layer and the main body portion of the p-type semiconductor layer.

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