Bipolar transistor and manufacturing method

Abstract

A bipolar transistor and a manufacturing method are disclosed. The bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion overlying and contacting a region of the first doped portion. The collector region has a doping profile having a peak at a first portion and decreasing from the peak to a second portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French patent application No. 2010686, filed on October 19, 2020, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] Embodiments and examples of the present invention relate to electronic components, in particular bipolar transistors and methods of manufacturing the same, such as heterojunction bipolar transistors (HBT transistors) having a base comprising silicon and germanium, and more particularly to doping of the collectors of these bipolar transistors. Background Art

[0004] A bipolar transistor is a semiconductor-based electronic device whose operating principle is based on two PN junctions, one in the forward direction and the other in the reverse direction.

[0005] The doping of the collector in bipolar transistors, in particular heterojunction bipolar transistors, is important since it influences the values ​​defining the transistor's performance, in particular its operating frequency, its maximum oscillation frequency and its primary capacitance.

[0006] Bipolar transistors have been the subject of numerous publications, notably: U.S. Patent Application Publication No. 2020 / 0111890 (French Patent Application No. 3087047); U.S. Patent No. 10,224,423; Heinemann et al., “SiGe HBT with fx / fmax of 505 GHz / 720 GHz,” 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016; and Rücker et al., “High-performance SiGe HBTs for next generation BiCMOS technology,” Semiconductor Science and Technology 33.11(2018):114003 (all incorporated herein by reference).

[0007] In these publications, the doping of the collector region of the bipolar transistor is performed, for example, by in-situ doping during collector epitaxy or also by implanting dopants after collector epitaxy.

[0008] During epitaxy, method constraints such as duration, cost, dopant type, and selectivity of in-situ doping are difficult to meet.

[0009] Furthermore, it is complicated to co-integrate a high-speed bipolar transistor and a bipolar transistor with a high collector-emitter breakdown voltage in the same integrated circuit, which requires different doping of their respective collectors, since in-situ doping subsequently involves performing different epitaxies.

[0010] Furthermore, implanting the collector after epitaxy requires the use of a mask.

[0011] Therefore, there is a need for a collector doping technique that has an industrially acceptable cost and complexity and that also optionally enables easy co-integration of high speed transistors and high breakdown voltage transistors in the same integrated circuit. Summary of the Invention

[0012] According to one embodiment and example, it is proposed to use diffusion of dopants from dopant reservoirs underneath the epitaxial part during epitaxy and to be activated by the epitaxy.

[0013] According to one aspect, a method for manufacturing at least one bipolar transistor, for example a heterojunction bipolar transistor, within an integrated circuit is therefore proposed.

[0014] The method includes creating a collector region including implanting dopants within a semiconductor substrate to form a first doped portion of the collector region, and forming a second doped portion of the collector region overlying and contacting an area of ​​the first doped portion.

[0015] The formation of the second doped portion comprises epitaxially growing a non-doped semiconductor material, such as non-doped single crystal silicon, from the region and diffusing dopants in the epitaxial material from the first doped portion, the diffusion being at least activated by the epitaxial growth.

[0016] Undoped semiconductor materials (such as silicon) typically have, for example, 3 Less than 10 15 A material with a dopant concentration of atoms.

[0017] Furthermore, epitaxy of semiconductor materials, such as monocrystalline silicon, is generally carried out at a given temperature for a certain time, so that this temperature makes it possible to activate the diffusion of dopants in the epitaxial material from the underlying reservoir (ie from the first doped portion).

[0018] However, depending on the thermal budget used, diffusion may also continue during subsequent conventional steps of bipolar transistor fabrication.

[0019] Therefore, this solution is easily implementable at an industrially acceptable cost.

[0020] Furthermore, as will be seen in more detail below, it easily enables the co-production of different types of transistors (high speed transistors or high breakdown voltage transistors) since one and the same epitaxy is used.

[0021] It is advantageous to control the diffusion of the dopant, so the method preferably includes controlling this diffusion.

[0022] There are several solutions to achieve this control.

[0023] According to one embodiment, the controlling may include adjusting the dose of the dopant, for example the phosphorus dose and / or the depth of the peak amount of the implanted dopant in said region.

[0024] According to one embodiment, the controlling may further include carbon ion implantation in the substrate so as to include carbon in the first doped portion.

[0025] In fact, carbon will make it possible to limit the diffusion of the dopant.

[0026] According to one embodiment, the control may include adjusting the carbon dose and / or the depth of the carbon amount peak implanted in the region relative to adjusting the dopant dose and / or adjusting the depth of the dopant (e.g. phosphorus) amount peak implanted in the region.

[0027] Of course, these various embodiments that make it possible to control the diffusion of dopants can be used alone or in combination with at least one other.

[0028] The second collector portion is in contact with the base region of the transistor.

[0029] Furthermore, according to a variant, the epitaxy of the undoped material (for example single-crystal silicon) continues up to the base region.

[0030] However, according to another variant, the epitaxy of the undoped material (e.g. single-crystal silicon) may also be stopped at a certain distance from the base region, and the control then comprises the continuation of the epitaxy with in situ carbon doping in the undoped material so as to form in the second portion an upper layer of semiconductor material containing carbon in contact with the base region.

[0031] A person skilled in the art will know how to choose various possibilities for performing control of the diffusion of dopants and the various amounts of implanted dopants and / or carbon and the relative positions of the peaks of dopants (e.g. phosphorus and carbon) according to the thermal budget achieved in the manufacture of the transistor and according to the final doping profile required for the collector of the transistor.

[0032] According to one embodiment, the method comprises: forming a stack of layers covering the first doped portion; forming a cavity in the stack until a surface of a region Z of the first doped portion is exposed; and forming the second doped portion in the cavity.

[0033] In some cases, due to the thermal budget implemented up to that point, the formation of the stack may affect the initial concentration of dopants implanted into the substrate and serve as a reservoir for the diffusion of the second portion of the collector region.

[0034] Therefore, in some cases it may be preferred to perform an additional (eg surface) implantation of the dopant in the first doped portion through the cavity before forming the second portion.

[0035] An additional carbon ion implantation, such as a surface implantation, may also be provided in the first doped portion through the cavity.

[0036] According to another aspect, a method for fabricating at least one first bipolar transistor (eg, a high speed transistor) and at least one second bipolar transistor (eg, a high breakdown voltage transistor) within an integrated circuit is presented.

[0037] The method comprises jointly manufacturing the at least one first transistor and the at least one second transistor using a method as described above, the implantation characteristics in the substrate being different for the at least one first transistor and for the at least one second transistor.

[0038] According to another aspect, an integrated circuit is provided, comprising a substrate and at least one bipolar transistor (eg a heterojunction bipolar transistor), including a collector region.

[0039] The collector region includes a first doped portion located in the substrate and a second doped portion overlying and contacting an area of ​​the first doped portion.

[0040] The collector region has a doping profile that has a peak at a first portion and decreases from the peak to a second portion.

[0041] Furthermore, the doping profile advantageously has no plateau in the second portion.

[0042] According to an embodiment, the collector region may further include carbon.

[0043] According to one embodiment, the second portion may include a layer of semiconductor material containing carbon near its end furthest away from the first portion.

[0044] According to one embodiment, an integrated circuit includes at least one first bipolar transistor and at least one second bipolar transistor, which are located at different locations of a substrate and have the same topology but different doping in their respective collector regions.

[0045] The transistors have the same topology, particularly when their corresponding structures in a cross-sectional view (e.g., the geometry of their active regions) do not differ significantly except for minor differences that may arise from non-uniformities in the manufacturing process (e.g., variations between the center and the edge of a wafer).

[0046] In other words, the only way to clearly distinguish between the two types of transistors is to, for example, analyze the doping profiles and evaluate the electrical performance.

[0047] Therefore, according to one embodiment, the at least one first transistor has a collector-emitter breakdown voltage-switching frequency pair that is different from the collector-emitter breakdown voltage-switching frequency pair of the at least one second transistor.

[0048] The at least one first transistor may have, for example, a collector-emitter breakdown voltage of 1.5 V to the nearest 10% and a switching frequency of 400 GHz. Thus, such a transistor may be, for example, a high-speed transistor.

[0049] As for the at least one second transistor, it may have, for example, a collector-emitter breakdown voltage of 3V to the nearest 10% and a switching frequency of 200 GHz. Thus, the second transistor may be a high breakdown voltage transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Other advantages and features of the present invention will become apparent upon examination of the detailed description of non-limiting embodiments and examples and the accompanying drawings, in which:

[0051] Figures 1 to 12 The steps of the manufacturing method are shown;

[0052] Figure 13 is a graph showing doping profile;

[0053] Figures 14 and 15 is a graph showing a doping profile according to the prior art;

[0054] Figures 16 to 18 The steps of the manufacturing method are shown;

[0055] Figure 19 A bipolar transistor is shown; and

[0056] Figure 20 The collector region is shown. DETAILED DESCRIPTION

[0057] exist Figure 1 In the Figures, reference numeral IC denotes an integrated circuit comprising a semiconductor substrate SB, for example made of silicon, in which insulating regions 1 and 2 are produced in a conventional and per se known manner from the front side FAV of the substrate.

[0058] Then, if Figure 2 As shown, an implantation IMP of a dopant, here phosphorus, is carried out in the substrate SB to form a first doped portion 3 which will be the first part of the future collector region of the transistor and will serve as a dopant reservoir.

[0059] It should be noted here that the bipolar transistor to be formed is an NPN transistor. However, the embodiments herein are also applicable to the formation of a PNP bipolar transistor. In this case, the phosphorus can be replaced by boron.

[0060] The dose of implanted dopants and the implantation energy depend on the final desired profile of the collector region of the transistor.

[0061] As an indication, 10 14 atoms / cm 2 to 10 15 atoms / cm 2 The phosphorus dosage is between 5×10 14 atoms / cm 2 of magnitude.

[0062] Here too, the depth of the implantation peak depends on the desired profile. As an indication, the implantation energy can be chosen so that the phosphorus peak is located in the substrate at a distance between 60 and 70 nanometers from the front-side FAV.

[0063] As will be seen in more detail below, at this stage, in addition to the phosphorus implantation, a carbon ion implantation may also be performed.

[0064] Then, if Figure 3 As shown, a stack 4 of layers covering the first doped portion 3 is formed in a conventional and per se known manner.

[0065] In this example, the stack 4 comprises, in particular, a supplementary insulating layer 40, on top of which lies a layer of P-doped polysilicon, intended to form part of the future extrinsic base of the transistor; a layer of P-doped silicon 42, intended to form the future intrinsic base of the transistor; and another insulating layer 43 (silicon nitride), on top of which lies another insulating layer 44 (silicon dioxide). The P-type silicon layer, intended to form the emitter region of the bipolar transistor after the N-type implant, is not present at this stage and will be deposited later.

[0066] Then, if Figure 4 As shown, a cavity 5 is formed in the stack 4 in a conventional and known manner until the surface of the region of the first doped portion 3 is exposed.

[0067] In the following steps, Figure 5 As shown, the epitaxy of the non-doped single-crystal silicon 60 is carried out from the upper surface of the region Z until reaching a height corresponding to the start of the future intrinsic base region of the transistor TR.

[0068] Therefore, the epitaxial region 60 covers the zone Z and is in physical contact with the first doped portion 3 .

[0069] The conditions for carrying out such an extension are known per se.

[0070] Epitaxy generally takes place at relatively high temperatures, for example 700° C., and it also activates the diffusion 61 of the dopant present in the first doped portion 3 , which here acts as a dopant reservoir.

[0071] In other words, epitaxy and diffusion occur together and make it possible to obtain the second portion 60 of the collector region which is also doped.

[0072] It should be noted here that, in a conventional and known manner, air pockets 45 appear at the ends of the layer 41 during the epitaxy process, which strengthen the insulation between the collector and the extrinsic base.

[0073] As an indication, in this embodiment the thickness (height) of the second portion 60 of the collector region may be on the order of 45 nanometers.

[0074] In order to be able to precisely fine-tune the desired doping profile, it is particularly advantageous to be able to control the diffusion of the dopant in the epitaxial semiconductor material 60 .

[0075] In this regard, if Figure 6 As shown very schematically in FIG, this control S10 can be performed in various ways which can be considered individually or in combination with one another.

[0076] Thus, controlling S10 may comprise adjusting S100 the dose of the dopant (eg phosphorus) and / or the depth of the peak of the amount of the dopant implanted in the first portion 3 and thus in the zone Z.

[0077] The control of the diffusion S10 may also include the carbon ion implantation S101 in the substrate as described above, so as to include carbon in the first doped portion 3 .

[0078] In fact, carbon makes it possible to control the diffusion of phosphorus (or boron) in epitaxial non-doped semiconductor materials.

[0079] As an indication, one can inject 14 atoms / cm 2 and 10 15 atoms / cm 2 The carbon dose between, for example, equal to 5×10 14 atoms / cm 2 .

[0080] The diffusion of the dopant can also be controlled by adjusting the carbon dose and / or the depth of the peak of the amount of carbon injected into the region Z relative to the dose of the dopant (e.g., phosphorus) injected into the region Z and / or the depth of the peak of the amount of the dopant (e.g., phosphorus) injected into the region Z S102.

[0081] Therefore, per cm 2 Injection 10 19 The phosphorus dose per cm 2 Injection 10 20 At a carbon dose of 10 atoms, the implant energy can be chosen to have a phosphorus peak between 60 and 70 nm and a carbon peak between 50 and 60 nm at the front FAV of the substrate.

[0082] like Figure 6 and Figure 7 As shown, controlling the diffusion of dopants may further include in-situ doping carbon in the undoped epitaxial material S103.

[0083] More specifically, if Figure 7 As shown, the epitaxy of the undoped material (undoped single-crystal silicon) stops at a distance from the layer 42, forming the future intrinsic base of the bipolar transistor. The epitaxy then continues with in-situ carbon doping until the layer 42 is reached, forming an upper silicon layer 601 containing carbon in the second part of the collector region and in contact with this layer 42 and therefore with the future intrinsic base of the transistor.

[0084] This in-situ doping epitaxy is usually performed with the help of silane and carbon and enhances the presence of carbon at the top of the collector region.

[0085] As an indication, in this embodiment, the thickness of the layer 601 may be of the order of 20 nanometers.

[0086] During the production of the stack 4 , the thermal budget used may have activated a certain diffusion of the dopant and / or carbon in the first doped part 3 .

[0087] Therefore, in this case, it is advantageous if Figure 8 As shown, once the cavity 5 is formed, an additional phosphorus and / or carbon implantation is performed in the first doped portion 3 through the cavity 5 to form an additional dopant reservoir 31 .

[0088] As an indication, once again one can implant per cm with an energy that results in surface implantation 2 10 19 The phosphorus dose per cm 2 10 20 Atoms of carbon.

[0089] Then, if Figure 9 As shown, diffusion 61 of dopants in the epitaxial material 60 takes place from the first doped portion 3 which is enhanced by the supplementary reservoir 31 .

[0090] After the conventional subsequent steps in fabricating bipolar transistors, such as Figure 10 As shown, an example of a bipolar transistor TR within an integrated circuit IC is obtained.

[0091] The bipolar transistor includes a collector region including a first doped portion 70 located in the substrate SB and a second doped portion 71 covering and contacting a region Z of the first doped portion 70 .

[0092] Furthermore, the bipolar transistor includes an extrinsic base region 81 , an intrinsic base region 80 and an emitter region 9 .

[0093] The transistor TR is here an NPN bipolar transistor having, for example, a heterojunction intrinsic base 80 (comprising, for example, silicon and germanium).

[0094] exist Figure 10 In the embodiment of the present invention, the isolation region 10 has a unique form of super shallow trench isolation (SSTI).

[0095] However, the embodiments herein are not limited to this embodiment and are fully compatible with other embodiments of the bipolar transistor TR, such as in Figure 11 and Figure 12 The same embodiment is schematically shown in FIG.

[0096] More specifically, in Figure 11 In FIG. 1 , the isolation region 10 has the form of an annular isolation super trench surrounding the intrinsic collector region.

[0097] In this regard, Figure 10 It can be noted that the height of the second portion 71 of the collector region, for example, is on the order of 95 nanometers, higher than Figure 11 The height of the portion 71 of the collector region of the transistor is, for example, 45 nanometers.

[0098] exist Figure 12 In FIG. 1 , the isolation region 10 does not include ultra shallow trench isolation, and only includes an isolation region located on the surface of the substrate SB.

[0099] like Figure 13 As schematically shown in the figure, the collector region of the transistor TR according to an embodiment of the present invention has a doping distribution PRF, which has a peak PC located in a first part of the collector region (i.e., in the substrate) and a decrease from the peak PC to a second part (i.e., in the doped diffused epitaxial region).

[0100] Furthermore, it can be seen that the doping profile has essentially a Gaussian shape and there is no plateau in the second portion.

[0101] Therefore, this doping profile is consistent with the Figure 14 The doping profile shown is clearly distinguishable from the prior art and would be obtained by in-situ doping of the epitaxial region of the collector.

[0102] In this case, the prior art doping profile PRF1 has a plateau region and a peak PC1 located in the in-situ doped epitaxial region.

[0103] The distributed PRF is also clearly distinguishable from the distributed PRF2 obtained by prior art transistors, where the collector region is an epitaxial and then implanted region.

[0104] from Figure 15 It can be seen that the doping peak PC2 is now located in the epitaxial and implanted regions.

[0105] Now more specifically refer to Figures 16 to 19 , to describe an embodiment for jointly producing a first transistor TRA and a second transistor TRB located at two different places in an integrated circuit IC.

[0106] More specifically, if Figure 16 As shown, in a similar way to reference Figure 1 After the isolation regions 1A and 2A are generated in the first portion SBA of the substrate and the isolation regions 1B and 2B in the second portion SBB, Figure 16 The structure obtained in the left part is covered by the mask MSKA and is similar to the reference Figure 2 The implantation of dopants and optionally carbon is carried out in the manner described in order to obtain a first doped portion 3B of the future collector region of the transistor TRB.

[0107] Then, if Figure 18 As shown on the right side of Figure 17 The structure obtained on the right side is covered by the mask MSKB and is similar to the reference Figure 3 The method described in Figure 17 The surface of the structure on the left is implanted with dopants and optionally carbon, the MSKA mask is cleared.

[0108] For the future transistor TRA, a first doped collector portion 3A is then obtained.

[0109] Then, execute the Figures 3 to 12 Similar steps are described in order to obtain exactly Figure 19 The left side shows the bipolar transistor TRA and the Figure 19 The right side shows the bipolar transistor TRB.

[0110] Transistor TRA and transistor TRB have the same topology (geometry of the collector region, etc.), but different doping in the collector. This makes it possible, for example, to jointly produce a high-speed transistor (such as transistor TRA) and a high collector-emitter breakdown voltage transistor (such as transistor TRB) on the same substrate using a single epitaxy.

[0111] In this regard, if Figure 20 As shown, for the transistor TRA, it is possible to select a transistor with a capacity of, for example, 3 10 18 to 10 20 The second portion 71A of the collector region of the first highly doped domain 710A is formed by a top portion having a doping capacity less than or equal to 1 cm 3 10 17 The low-doped domain 711A has a dopant concentration of atoms.

[0112] Furthermore, the thickness e1 of the domain 711A is less than 50% of the total thickness e1 + e2 of the epitaxy, for example being of the order of 30% of this total thickness.

[0113] For the transistor TRB, the second portion 71B of its collector region comprises a first highly doped domain 710B, the concentration of the dopant of which is again 100 Å per cm 3 10 18 to 10 20 atoms, with the top portion being a low-doped region 711B, for example, where the dopant concentration is less than or equal to 1 cm 3 10 17 atoms.

[0114] However, at this point, the thickness e4 of the domain 710B is less than 50% of the total thickness e3+e4 of the epitaxy, for example being of the order of 10% of this total thickness.

Claims

1. A method for fabricating at least one bipolar transistor within an integrated circuit, comprising: creating a collector region by implanting dopants into the semiconductor substrate to form a first doped portion of the collector region and forming a second doped portion of the collector region, the second doped portion covering and contacting an area of ​​the first doped portion; The forming of the second doped portion comprises: epitaxially growing an undoped semiconductor material from a surface of the region; and diffusing a dopant from the first doped portion into the epitaxial material; wherein said diffusion is activated by at least said epitaxial growth; and controlling the diffused dopant; wherein the second doped portion of the collector region is in contact with the base region of the transistor, wherein the epitaxial growth of the non-doped semiconductor material includes stopping the epitaxial growth at a certain distance from the base region, and The controlling comprises: continuing the epitaxial growth by in-situ doping carbon in the non-doped semiconductor material so as to form an upper layer containing carbon of the semiconductor material in the second doped portion, the upper layer being in contact with the base region. 2 . The method of claim 1 , further comprising controlling the diffusion of dopants by adjusting a dosage of the dopant implanted in the region. 3 . The method of claim 2 , wherein controlling further comprises implanting carbon ions in the substrate so as to include carbon in the first doping portion.

4. The method according to claim 1, further comprising: The diffusion of the dopant is controlled by adjusting the depth at which the amount of dopant implanted in the region peaks. 5 . The method of claim 4 , wherein controlling further comprises implanting carbon ions in the substrate so as to include carbon in the first doped portion. 6 . The method of claim 5 , wherein controlling further comprises adjusting a carbon dose implanted in the region relative to the depth at which the amount of dopant implanted in the region peaks. 7 . The method of claim 5 , wherein controlling further comprises adjusting a depth of a peak amount of carbon implanted in the region relative to adjusting a depth of a peak amount of dopant implanted in the region.

8. The method according to claim 1, further comprising: forming a stack of layers overlying the first doped portion; forming a cavity in the stack to expose a surface of the region of the first doped portion; as well as The second doped portion is formed in the cavity. 9 . The method of claim 8 , further comprising performing an additional implantation of a dopant in the first doped portion through the cavity before forming the second doped portion. 10 . The method of claim 9 , further comprising implanting additional carbon ions in the first doped portion through the cavity.

11. The method of claim 1 , wherein the at least one bipolar transistor comprises at least one first bipolar transistor and at least one second bipolar transistor, the method further comprising: jointly fabricating the at least one first transistor and the at least one second transistor; Wherein implanting comprises implanting different features in the substrate for the at least one first transistor and the at least one second transistor.

12. A method for fabricating at least one bipolar transistor within an integrated circuit, comprising: creating a collector region by implanting dopants into the semiconductor substrate to form a first doped portion of the collector region and forming a second doped portion of the collector region, the second doped portion covering and contacting an area of ​​the first doped portion; The forming of the second doped portion comprises: epitaxially growing an undoped semiconductor material from a surface of the region; and diffusing a dopant from the first doped portion into the epitaxial material; wherein said diffusion is activated by at least said epitaxial growth; and The diffusion of dopants is controlled by: adjusting a dose of a dopant implanted in the region; implanting carbon ions into the substrate so as to include carbon in the first doped portion; and A dose of carbon implanted in the region is adjusted relative to adjusting the dose of dopant implanted in the region.

13. A method for fabricating at least one bipolar transistor within an integrated circuit, comprising: creating a collector region by implanting dopants into the semiconductor substrate to form a first doped portion of the collector region and forming a second doped portion of the collector region, the second doped portion covering and contacting an area of ​​the first doped portion; The forming of the second doped portion comprises: epitaxially growing an undoped semiconductor material from a surface of the region; and diffusing a dopant from the first doped portion into the epitaxial material; wherein said diffusion is activated by at least said epitaxial growth; and The diffusion of dopants is controlled by: adjusting a dose of a dopant implanted in the region; implanting carbon ions into the substrate so as to include carbon in the first doped portion; and The depth of the peak amount of carbon implanted in the region is adjusted relative to adjusting the dose of the dopant implanted in the region.

14. An integrated circuit comprising: substrate; as well as At least one bipolar transistor comprising: A collector region comprising: a first doped portion located in the substrate; and a second doped portion, the second doped portion covering and contacting a region of the first doped portion; wherein the collector region has a doping profile having a concentration peak in the first doping portion and decreasing concentration from the peak to the second doping portion, and wherein the doping profile has a Gaussian shape and has no plateau in the second doping portion; wherein the collector region further comprises carbon; and The carbon concentration peak is located at a first depth from the front surface of the substrate, and the dopant concentration peak is located at a second depth from the front surface of the substrate, wherein the second depth is deeper than the first depth. 15 . The integrated circuit of claim 14 , wherein the second doped portion comprises a layer of semiconductor material containing carbon near an end of the second doped portion farthest from the first doped portion.

16. The integrated circuit of claim 14, wherein the at least one bipolar transistor comprises a first bipolar transistor and a second bipolar transistor, wherein the first bipolar transistor and the second bipolar transistor are located at different locations of the substrate, and wherein the first bipolar transistor and the second bipolar transistor have the same topology but different doping in their respective collector regions.

17. The integrated circuit of claim 16, wherein the first transistor has a collector-emitter breakdown voltage-switching frequency pair that is different from a collector-emitter breakdown voltage-switching frequency pair of the second transistor.

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