A method and device for optimizing dielectric layer flatness

Abstract

The embodiment of the present application discloses a method and device for optimizing the flatness of a dielectric layer. The method is used for an integrated circuit device. The surface of the integrated circuit device is divided into a dense area and an open area. There are device protrusions in the dense area, and there are no device protrusions in the open area. The method includes: performing a film forming process on the integrated circuit device to generate a dielectric layer and a first grinding layer; performing a flattening process on the first grinding layer to obtain a first grinding surface, and the treated first grinding surface is located between the dielectric layer and the first grinding layer; etching the first grinding surface based on the etching ratio of the dielectric layer and the first grinding layer to obtain a second grinding surface, and the second grinding surface is located in the dielectric layer, and the flatness of the grinding surface is greater than the flatness threshold. The technology provided by this solution can minimize the global drop of the dielectric layer, which not only meets the process requirements, but also greatly increases the subsequent process window.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method and device for optimizing the flatness of a dielectric layer. Background Art

[0002] In the semiconductor manufacturing process, the semiconductor surface needs to be flattened and ground to control the thickness within the corresponding process line width. For example, in current integrated circuits, the wafer surface is mainly polished with high precision through chemical mechanical polishing (CMP) technology, and can achieve ultra-high flatness with a global flatness drop of 100A to 1000A (equivalent to 10 to 100nm at the atomic level). However, with the continuous improvement of semiconductor process line width, the requirements for CMP flatness are getting higher and higher. Ordinary material flattening treatment has a flattening treatment limit, and the global drop may not meet the overall flatness requirements of advanced processes.

[0003] In the prior art, the interlayer dielectric (ILD)-CMP technology is usually used in the FDSOI process flow, that is, a single material planarization process is used. This method still has defects in the global planarization height, and the global height difference can still reach 150-300A, which cannot meet the ultra-high precision process requirements. Summary of the invention

[0004] The embodiment of the present application provides a method and device for optimizing the flatness of a dielectric layer. The technical solution is as follows:

[0005] In one aspect, a method for optimizing dielectric layer flatness is provided, the method comprising:

[0006] The method is used for an integrated circuit device, the surface of which is divided into a dense area and an open area, the dense area has device protrusions, and the open area has no device protrusions, and the method comprises:

[0007] Performing film forming treatment on the integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is located on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the empty area after the film forming treatment have different flatnesses;

[0008] Performing a planarization process on the first grinding layer to obtain a first grinding surface, wherein the planarization process includes performing a chemical mechanical polishing (CMP) process on the first grinding layer, and the first grinding surface after the process is located between the dielectric layer and the first grinding layer;

[0009] Based on the etching ratio of the dielectric layer and the first grinding layer, the first grinding surface is etched to obtain a second grinding surface, where the second grinding surface is located in the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold.

[0010] Specifically, the dielectric layer is filled with an oxide film layer, which is composed of oxide, and the thickness of the oxide film layer is 4000A; the first grinding layer is a polysilicon thin film layer, and the thickness of the polysilicon thin film layer is 2000-2500A;

[0011] Specifically, the planarizing the first grinding layer to obtain a first grinding surface includes:

[0012] Performing polysilicon thin film planarization processing on the dense area and the first grinding layer in the open area after the film forming processing;

[0013] When the grinding contacts the oxide film layer, the chemical mechanical polishing is stopped to obtain the first grinding surface;

[0014] The flatness of the first polished surface is less than the flatness threshold, and the hollow area is recessed by at least 100 Å relative to the polysilicon thin film layer in the dense area.

[0015] Specifically, etching the first grinding surface based on the etching ratio of the dielectric layer and the first grinding layer to obtain the second grinding surface includes:

[0016] Determining an etching ratio of the dielectric layer and the first grinding layer based on the recessed depth of the first grinding surface;

[0017] The oxide film layer and the polysilicon thin film layer in the first grinding surface are etched based on the etching ratio to obtain the second grinding surface.

[0018] Specifically, etching the oxide film layer and the polysilicon thin film layer in the first grinding surface based on the etching ratio to obtain the second grinding surface includes:

[0019] Determining an etching depth based on the etching ratio and the thickness of a target dielectric layer, wherein the etching depth is greater than a maximum thickness of the polysilicon film after planarization, and the thickness of the target dielectric layer is determined according to a semiconductor manufacturing process;

[0020] The oxide film layer and the polysilicon film layer in the first grinding surface are etched based on the etching ratio and the etching depth to obtain a second grinding curved surface; the flatness of the second grinding curved surface is less than the flatness threshold, and the second grinding curved surface has a global drop of at least 100A;

[0021] The second ground curved surface is subjected to an oxide film flattening treatment to obtain the second ground surface.

[0022] Specifically, after the integrated circuit device is subjected to film forming processing, there is at least a height difference of 600 to 800 Å between the polysilicon thin film layer and the oxide film layer.

[0023] Specifically, the thickness of the target dielectric layer is 600-800 Å, the etching ratio of the polysilicon thin film layer to the oxide film layer is 0.9:1, and the etching depth is 1000 Å.

[0024] On the other hand, a device for optimizing the flatness of a dielectric layer is provided, the device being used for an integrated circuit device, the surface of the integrated circuit device being divided into a dense area and an open area, the dense area having device protrusions, and the open area having no device protrusions, the device comprising:

[0025] A film forming module, used for performing film forming treatment on the integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is located on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the open area after the film forming treatment have different flatness;

[0026] A planarization processing module, used for performing a planarization processing on the first grinding layer to obtain a first grinding surface, wherein the planarization processing includes performing a chemical mechanical polishing (CMP) processing on the first grinding layer, and the first grinding surface after the processing is located between the dielectric layer and the first grinding layer;

[0027] The etching module is used to etch the first grinding surface based on the etching ratio of the dielectric layer and the first grinding layer to obtain a second grinding surface, wherein the second grinding surface is located in the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold.

[0028] On the other hand, a computer device is provided, comprising a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the method for optimizing dielectric layer flatness as described in the above claims.

[0029] The beneficial effects brought by the above technical solution include at least: when the integrated circuit device is subjected to film forming, a polysilicon thin film layer is additionally added to the outside of the dielectric layer as the first grinding layer, and the first grinding layer is first subjected to polysilicon thin film flattening treatment, and when the oxide film layer is ground, the chemical mechanical polishing is stopped; since the two film layers formed by the film forming are not horizontal surfaces, the integrated circuit device after grinding contains an oxide film layer and a polysilicon thin film layer; at this time, the etching ratio and etching depth are further determined according to the recess depth on the first grinding surface and the thickness of the target dielectric layer, and the first grinding surface is etched to obtain a second grinding curved surface, and finally the oxide film is flattened to obtain the second grinding surface. Minimizing the global drop not only meets the process requirements, but also greatly increases the subsequent process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of dielectric layer filling provided in an embodiment of the present application;

[0031] Figure 2 is a schematic diagram of generating a target dielectric layer based on ILD-CMP polishing provided in an embodiment of the present application;

[0032] Figure 3 is a flow chart of a method for optimizing dielectric layer flatness provided in an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of filling the dielectric layer and the first polishing layer provided in an embodiment of the present application;

[0034] Figure 5 is a schematic diagram of generating a first grinding surface and a recessed depth provided in an embodiment of the present application;

[0035] Figure 6 is a schematic diagram of generating a second grinding curved surface and a protrusion provided in an embodiment of the present application;

[0036] Figure 7 is a schematic diagram of generating a second grinding surface provided in an embodiment of the present application;

[0037] Figure 8 It is a structural block diagram of a device for optimizing dielectric layer flatness provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0039] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0040] In the related art, in the process flow of FDSOI, the ILD-CMP process adopts single-material planarization grinding. After the film is formed, CMP treatment is directly performed, that is, chemical mechanical polishing treatment is performed using oxide film polishing liquid to flatten the surface. Figure 1 As shown, the surface of the dense area of ​​the integrated circuit device 10 is embedded with logic circuits and components to form device protrusions; the surface of the open area has no logic circuits and components, and no device protrusions. In the semiconductor manufacturing process, it is necessary to perform film forming treatment on the surface of the integrated circuit device to generate a dielectric layer 101. With the continuous improvement of the semiconductor process line width, the thickness of the dielectric layer 101 is gradually reduced, and the flatness requirements of the dielectric layer 101 are also correspondingly increased, that is, the global drop of the surface of the dielectric layer 101 needs to meet a certain horizontal height. Figure 1 The dielectric layer 101 in the ILD is an oxide film layer (ILD OX). The thickness of the oxide film layer 101 formed during the film forming process is uniform, but due to the presence of device protrusions in the dense area of ​​the integrated circuit device 10, the global height difference is large, reaching 600-800A. When polishing by ILD-CMP technology, only the oxide film polishing liquid is used for planarization polishing. Ordinary single-material planarization processing has a planarization limit. Figure 2 As shown, the thickness of the oxide film layer 201 after grinding meets the process requirements, but the second grinding surface 210 formed after grinding has a depression depth of h2 (located in the open area), which reaches about 150 to 300 Å, and the global flatness does not meet the process requirements.

[0041] In the embodiment of the present application, considering the limited grinding accuracy of the ILD-CMP technology, when the integrated circuit device is subjected to film forming, an additional polysilicon film layer is added to the outside of the dielectric layer as the first grinding layer, and the first grinding layer is first subjected to polysilicon film flattening treatment, and when the oxide film layer is ground, the chemical mechanical polishing is stopped; since the two film layers formed by the film formation are not horizontal planes, the integrated circuit device after grinding contains an oxide film layer and a polysilicon film layer; at this time, the etching ratio and etching depth are continued to be determined according to the depth of the depression on the first grinding surface and the thickness of the target dielectric layer, and the first grinding surface is etched to obtain a second grinding curved surface, and finally the oxide film is flattened to obtain a second grinding surface. The flatness of the second grinding surface finally formed meets the process requirements.

[0042] Figure 3: is a flow chart of a method for optimizing dielectric layer flatness provided in an embodiment of the present application, which specifically includes the following steps:

[0043] Step 301, performing film forming processing on the integrated circuit device to generate a dielectric layer and a first polishing layer.

[0044] During the film forming process, an oxide film layer is first uniformly formed on the surface of the integrated circuit device to form the target dielectric layer. The oxide film layer is used to finally form the target dielectric layer. The thickness of the oxide film layer is determined according to the process flow and the thickness of the target dielectric layer. The target dielectric layer thickness is usually 600-800A, and the thickness of the filled oxide film layer is about 4000A. After the oxide film layer is filled, the first grinding layer is continued to be filled on the outside of the oxide film layer. The first grinding layer is used for grinding in the subsequent process. The first grinding layer in this solution is a polycrystalline silicon thin film layer Poly, and the thickness of the polycrystalline silicon thin film layer is controlled at 2000-2500A.

[0045] like Figure 4 As shown, since there are device protrusions on the surface of the integrated circuit device, and the thickness of the filled polysilicon film layer 401 and the oxide film layer 402 is uniform, there is a large global drop on the surface of the filled polysilicon film layer 401 and the oxide film layer 402. Figure 4 The thickness of the polysilicon film layer 401 is h2, the thickness of the oxide film layer 402 is h3, and the global height difference of the surface is h1 (the global height difference exists in the dense area). The global height difference is the height of the device protrusion.

[0046] Step 302, performing polysilicon thin film planarization processing on the first grinding layer in the dense area and the open area after the film forming processing.

[0047] Since the first grinding layer has a large global drop, the flatness cannot meet the process requirements. Figure 4 In the middle, h1 reaches 600-800A, so the polysilicon film layer needs to be planarized (Poly CMP). This process is to use abrasive liquid to perform chemical mechanical polishing to grind away the polysilicon film layer in dense areas and open areas.

[0048] Step 303, when the grinding contacts the oxide film layer, the chemical mechanical polishing is stopped to obtain a first grinding surface.

[0049] The grinding surface needs to be monitored during the grinding process of the polysilicon thin film layer. When the grinding contacts the oxide film layer (the highest point of the oxide film layer is contacted at this time), the chemical mechanical polishing is stopped immediately. The grinding surface obtained at this time is the first grinding surface.

[0050] like Figure 5As shown, this process has the same problem as the prior art, that is, the first grinding surface located in the open area relative to the dense area has a concave depth h4, and the experimentally measured h4 is about 150A, and the flatness of the first grinding surface 510 is less than the flatness threshold. For example, the flatness threshold requires that the global drop does not exceed 100A, so chemical mechanical polishing alone cannot meet the process requirements.

[0051] It should be noted that due to the global height difference, the first polishing layer is between the oxide film layer and the polysilicon film layer. Figure 5 , the first grinding surface 510 is in contact with the polysilicon film layer 501 and the oxide film layer 502 at the same time.

[0052] Step 304 : determining an etching ratio of the dielectric layer and the first grinding layer based on the recess depth of the first grinding surface.

[0053] In this solution, after the polysilicon film is planarized, the first grinding surface continues to be etched, and the etching technology can further reduce the global drop. It should be noted that in this solution, etching technology is not directly used to etch the dielectric layer or the first grinding layer. This is because the global drop caused by the device protrusion is large, and it is not suitable to use etching technology. Therefore, it is necessary to additionally fill the first grinding layer, perform chemical mechanical polishing, and then etch. In addition, etching technology usually uses atomic bombardment to etch the first grinding layer. Etching is to bombard the entire surface, but there are many device protrusions in dense areas, and the etching process cannot be controlled.

[0054] Before etching the first grinding surface, it is also necessary to determine the etching ratio of the dielectric layer and the first grinding layer according to the depression depth of the first grinding surface. Because the target dielectric layer finally generated is only the oxide film layer, and the depression depth needs to be eliminated, it is necessary to determine the etching ratio. In this scheme, the target dielectric layer thickness is 600-800A, and the etching ratio is 0.9:1, that is, the polysilicon and the oxide film layer and the oxide film layer are etched at a thickness of 0.9:1.

[0055] Step 305 , etching the oxide film layer and the polysilicon film layer in the first grinding surface based on the etching ratio to obtain a second grinding surface.

[0056] After the etching ratio is determined, the first grinding surface can be etched according to the etching ratio and using an etching technique. Specifically, physical etching or chemical etching technology can be used, which is not limited in this embodiment. It should be noted that under ultra-high process requirements, the etching process is not completed in one step. An etched surface will be formed during the etching process. After the etching is completed, the etched surface needs to continue to be subjected to chemical mechanical polishing. The process specifically includes the following steps:

[0057] 1. The etching depth is determined based on the etching ratio and the thickness of the target dielectric layer. The etching depth is greater than the maximum thickness of the polysilicon film after planarization. The thickness of the target dielectric layer is determined according to the semiconductor manufacturing process.

[0058] After determining the etching ratio of the polysilicon film layer and the oxide film layer, the etching depth is determined according to the thickness of the target dielectric layer, and the etching depth needs to ensure that the polysilicon film layer can be removed, that is, the etching depth is greater than the maximum thickness of the polysilicon film after planarization.

[0059] As in this solution, the global height difference corresponding to the oxide film layer is 800A, and the target dielectric layer thickness is 800A, so the etching depth should be at least greater than 800A. At the same time, in order to ensure the workload of the subsequent chemical mechanical polishing process and to avoid causing the depth of the recess again, the etching depth should be increased as much as possible and set to 1000A.

[0060] 2. Etching the oxide film layer and the polysilicon film layer in the first grinding surface based on the etching ratio and etching depth to obtain a second grinding curved surface.

[0061] Although the etching process continues to etch down 1000A on the basis of the original first grinding surface according to the etching ratio (the etching depth of the oxide film layer is 1000A), the use of atomic bombardment cannot guarantee that a grinding surface with a higher flatness will be obtained after the etching is completed. In the actual etching process, multiple protrusions will be formed in the dense area and the empty area after the etching is completed, which is the second grinding surface.

[0062] like Figure 6 As shown, the second grinding curved surface 610 formed after etching is completely composed of the oxide film layer 601. There are multiple protrusions 602 in the second grinding curved surface 610. The height of the protrusion 602 is h5, which is usually a global drop of 100A. Therefore, the flatness of the second grinding curved surface 610 is less than the flatness threshold.

[0063] 3. Performing an oxide film flattening treatment on the second grinding curved surface to obtain a second grinding surface.

[0064] On the basis of the second grinding surface, the oxide film layer is further subjected to oxide film flattening (ILD-CMP) treatment. In this treatment process, the grinding liquid is also used for chemical mechanical polishing. Unlike the prior art, this step is to eliminate the global drop caused by the protrusions on the second grinding surface, and the oxide film layer is further ground to the target dielectric layer thickness. Compared with the prior art method of directly grinding the first grinding surface, the grinding thickness of this process is greatly reduced, and the global drop of the second grinding surface is relatively low, so the second grinding surface finally obtained will not form a large concave depth. Figure 7As shown, the second polishing surface 710 is completely composed of the oxide film layer 701, that is, the target dielectric layer is generated, and the global drop of the second polishing surface 710 is usually around 50A, which is much smaller than the global drop of 150 to 300A in the prior art. Therefore, the flatness is greater than the flatness threshold (for example, the global drop corresponding to the flatness threshold is 80A).

[0065] In summary, in the implementation of this application, when the integrated circuit device is subjected to film forming, an additional polysilicon thin film layer is added to the outside of the dielectric layer as the first grinding layer, and the first grinding layer is first subjected to polysilicon thin film flattening treatment, and when the oxide film layer is ground, the chemical mechanical polishing is stopped; since the two film layers formed by the film formation are not horizontal planes, the integrated circuit device after grinding contains an oxide film layer and a polysilicon thin film layer; at this time, the etching ratio and etching depth are continued to be determined according to the depth of the depression on the first grinding surface and the thickness of the target dielectric layer, and the first grinding surface is etched to obtain a second grinding curved surface, and finally the oxide film is flattened to obtain a second grinding surface. Minimizing the global drop not only meets the process requirements, but also greatly increases the subsequent process window.

[0066] Figure 8 : is a structural block diagram of a device for optimizing dielectric layer flatness provided in an embodiment of the present application. The device is used for an integrated circuit device, the surface of which is divided into a dense area and an open area, the dense area has device protrusions, and the open area has no device protrusions, and the device comprises:

[0067] The film forming module 801 is used to perform film forming treatment on the integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is located on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the empty area after the film forming treatment have different flatnesses;

[0068] A planarization processing module 802 is used to perform a planarization process on the first grinding layer to obtain a first grinding surface, wherein the planarization process includes performing a chemical mechanical polishing (CMP) process on the first grinding layer, and the first grinding surface after the process is located between the dielectric layer and the first grinding layer;

[0069] The etching module 803 is used to etch the first grinding surface based on the etching ratio of the dielectric layer and the first grinding layer to obtain a second grinding surface, where the second grinding surface is located in the dielectric layer and the flatness of the grinding surface is greater than a flatness threshold.

[0070] In an embodiment of the present application, a computer device is also provided, which includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the method for optimizing the flatness of the dielectric layer provided by the above-mentioned various method embodiments.

[0071] The preferred embodiments of the present invention are described above; it should be understood that the present invention is not limited to the above-mentioned specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify them into equivalent embodiments with equivalent changes, which does not affect the essential content of the present invention; therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A method for optimizing the flatness of a dielectric layer, characterized in that: The method is used for an integrated circuit device, the surface of which is divided into a dense area and an open area, the dense area has device protrusions, and the open area has no device protrusions, and the method comprises: Performing film forming treatment on the integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is located on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the empty area after the film forming treatment have different flatnesses; The first grinding layer is planarized to obtain a first grinding surface, wherein the planarization process includes chemical mechanical polishing (CMP) of the first grinding layer, and the first grinding surface after the treatment is located between the dielectric layer and the first grinding layer; the dielectric layer is filled with an oxide film layer and is composed of oxide, the first grinding layer is a polysilicon thin film layer, the flatness of the first grinding surface is less than a flatness threshold, and the empty area has a recess depth of at least 150 angstroms relative to the polysilicon thin film layer in the dense area; Determining an etching ratio of the dielectric layer and the first grinding layer based on the recessed depth of the first grinding surface; Determining an etching depth based on the etching ratio and the thickness of the target dielectric layer; the etching depth is greater than the maximum thickness of the polysilicon film after planarization; Etching the oxide film layer and the polysilicon film layer in the first grinding surface based on the etching ratio and the etching depth to obtain a second grinding curved surface; the flatness of the second grinding curved surface is less than the flatness threshold, and the second grinding curved surface has a global drop of at least 100 angstroms; The second grinding curved surface is subjected to an oxide film flattening treatment to obtain a second grinding surface; the second grinding surface is located in the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold.

2. The method according to claim 1, characterized in that The thickness of the oxide film layer is 4000 angstroms; the thickness of the polysilicon thin film layer is 2000-2500 angstroms.

3. The method according to claim 2, characterized in that The step of flattening the first grinding layer to obtain a first grinding surface comprises: Performing polysilicon thin film planarization processing on the dense area and the first grinding layer in the open area after the film forming processing; When the grinding contacts the oxide film layer, the chemical mechanical polishing is stopped to obtain the first grinding surface.

4. The method according to any one of claims 1 to 3, characterized in that: After the integrated circuit device is subjected to film forming processing, there is a height difference of at least 600 to 800 angstroms between the polysilicon thin film layer and the oxide film layer.

5. The method according to any one of claims 1 to 3, characterized in that: The thickness of the target dielectric layer is 600-800 angstroms, the etching ratio of the polysilicon thin film layer to the oxide film layer is 0.9:1, and the etching depth is 1000 angstroms.

6. A device for optimizing the flatness of a dielectric layer, characterized in that: The device is used for an integrated circuit device, the surface of which is divided into a dense area and an open area, the dense area has device protrusions, and the open area has no device protrusions, and the device comprises: A film forming module, used for performing film forming treatment on the integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is located on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the open area after the film forming treatment have different flatness; a planarization processing module, used for planarizing the first grinding layer to obtain a first grinding surface, wherein the planarization process includes performing a chemical mechanical polishing (CMP) process on the first grinding layer, and the first grinding surface after the process is located between the dielectric layer and the first grinding layer; the dielectric layer is filled with an oxide film layer and is composed of oxide, the first grinding layer is a polysilicon thin film layer, the flatness of the first grinding surface is less than a flatness threshold, and the empty area has a recess depth of at least 150 angstroms relative to the polysilicon thin film layer in the dense area; An etching module, configured to determine an etching ratio of the dielectric layer and the first grinding layer based on the recess depth of the first grinding surface; Determining an etching depth based on the etching ratio and the thickness of the target dielectric layer; the etching depth is greater than the maximum thickness of the polysilicon film after planarization; Etching the oxide film layer and the polysilicon film layer in the first grinding surface based on the etching ratio and the etching depth to obtain a second grinding curved surface; the flatness of the second grinding curved surface is less than the flatness threshold, and the second grinding curved surface has a global drop of at least 100 angstroms; The second grinding curved surface is subjected to an oxide film flattening treatment to obtain a second grinding surface; the second grinding surface is located in the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold.

7. A computer device, characterized in that: The computer device includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the method for optimizing the flatness of a dielectric layer as claimed in any one of claims 1 to 5.

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