Wafer alignment using multi-scan electron microscope

Abstract

A method, processing device, and system are disclosed. The method includes controlling a multi-scan electron microscope (mSEM) to capture a first image of a wafer attached to an electro-mechanical stage while the electro-mechanical stage is in a first position. The first image includes at least a portion of a recess of the wafer. The method also includes determining a radial axis of the wafer based on the first image, and controlling the electro-mechanical stage to displace the wafer along the radial axis by a half diameter of the wafer to cause the electro-mechanical stage to be in a second position. The method further includes controlling the mSEM to capture a second image of the wafer while the electro-mechanical stage is in the second position. The second image includes a structure of the wafer. Additionally, the method includes determining a reference position of the wafer based on structure recognition of the structure of the wafer of the second image, and registering a wafer coordinate system of the wafer to a stage coordinate system of the electro-mechanical stage based on the reference position and the radial axis.

Description

Technical Field

[0001] This application generally relates to wafer alignment techniques. More specifically, the present invention relates to wafer alignment using a multi-scan electron microscope. Background Technology

[0002] Current state-of-the-art semiconductor structures are built to a minimum structure size, or critical size, of approximately 5 nanometers, and devices with even smaller critical sizes are being developed. Manufacturing such a semiconductor structure may involve approximately 1000 manufacturing steps, starting from a blank wafer to form an array of semiconductor dies, each including the semiconductor structure. These manufacturing steps may include, for example, approximately 100 photolithography steps. In a modern production line, each photolithography step may process up to 200 wafers per hour.

[0003] Each semiconductor die, and sometimes each semiconductor structure, has a clearly defined location within a wafer coordinate system. This wafer coordinate system defines the lateral positioning of the wafer on a plane. This wafer coordinate system may be aligned with, for example, (i) the center or other center of the wafer and (ii) the notch of the wafer.

[0004] To achieve near 100% high yield in semiconductor structures, close monitoring of variations in any manufacturing step is typically required, as these variations may indicate process changes leading to defects. Therefore, high-speed in-line metrology is used between different manufacturing steps, or integrated into those steps. This metrology is sometimes also referred to as wafer inspection. Metrological tools are used to detect process variations or indications of defect candidates within the structure after a specified manufacturing step. Typical silicon wafers used to produce semiconductor structures have diameters up to 12 inches (300 mm). In the case of small structure sizes, the requirement is to identify defect candidates on the order of magnitude of critical dimensions over a large area in a short time.

[0005] For wafer inspection, imaging modalities such as scanning electron microscopy (SEM) or x-ray diffraction are typically used to capture some type of image of the wafer surface. The field-of-view (FOV) of this imaging modal is within a defined arrangement of a motorized loading stage to which the wafer can be attached. Typically, such a motorized loading stage has at least two, three, or even more degrees of freedom (e.g., lateral, vertical, rotational, and tilting). This motorized loading stage can be positioned with high precision, for example, using closed-loop feedback control for any associated motion. The motion of the wafer loading stage is constrained within a stage coordinate system associated with the motorized loading stage.

[0006] Therefore, semiconductor wafer inspection is crucial for semiconductor process control and production. Defect monitoring and yield management services involve numerous steps and types of analysis. Wafer inspection forms an integral part of this task. Due to the extremely small size of the features and defects (approximately a few nanometers), a good reference point is required for guiding the wafer through the bare die and wafer (i.e., positioning the motorized loading stage). Wafer alignment is used to register the wafer coordinate system to the stage coordinate system. Such alignment can be used to create a wafer map, which is a mapping between the positioning in the stage coordinate system and the positioning in the wafer coordinate system. Therefore, wafer alignment and wafer map creation form the basis for subsequent diagnostic / characterization methods because the FOV alignment of the imaging modality used for wafer inspection is within the stage coordinate system.

[0007] According to reference techniques, wafer alignment can be a very time-consuming task. For example, it often requires a combination of different microscopy techniques offering varying degrees of (i) resolution and (ii) field of view (FOV). Coarse alignment is typically performed using a microscopy technique that provides a wide FOV. Such a microscope using a wide FOV may have limited resolution. A common example is optical microscopy. Fine alignment, then, is performed using yet another microscopy technique (such as SEM, which offers higher resolution but often has limited available FOV). In this case, inaccuracies or shifts can be introduced due to switching between the two microscopy techniques, making wafer alignment difficult. In particular, the fields of view between multiple imaging modalities may be misaligned. Furthermore, the orientation of the detector optics of each of the multiple imaging modalities with respect to the wafer may vary, for example, due to non-uniaxial alignment. For instance, it may be necessary to take multiple images for fine alignment to detect positioning marks. Due to the limited FOV of the microscopy techniques used for fine alignment, ambiguities in the reproducible arrangement of positioning marks or semiconductor structures can sometimes lead to incorrect registration results.

[0008] The following references are known: US 10,199,330 B2 and US 10,199,316 B2. Summary of the Invention

[0009] Therefore, advanced wafer alignment technology is needed. In particular, advanced technology is needed to overcome or mitigate at least some of the aforementioned limitations.

[0010] The features described below satisfy this requirement.

[0011] A method includes controlling a multi-scanning electron microscope (mSEM) to acquire a first image of a wafer attached to a motorized loading stage. The mSEM is controlled to acquire the first image while the motorized loading stage is in a first position. The first image includes at least a portion of a recess in the wafer. The method also includes determining a radial axis of the wafer based on the first image. The method further includes controlling the motorized loading stage to displace the wafer along the radial axis by half its diameter; then, the motorized loading stage is in a second position. The method further includes controlling the mSEM to acquire a second image of the wafer while the motorized loading stage is in the second position. The second image includes the wafer structure. The method also includes determining a reference position of the wafer based on structural recognition of the wafer structure in the second image. The method further includes registering the wafer coordinate system of the wafer to the stage coordinate system of the motorized loading stage based on the reference position and the radial axis.

[0012] A computer program, a computer program product, or a computer-readable storage medium includes program code executable by at least one processor. Executing the program code causes the at least one processor to perform a method. The method includes controlling a multi-scanning electron microscope (mSEM) to capture a first image of a wafer. The wafer is attached to a motorized loading stage. The mSEM is controlled to capture the first image while the motorized loading stage is in a first position. The first image includes at least a portion of a recess in the wafer. The method further includes determining a radial axis of the wafer based on the first image. The method further includes controlling the motorized loading stage to displace the wafer along the radial axis by half a diameter of the wafer; then, the motorized loading stage is in a second position. The method further includes controlling the mSEM to capture a second image of the wafer while the motorized loading stage is in the second position. The second image includes a wafer structure. The method further includes determining a reference position of the wafer based on structural identification of the wafer structure in the second image. The method further includes registering a wafer coordinate system of the wafer to a stage coordinate system of the motorized loading stage based on the reference position and the radial axis.

[0013] A processing apparatus includes control circuitry. The control circuitry is configured to control a multi-scanning electron microscope (mSEM) to acquire a first image of a wafer attached to a motorized loading stage while the stage is in a first position. The first image includes at least a portion of a recess in the wafer. The control circuitry is further configured to determine a radial axis of the wafer based on the first image. The control circuitry is further configured to control the motorized loading stage to displace the wafer along the radial axis by half its diameter, thereby positioning the stage in a second position. The control circuitry is further configured to control the mSEM to acquire a second image of the wafer while the stage is in the second position, the second image including the wafer structure. The control circuitry is further configured to determine a reference position of the wafer based on structural identification of the wafer structure in the second image. The control circuitry is further configured to align the wafer coordinate system to the stage coordinate system of the motorized loading stage based on the reference position and the radial axis.

[0014] A system includes the processing device described above and an mSEM.

[0015] Examples are defined below.

[0016] In a preferred embodiment of the method, the wafer structure undergoing this structural identification includes orthogonal die cuts between adjacent semiconductor dies.

[0017] In a preferred embodiment of the method, the wafer comprises an array of semiconductor dies; and the method further comprises: determining one or more other axes of the wafer; controlling the motorized loading stage to traverse along the one or more other axes; controlling the mSEM to capture one or more third images while traversing along the one or more other axes, the one or more third images comprising the semiconductor structure of the semiconductor dies of the array; determining the semiconductor structure based on the identification of another structure in the one or more third images; and registering the die coordinate system of the semiconductor dies to the stage coordinate system based on the further structure identification.

[0018] In a preferred embodiment of the method, the one or more other axes include an axis that is offset about a central radial axis.

[0019] In a preferred embodiment of the method, the offset is determined based on the width of the die dicing track between adjacent semiconductor dies in the array.

[0020] In a preferred embodiment of the method, the field of view of the mSEM is 60% to 140% of the offset.

[0021] In a preferred embodiment of the method, multiple third images are captured for multiple adjacent semiconductor dies of the array that are adjacent to each other along one or more other axes; and the semiconductor structure in the multiple third images is determined by comparing the multiple third images with each other.

[0022] In a preferred embodiment of the method, the first image includes a saddle point of the groove, and the radial axis of the wafer is determined based on the saddle point.

[0023] In a preferred embodiment of the method, the method further includes: controlling an optical microscope to capture an optical image of the wafer; identifying the groove in the optical image; and controlling the motorized loading stage to laterally move to the first position based on the identification of the groove and a predefined alignment between the field of view of the mSEM and the stage coordinate system.

[0024] In a preferred embodiment of the processing device, the control circuit is configured to perform the method described above.

[0025] It should be understood that the features mentioned above and the following description may be used not only in the indicated combinations but also in other combinations or alone without departing from the scope of the invention. Attached Figure Description

[0026] Figure 1 The illustrations illustrate various types of wafer coordinate systems and stage coordinate systems.

[0027] Figure 2 The diagram illustrates bare core coordinate systems based on various paradigms.

[0028] Figure 3 These illustrations illustrate various models of chip manufacturing and chip inspection.

[0029] Figure 4 The illustrations are based on various paradigms of systems.

[0030] Figure 5 It is a flowchart based on various examples of methods.

[0031] Figure 6 The illustrations illustrate the grooves and centers of wafers according to various types.

[0032] Figure 7 The illustrations illustrate the grooves and centers of wafers according to various types.

[0033] Figure 8 The illustrations depict the bare semiconductor dies around the center of a wafer according to various types. Detailed Implementation

[0034] Some examples of the present invention generally provide for use in multiple circuits or other electronic devices. All references to the circuits and other electronic devices, and the functionality provided therein, are not intended to be limited to what is illustrated and described herein. Although specific designations may be assigned to the various circuits or other electronic devices disclosed, such designations are not intended to limit the scope of operation of the circuits and other electronic devices. Such circuits and other electronic devices may be combined and / or separated from each other in any manner based on a particular type of desired electronic implementation. It is understood that any circuit or other electronic device disclosed herein may include any number of microcontrollers, graphics processing units (GPUs), integrated circuits, memory devices (such as flash memory, random access memory (RAM), read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or other suitable variations), and software that cooperates to perform the operations disclosed herein. Furthermore, any one or more of the electronic devices may be configured to execute program code embodied in a non-transitory computer-readable medium programmed to perform any number of functions as disclosed.

[0035] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the following description of the embodiments is not intended to be limiting. The scope of the present invention is not limited to the embodiments or drawings described below, which are considered to be illustrative only.

[0036] The accompanying drawings should be considered schematic diagrams, and the elements shown are not necessarily displayed to scale. Rather, the representation of the various elements makes their function and general purpose obvious to those skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be achieved through indirect connections or couplings. Coupling between components may also be established via wireless connections. Functional blocks may be implemented in hardware, firmware, software, or a combination thereof.

[0037] The following describes a technique for wafer alignment. The technique described herein facilitates the generation of a wafer map. This wafer map indicates (i) a mapping from the position in the stage coordinate system of the motorized loading stage to (ii) a mapping from the position in the wafer coordinate system associated with the wafer. This wafer map can be used for wafer inspection, for example, to align one or more positions on the wafer with the field of view (FOV) of an associated imaging modality.

[0038] Based on the techniques described in this article, multi-scan electron microscopy (mSEM) can be used for wafer alignment.

[0039] In particular, the various examples are based on the finding that, in each reference implementation, wafer alignment is a two-step process, comprising: first, coarse alignment using an optical microscope, and second, fine alignment using a scanning electron microscope. According to the various examples described herein, mSEM can be used to complete the entire process for wafer alignment, thus omitting the coarse alignment using an optical microscope. This mSEM is an implementation of charged particle microscopy. In mSEM, the wafer is irradiated by an array of electron beams (including, for example, more than 40 or even more than 90 electron beams) as primary radiation. The beams scan together over the wafer to collectively form a large-area image of the wafer. Multiple beams are used to obtain individual images according to the scan positioning. This provides for a large FOV. The image is formed based on secondary particles or radiation emitted from the wafer in response to irradiation using primary radiation (i.e., electron beams). The secondary radiation may take the form of secondary electrons, backscattered electrons, X-rays, and / or luminescent radiation. The composition, energy, and angle of secondary radiation can be controlled by the energy of primary radiation, indicating the material composition and surface quality of the scanned wafer surface. mSEM allows for rapid scanning of wafer surfaces and is therefore ideal for wafer metrology with high throughput. For example, the FOV of an mSEM can be on the order of 100 μm × 100 μm or even 120 μm × 120 μm; while the FOV of a conventional scanning electron microscope may be on the order of 1 μm × 1 μm. The resolution of each mSEM image can be on the order of 5 nm × 5 nm.

[0040] By using mSEM in wafer alignment, both fine and coarse alignment can be performed in a single operation. Specifically, for example, global and local features can be identified from mSEM images without the need for complementary optical imaging. This makes wafer alignment robust and simplifies it. More specifically, it becomes possible to reduce translational errors (which would otherwise be encountered when using multiple imaging modalities without uniaxial alignment). The large FOV of mSEM can be used to identify unique structures on the wafer, such as positioning marks or semiconductor structures or other wafer structures, and to use such structures for wafer alignment. Furthermore, the large FOV also ensures uniqueness, for example, when combined with image processing algorithms such as feature recognition: typically, the background of repetitive structures on the wafer can be captured by the large FOV of mSEM, and thus the ambiguity of the repetitive nature of these structures can be resolved. The high resolution of mSEM allows for accurate alignment by using small features of the structure.

[0041] Figure 1 The illustrations illustrate various aspects of the stage coordinate system 191 and the wafer coordinate system 192. The stage coordinate system 191 is associated with the electrically operated wafer loading and unloading stage 90 (hereinafter referred to as the stage).

[0042] A wafer 100 is attached to a stage 90. The wafer 100 includes an array 111 of semiconductor dies 112. The array 111 defines a repeating order of the semiconductor dies 112. The wafer 100 also includes a recess 201, which, together with the center of the wafer 100, defines a wafer coordinate system 192 (in...). Figure 1 In this example, the wafer coordinate system 192 is defined by lateral dimensions; perpendicular to Figure 1 (The vertical dimensions of the diagram plane are not shown).

[0043] Despite Figure 1 In one example, the origin of the wafer coordinate system 192 is aligned with the recess 201, but in other examples, the origin of the wafer coordinate system 192 may be set in other ways, such as with respect to the center of the wafer 100 or another reference location.

[0044] The following describes the technique of wafer alignment. Wafer alignment refers to the process of aligning the wafer coordinate system 192 to the stage coordinate system 191.

[0045] After the wafer 100 is mounted onto the stage 90, the arrangement of the wafer coordinate system 192 with respect to the stage coordinate system 191 is unknown, or at least unknown in terms of the required manufacturing or metrological accuracy. For example, in the lateral plane, there may be rotation of the primary axis of the wafer coordinate system 192 about the primary axis of the stage coordinate system 191. Furthermore, the lateral principal axis of the wafer coordinate system 192 may be tilted out of the lateral plane of the stage coordinate system 191 (i.e., the wafer surface is tilted out of the mounting surface of the stage 90 due to non-planar mounting), to name just a few examples that could lead to differences between the stage coordinate system 191 and the wafer coordinate system 192. The effects of such differences can be compensated for by aligning the wafer coordinate system 192 to the stage coordinate system 191. Coordinate transformations can be determined between the wafer coordinate system 192 and the stage coordinate system 191, and / or vice versa.

[0046] Sometimes, in addition to the stage coordinate system 191 and the wafer coordinate system, a die coordinate system may be used. Furthermore, the die coordinate system may be registered to the stage coordinate system as part of wafer alignment. Detailed information regarding die coordinate systems is available upon request. Figure 2 illustrate.

[0047] Figure 2 The diagram illustrates various aspects of the die coordinate system 193. The die coordinate system 193 is associated with the semiconductor dies 112 of the array 111. Specifically, each semiconductor die 112 of the array 111 may have its own associated die coordinate system 193. The positioning of one or more semiconductor structures 113 within each semiconductor die 112 may be defined with respect to their respective die coordinate system 193. The semiconductor dies 112 may be repeatable, meaning that each semiconductor die 112 may include the same arrangement of the same one or more semiconductor structures 113.

[0048] As a general rule, each semiconductor die 112 may have its own die coordinate system 193, which is defined with respect to a corresponding origin located at a reference position of the respective semiconductor die 112 (such as at its corner or center). The multiple die coordinate systems 193 may be transformed into each other by translational displacement between the respective reference positions of the multiple semiconductor dies 112.

[0049] Sometimes, the die coordinate system 193 is also referred to as a local coordinate system because it defines the local location of the semiconductor structure 113 in each of the dies 112; similarly, the wafer coordinate system 192 is sometimes referred to as a global coordinate system because it globally (i.e., at the wafer level of the wafer 100) defines the location of the dies 112 of the array 111.

[0050] Depending on various models, the die coordinate system 193 of the semiconductor die 112 may be registered to the stage coordinate system 191, for example, as part of wafer alignment. This may include finding a suitable reference position for each semiconductor die 112.

[0051] For example, the stage 90 can then be positioned by appropriately controlling its motors so that one of the semiconductor structures 113 is centered in the FOV of the corresponding imaging mode (having an FOV aligned with the stage 90). Wafer inspection can then be performed.

[0052] As a general rule, the typical lateral length scale of semiconductor structure 113 can be on the order of several nanometers to tens of nanometers. The typical lateral length scale of semiconductor die 112 can be on the order of tens of micrometers to 100 micrometers, which is at least 1000 times larger than the typical length scale of semiconductor structure 113. Therefore, by using mSEM, it is possible to have sufficiently high resolution to image the details of each semiconductor structure 113, and sufficiently large FOV to image a large portion of semiconductor die 112. This facilitates both coarse and fine alignment.

[0053] As discussed herein, wafer alignment may be employed as in-line metering during the production of semiconductor structures. This is an example of the production of semiconductor structures as an application environment for various specific embodiments. Figure 3 Example in.

[0054] exist Figure 3 In this process, the production of the semiconductor structure begins with a blank wafer 100. Examples of such wafers include silicon wafers or gallium arsenide wafers, but any semiconductor wafer may be used.

[0055] First, wafer 100 undergoes what is known as front-end processing 11. Front-end processing involves all processing steps in which the various structures on the wafer are formed before being mechanically separated (detached) from each other. For mass production, multiple equivalent structures are formed on the wafer and then separated into discrete semiconductor structures.

[0056] Front-end processing 11 includes multiple manufacturing steps 13. Such manufacturing steps 13 may include etching, layer deposition, diffusion, or implantation of semiconductor or metal layers, such as for doping, cleaning, wafer planarization, photoresist coating and treatment, photolithography, etc. Through these manufacturing steps 13, structures are formed on wafer 100, such as an array 111 of semiconductor dies (see...). Figure 1 ).

[0057] After certain manufacturing steps 13, the wafer undergoes in-line metrology / wafer inspection 14. Alternatively, in addition to in-line metrology 14, measurements may be performed "in situ," i.e., during one or more periods of manufacturing steps 13.

[0058] For wafer inspection, the methods and components described above and further explained below are used for wafer alignment. Wafer inspection may include various measurements of physical parameters, such as film thickness, film uniformity, particle or contaminant detection, or measurements of electrical parameters, such as resistance or capacitance. By using metrology, the dimensions of the various structures formed on the wafer can be determined by obtaining an image of the wafer. Since the wafer coordinate system 192 (and, if necessary, the die coordinate system 193) is registered to the stage coordinate system 191, the image may be obtained at a clearly defined location on the wafer. If necessary, a defect map 16 of the wafer may be obtained, i.e., information indicating that the structures on the wafer have not yet been formed as required. The defect map can be defined by the wafer coordinate system 192. Determining the presence or absence of defects may be performed by comparing the image data with data previously collected for similar segments of another object (die to die), or by comparing with a reference database (die to database) or design data (die to computer-aided design (CAD)). All data can be processed and controlled in databases, including defect databases that form collectives of representative defects, CAD databases that collect information about ideal or representative structures, and process formulations.

[0059] During manufacturing step 13 or at in-line wafer inspection 14, these measurements for wafer inspection may be performed directly on the product wafer, i.e., on the wafer on which a semiconductor structure is to be manufactured directly or using a specific test structure for sale, or on a specific non-functional monitor wafer (also referred to as a dummy wafer). A specifically designed test structure is also known as a process control monitor (PCM).

[0060] When a defect is detected, the defective wafer 100 may be provided to at-line wafer defect review and classification 17. "At-line" indicates that the wafer 100 in this case is removed from the normal manufacturing process for further inspection. Specifically, in review and classification 17, locations identified in the wafer defect map may be reviewed to verify and classify indications of process variations or defects. Since the wafer coordinate system 192 (and, if necessary, the die coordinate system 193) is registered to the stage coordinate system 191, images may be acquired at clearly defined locations on the wafer 100. Therefore, the stage 90 can be moved to an appropriate location for the corresponding imaging mode.

[0061] As a result, for example, to modify manufacturing parameters to count process changes, a feedback instruction 15 for manufacturing may be given, or an instruction may be given for maintenance due to possible defective components in the corresponding manufacturing equipment.

[0062] This process is repeated until all layers determined to be processed at inspection point 18 are complete. Afterward, wafer probe testing 19 may be performed, whereby structures on the wafer are electrically contacted by probes for test measurements.

[0063] Following front-end processing 11, back-end processing 12 occurs, in which the wafer is diced into discrete chips along aligned die dicing paths between aligned dies 112, and the chips are packaged. Further testing of the produced semiconductor structure may occur during back-end processing.

[0064] As will be understood from the foregoing, metrology and wafer inspection can rely on precise wafer alignment: because the FOV of the imaging modality used as part of metrology is defined in the stage coordinate system 191, it is important to precisely align the wafer coordinate system 192 and (if necessary) any bare die coordinate system 193 to the stage coordinate system. This facilitates the accurate identification of defect locations, which can help, for example, identify the pass / fail status of individual wafers, or may also help identify the root cause of associated defects. The techniques described herein facilitate such precise wafer alignment. Further details regarding precise wafer alignment will be illustrated below with accompanying figures.

[0065] Figure 4 System 30 is illustrated. System 30 can be used for wafer alignment according to various paradigms. System 30 includes a processing device 31, an image acquisition device 32, and a stage control device 33. Each of the processing device 31, the image acquisition device 32, and the stage control device 33 includes a corresponding communication interface 901, 911, 921, and can communicate with each other through the communication interfaces 901, 911, 921.

[0066] Despite Figure 4 The example illustrates a scenario where a single image acquisition device 32 is used, but sometimes multiple image acquisition devices may be used.

[0067] Image acquisition device 32 may be an optical image acquisition device using short-wavelength light, such as for spectrometry; an X-ray metrology device using X-rays, such as for X-ray transmission or diffraction microscopy; or a device using charged particles, such as for scanning electron microscopy or for focusing ion beam microscopy using electrons or other charged particles (such as gallium or helium ions). These devices using charged particles are also collectively referred to as charged particle microscopes. One particular implementation of a charged particle microscope is a mSEM. Hereinafter, the technology will be described in conjunction with the implementation of image acquisition device 32 as an mSEM. mSEM provides a sufficiently high pixel density (i.e., high resolution) to capture minimal relevant details, such as the smallest defects or deviations appearing from semiconductor structure 113. On the other hand, mSEM provides a sufficiently large FOV to capture the spatial background of individual structures, such as by capturing multiple semiconductor structures 113, or important segments / regions of bare core 112, or multiple positioning markers. Figure 4 Example of the optical component 912 of mSEM 32.

[0068] The stage control unit 33 includes a motor 922, which can be used, for example, to reposition the stage 90 along the principal lateral axis of the stage coordinate system 191. The positioning accuracy is in the sub-micron range.

[0069] Processing device 31 includes a processor 902 and a memory 903, which together form a control circuit. For example, the control circuit can transmit control data to stage control device 33 to control stage 90 to reposition wafer 100. The control circuit of processing device 31 can also receive images from the optical components 912 of mSEM 32. For example, the control circuit can perform feature recognition on pairs of features included in such images. The control circuit can be configured to perform wafer alignment by aligning wafer coordinate system 192 to stage coordinate system 191, and, if necessary, align one or more of the bare core coordinate systems 193 to stage coordinate system 191. Then, if a location on wafer 100 (such as a semiconductor structure 113) is about to be positioned within the FOV of a given imaging modality for wafer inspection, the control circuit can calculate the required displacement in stage coordinate system 191 based on the relevant locations in wafer coordinate system 192 and / or the respective bare core coordinate systems 193. Appropriate control data can then be transmitted to motor 922 of stage control device 33.

[0070] For detailed information about the features of System 30, please refer to the following sections. Figure 5 Explanation.

[0071] Figure 5 It is a flowchart based on various paradigms. For example, Figure 5 The method may be executed through the control circuitry of the processing device 31. For example, Figure 5The method may be executed by processor 902 after the program code is loaded from memory 903.

[0072] In grid 1001, a wafer loading check is performed. For example, this may include checking whether the loading dock is closed and whether the wafer 100 is properly attached to the stage 90. Grid 1001 may also include initializing the stage 90, for example by positioning the stage 90 in an initial positioning defined within the stage coordinate system 191.

[0073] When executing grid 1001, the wafer coordinate system 192 is not aligned with the stage coordinate system 191. Therefore, the known accuracy of centering the FOV of the mSEM 32 on the wafer 100 is very low, i.e., less than the magnitude of the typical structural size of the semiconductor structure 113. Typically, alignment accuracy without a specific wafer alignment process (i.e., mechanical alignment when attaching the wafer 100 to the stage 90) is less than 100 micrometers and is limited by manual loading / unloading accuracy or the accuracy of the loading tools.

[0074] In grid 1002, an optical microscope is used to identify the recess 201 of the wafer 100. This can be used for coarse alignment, such that the FOV of the mSEM 32 is centered on the saddle point 202 of the recess 201 (in an example, the saddle point 202 is located at...). Figure 6 and Figure 7 example in).

[0075] Accordingly, within grid 1002, an optical microscope may be controlled to capture an optical image of the wafer 100, and then the groove 201 in the optical image may be identified. The stage 90 may then be controlled to laterally shift to a first position based on the identification of the groove and a predefined alignment between the mSEM's FOV and the stage coordinate system 191. The mSEM's FOV may be centered on the saddle point 202 of the groove 201 when the stage 90 is in the first position. For example, a computer-implemented feature recognition algorithm may be used.

[0076] The pre-defined alignment of the mSEM's FOV with the stage coordinate system 191 may be limited to the stage 90 by the fixed mechanical attitude of the mSEM optical component 912.

[0077] Next, in grid 1003, mSEM 32 can be controlled to capture a first image 601 of wafer 100 while stage 90 is in a first position. This first image 601 includes at least a portion of recess 201. In particular, the first image 601 may include / image the saddle point 202 of recess 201.

[0078] Then, saddle point 202 can be used to determine radial axis 205 (see...). Figure 6 and Figure 7Please refer to grid 1004. More generally, the radial axis 205 (intersecting the groove 201 and the center 209 of the wafer 100) can be determined based on the first image captured using mSEM 32.

[0079] For example, the tangent 206 to the groove 201 may be determined based on the saddle point 202, which may then determine the radial axis 205 that will be orthogonal to the tangent 206. The radial axis 205 may also be determined as the axis of symmetry of the groove 201.

[0080] As a general rule, tangent 206 and radial axis 205 may be parallel to the principal axes of wafer coordinate system 192. Therefore, grid 1004 can help determine the orientation of wafer coordinate system 192.

[0081] Once the radial axis 205 is determined, the stage 90 is then controlled in grid 1005 to displace the wafer 100 along this radial axis 205 by half its diameter. The diameter of the wafer 100 can be known a priori. Wafer sizes are typically standardized to, for example, a diameter of 150 mm or 300 mm.

[0082] Furthermore, any offset perpendicular to the radial axis 205 can be compensated at square 1005.

[0083] Then, after traversing along the radial axis 205, the stage 90 is positioned in a second position. While the stage 90 is in the second position, the mSEM 32 is controlled to capture one or more second images 602 of the wafer 100.

[0084] The second image includes a reference positioning of the chip 100. The reference positioning of the chip 100 may correspond to the center 209 of the chip 100 (see [reference image]). Figure 6 and Figure 7 In other examples, the reference location may also have some predetermined offset about center 209. For simplicity, we will assume below that the reference location corresponds to center 209; however, other reference locations may be used in other examples.

[0085] One or more second images 602 include wafer structures disposed at or around a center 209. Examples of such wafer structures include: die dicing lines; positioning marks; corners of semiconductor structures 113, semiconductor dies 112, etc. The relative distance of such wafer structures to the center 209 may be known, for example, from a reference database or design data. Therefore, the center 209 of the wafer 100 in the second image 602 may be determined based on structural identification of the device structures in one or more second images. As a general rule, structural identification is considered to be performed by a computer using an appropriate structural identification algorithm.

[0086] Then, any stretching / skewness of the wafer coordinate system 192 with respect to the stage coordinate system 191 will be determined, for example, based on a comparison between the actual distance between the saddle point 202 and the center 209 and the travel distance of the stage 90.

[0087] Therefore, once the center 209 of wafer 100 is determined (or more specifically, once the positioning of the center 209 in the second image 602 is determined), the wafer coordinate system 192 is registered to the stage coordinate system 191 based on the center 209 and the radial axis 205. For example, rotation between the wafer coordinate system 192 and the stage coordinate system 191 can be determined based on the alignment of the radial axis 205. By comparing the travel distance between the first and second positioning of the stage 90 with the nominal distance between the saddle point 202 and the center 209, any stretching or compression of the distance in the wafer coordinate system 102 relative to the distance in the stage coordinate system 191 can be identified. For example, a transformation matrix can be obtained to convert the wafer coordinate system 192 to the stage coordinate system 191 or vice versa. These are merely a few examples of how to perform registration from the wafer coordinate system 192 to the stage coordinate system 191. Other implementations are conceivable. General techniques for wafer alignment are known and can be reused here.

[0088] Detailed information regarding the decision to center 209 in square 1006, and matching Figure 8 Example. Figure 8 This is a schematic illustration of the wafer 100 at and around center 209. Specifically, adjacent semiconductor dies 112-1 to 112-4 are illustrated. Orthogonal die dicing channels 261 to 262 are located between the adjacent semiconductor dies 112-1 to 112-4. Positioning marks 272 are located between die dicing channels 261 to 262 and semiconductor dies 112-1 to 112-4. Positioning marks 272 may have a repeatable arrangement, such as... Figure 8 As illustrated in the example. The positioning of center 209 in the second image 602 can be determined by: performing structural identification on orthogonal core cut lines 261 to 262, and then identifying the center of the corresponding intersection between orthogonal core cut lines 261 to 262, thereby determining center 209. For example, core cut lines 261 to 262 can be based on the test structure within core cut lines 261 to 262 ( Figure 8 (The test structure is not illustrated in the text) and / or it is identified based on adjacent positioning markers 272.

[0089] Refer again Figure 5As a result of executing grid 1007, wafer alignment is achieved. Sometimes, it may also include registration of one or more die coordinate systems 193 to stage coordinate systems 191. Then, subsequent grids 1008 to 1010 can be executed. Another reason for executing grids 1008 to 1010 is to improve the accuracy of the registration from wafer coordinate system 192 to stage coordinate system 191.

[0090] In grid 1008, one or more other axes of wafer 100 are determined. This may be based on wafer coordinate system 192. Since an initial registration is available (from grid 1007), stage 90 may also be controlled in grid 1009 to traverse along one or more other axes. While traversing along one or more other axes, mSEM 32 is controlled to capture one or more third images 603 (stage 90 may stop while capturing one or more third images 603). Third image 603 includes semiconductor structure 113 of bare die 112. Semiconductor structure 113 may be identified in grid 1010 (i.e., the location of semiconductor structure 113 in third image 603 is determined using structure identification), and then in grid 1011, the bare die coordinate system 193 defined thereunder is registered to stage coordinate system 191. Furthermore, any displacement or translation can be identified by the deviation between (i) the actual distance traveled between the center 209 and the bare cores 112-1 to 112-4 and the semiconductor structure 113 and (ii) the nominal distance (such as that obtained from CAD or a database).

[0091] Detailed information about these other axes is also provided. Figure 8 For example. In particular, Figure 8Examples of a first exemplary implementation of such an additional axis 215 and a second exemplary implementation of such an additional axis 216 are given. The additional axis 215 is a radial axis intersecting the center 209. Axis 215 is aligned with the die dicing 262 and, therefore, orthogonal to the radial axis 205. In another example, an additional axis 216 with an offset 219 compared to axis 215 may also be determined. For example, the offset 219 may be based on the width of the die dicings 261, 262, or more generally on the distance between adjacent semiconductor dies 112-1 to 112-4. The width of the die dicings 261, 262 is associated with the distance between adjacent semiconductor dies 112-1 to 112-4. Accordingly, the FOV 301 of the mSEM 32 may subsequently be aligned with the corner 271 of semiconductor dies 112-1, 112-3 as it travels along the additional axis 216. Therefore, a better coverage of the semiconductor structure 113 within the semiconductor die can be obtained by using the offset axis 216. This is because the FOV 301 of the mSEM is typically on the order of magnitude of the width of the die dicing traces 261, 262, for example, on the order of 60% to 140% of the width of the offset 219. Figure 8 As illustrated in the example, multiple third images may be taken for a plurality of adjacent semiconductor dies 112-1, 112-3 arranged along another axis 215, 216. The repeating semiconductor structure 113 of the adjacent semiconductor dies can then be identified in the multiple third images, for example by comparing the multiple third images with each other. And this can be used for wafer alignment.

[0092] Then, the specific positioning of each die 112-1 to 112-4 can be determined. This can be used to align each die coordinate system 193 to the stage coordinate system 191 and / or to the wafer coordinate system 192. Furthermore, the accuracy of the registration from the wafer coordinate system 192 to the stage coordinate system 191 may be improved.

[0093] In summary, the wafer alignment technique described above has been explained. Pre-alignment using an optical microscope is employed. Subsequent steps associated with wafer alignment do not depend on the use of an optical microscope; instead, mSEM images are used. This technique has the advantage of mitigating the offset caused by the non-uniaxial arrangement of the optical microscope and avoids other imaging modalities such as limited FOV SEM. The technique can be implemented quickly and reliably.

[0094] Although the disclosure has shown and described with respect to certain preferred embodiments, equivalents and modifications will arise upon reading and understanding this specification by those skilled in the art. The invention includes all such equivalents and modifications and is limited only by the scope of the appended claims.

[0095] As an example, although some implementations have been illustrated with respect to automated feature recognition, in some examples, feature recognition may be performed manually.

Claims

1. A method for wafer alignment, comprising: Control the multi-scan electron microscope (32) to capture a first image (601) of a wafer (100) attached to the electric loading stage (90) while the electric loading stage (90) is in a first position, the first image (601) including at least a portion of the groove (201) of the wafer (100); The radial axis (205) of the wafer (100) is determined based on the first image (601). Control the electric loading and unloading stage (90) to displace the wafer (100) along the radial axis (205) by half the diameter of the wafer (100) so that the electric loading and unloading stage (90) is in a second position; The multi-scan electron microscope (32) is controlled to capture a second image (602) of the wafer (100) while the motorized loading stage (90) is in the second position. The second image includes the wafer structure (112, 112-1 – 112-4, 113, 261, 262, 272). Based on the structural identification of the wafer structure (112, 112-1 – 112-4, 113, 261, 262, 272) of the second image (602), the reference positioning (209) of the wafer (100) is determined; and Based on the reference positioning (209) and the radial axis (205), the wafer coordinate system (192) of the wafer (100) is registered to the stage coordinate system (191) of the electric loading and unloading stage (90).

2. The method of claim 1, wherein the wafer structure identified by the structure comprises orthogonal die cut channels (261, 262) between adjacent semiconductor dies (112, 112-1 – 112-4).

3. The method of claim 1 or 2, wherein: The wafer (100) comprises an array of semiconductor dies (112, 112-1 – 112-4); and This method further includes: Determine one or more of the other axes (215, 216) of the wafer (100). Control the electric loading / unloading platform (90) to move laterally along one or more of the other axes (215, 216); The multi-scan electron microscope (32) is controlled to capture one or more third images (603) while traversing along one or more other axes (215, 216), the one or more third images (603) containing the semiconductor structure (113) of the semiconductor bare die of the array. Based on the identification of another structure in one or more third images (603), the semiconductor structure (113) is determined; and Based on this further structural identification, the bare core coordinate system (193) of the semiconductor bare core (112, 112-1 – 112-4) is registered to the stage coordinate system (191).

4. The method of claim 3, wherein the one or more other axes comprise an axis (216) having an offset (219) about the central radial axis (215).

5. The method of claim 4, wherein the offset (219) is determined based on the width of the dicing paths (261, 262) between adjacent semiconductor dies (112, 112-1 – 112-4) of the array.

6. The method of claim 4, wherein the field of view (301) of the multi-scan electron microscope (32) is 60% to 140% of the offset (219).

7. The method of claim 4, wherein: Multiple third images (603) are captured for multiple adjacent semiconductor dies (112, 112-1 – 112-4) of the array that are adjacent to each other along one or more other axes (215, 216); and The semiconductor structure (113) in the plurality of third images (603) is determined by comparing them with each other.

8. The method of claim 1 or 2, wherein: The first image (601) includes the saddle point (202) of the groove (201). The radial axis (205) of the wafer (100) is determined based on the saddle point (202).

9. The method of claim 1 or 2, further comprising: Control the optical microscope to capture an optical image of the wafer (100); Identify the groove (201) in the optical image; and The electric loading and unloading stage (90) is controlled to move laterally to the first position based on the identification of the groove (201) and the predefined alignment of the field of view of the multi-scan electron microscope with the stage coordinate system (191).

10. A processing apparatus (31) including control circuitry (902, 903) and configured to: Control the multi-scan electron microscope (32) to capture a first image (601) of a wafer (100) attached to the electric loading stage (90) while the electric loading stage (90) is in a first position, the first image (601) including at least a portion of the groove (201) of the wafer (100); The radial axis (205) of the wafer (100) is determined based on the first image (601). Control the electric loading and unloading stage (90) to displace the wafer (100) along the radial axis (205) by half the diameter of the wafer (100) so that the electric loading and unloading stage (90) is in a second position; The multi-scan electron microscope (32) is controlled to capture a second image (602) of the wafer (100) while the motorized loading stage (90) is in the second position. The second image includes the wafer structure (112, 112-1 – 112-4, 113, 261, 262, 272). Based on the structural identification of the wafer structure (112, 112-1 – 112-4, 113, 261, 262, 272) of the second image (602), the reference positioning (209) of the wafer (100) is determined; and Based on the reference positioning (209) and the radial axis (205), the wafer coordinate system (192) of the wafer (100) is registered to the stage coordinate system (191) of the electric loading and unloading stage (90).

11. The processing apparatus (31) of claim 10, wherein the control circuit (902, 903) is configured to perform the method of any one of claims 1 to 9.

12. A system (30) for wafer alignment, comprising the processing apparatus (31) as claimed in claim 10 or 11 and a multi-scan electron microscope (32).

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