Manufacturing method of PCIE golden finger and electroplating lead structure

Abstract

The application provides a manufacturing method of a PCIE golden finger and an electroplating lead structure. The method comprises: arranging the golden finger on a PCB board, wherein the golden finger comprises a ground network golden finger and a non-ground network golden finger; connecting the ground network golden finger with a ground hole located on a first side of the ground network golden finger; arranging a first electroplating bus on the PCB board, wherein the first electroplating bus transversely connects all the ground holes on the first side of the golden finger together and extends out of a second side edge and / or a third side edge of the PCB board; arranging a first electroplating branch on the PCB board, wherein the first electroplating branch connects the non-ground network golden finger in the golden finger to the first electroplating bus; electroplating the golden finger by using the first electroplating bus and the first electroplating branch; and drilling a hole on the first electroplating branch to cut off the connection between the non-ground network golden finger and the first electroplating bus after the electroplating is completed. The manufacturing process of the golden finger is simple and the residual lead on the PCB board is less.

Description

Technical Field

[0001] This invention belongs to the field of electronic devices, specifically relating to a method for manufacturing PCIe gold fingers and an electroplating lead structure. Background Technology

[0002] This section is intended to provide background or context for embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] Gold fingers (connecting fingers) refer to numerous conductive copper plates fabricated on the top and bottom surfaces of a PCB. Their arrangement resembles fingers, hence the name "gold fingers." They are used to connect components such as memory modules and graphics cards to their slots. To improve the oxidation resistance and reduce contact resistance, a layer of gold is electroplated onto the copper plates. To achieve this gold plating, a conductive wire needs to be designed on the gold finger, extending to the edge of the board. Current is applied to this wire to achieve the gold plating. However, this designed wire needs to be removed after plating to avoid affecting the appearance or the quality of high-speed signals.

[0004] In existing technologies, electroplated lead structures are typically quite long, and residual leads on the gold fingers are usually removed using chemical etching or mechanical grinding. However, mechanical grinding is not effective in removing residual leads from shorter gold fingers, such as those in PCIe Gen 5, while chemical etching for removing residual leads is a complex and expensive process.

[0005] Therefore, designing a simple electroplated lead structure with shorter length and a simple manufacturing method for PCIE gold fingers is an urgent problem to be solved. Summary of the Invention

[0006] To address the problems existing in the prior art, a manufacturing method for PCIE gold fingers and an electroplating lead structure are proposed. This method and structure can solve the aforementioned problems.

[0007] The present invention provides the following solutions.

[0008] In a first aspect, a method for manufacturing PCIe gold fingers is provided. The gold fingers are disposed on a PCB board and include ground network gold fingers and non-ground network gold fingers. The method includes: connecting the ground network gold fingers to ground vias located on a first side thereof; providing a first electroplating bus on the PCB board, the first electroplating bus laterally connecting all ground vias located on the first side of the gold fingers together and laterally extending to a second side edge and / or a third side edge of the PCB board, wherein the second side edge and the third side edge are opposite sides of the PCB board; providing a first electroplating branch on the PCB board, the first electroplating branch connecting one or more non-ground network gold fingers to the first electroplating bus; electroplating the gold fingers using the first electroplating bus and the first electroplating branch; and, after electroplating is completed, drilling holes in the first electroplating branch to sever the connection between the non-ground network gold fingers and the first electroplating bus.

[0009] In one embodiment, the first electroplating bus is formed as an integral metal sheet; or, the first electroplating bus is formed as a separate metal sheet, the separate metal sheet including: a plurality of intermediate metal sheets disposed between adjacent ground holes, a second side metal sheet extending from the ground holes to the second edge of the PCB board and / or a third side metal sheet extending from the ground holes to the third edge of the PCB board.

[0010] In one embodiment, the first electroplating branch is formed as a lead that extends from one or more non-ground network gold fingers in a first direction and is connected to the first electroplating bus.

[0011] In one embodiment, a hole is drilled on the first electroplated branch near the non-ground network gold finger.

[0012] In one embodiment, the PCIe gold fingers include: PCIe GEN5 gold fingers and / or PCIe GEN6 gold fingers.

[0013] In a second aspect, a method for manufacturing PCIe gold fingers is provided. The gold fingers are disposed on a PCB board and include ground network gold fingers and non-ground network gold fingers. The method includes: connecting the ground network gold fingers to a ground via located on a first side thereof; providing a second electroplating bus on the PCB board, the second electroplating bus including at least: a second-side electroplating bus extending from one or more ground vias on the first side of the gold fingers out of a second side edge of the PCB board, and / or a third-side electroplating bus extending from one or more ground vias on the first side of the gold fingers out of a third side edge of the PCB board, wherein the second side edge and the third side edge are opposite sides of the PCB board; providing a second electroplating branch on the PCB board, the second electroplating branch connecting the non-ground network gold fingers to ground vias adjacent to the non-ground network gold fingers, so that the non-ground network gold fingers are electrically connected to the second-side electroplating bus and / or the third-side electroplating bus; electroplating the gold fingers using the second electroplating bus and the second electroplating branch; and, after electroplating is completed, drilling holes in the second electroplating branch to sever the electrical connection between the non-ground network gold fingers and the second electroplating bus.

[0014] In one embodiment, the second electroplating branch includes: a bent lead from the non-ground network gold finger to a first adjacent ground via adjacent thereto, and / or a bent lead from the non-ground network gold finger to a second adjacent ground via adjacent thereto; the first adjacent ground via is closer to a first side edge of the PCB board relative to the non-ground network gold finger, and the second adjacent ground via is closer to a second side edge of the PCB board relative to the non-ground network gold finger.

[0015] In one embodiment, a hole is drilled on the second electroplated branch near the non-ground network gold finger.

[0016] In one embodiment, the PCIe gold fingers include: PCIe GEN5 gold fingers, and / or PCIe GEN6 gold fingers.

[0017] Thirdly, a plating lead structure for PCIe gold fingers is provided. The gold fingers include ground network gold fingers and non-ground network gold fingers disposed on a PCB board. The ground network gold fingers are connected to ground vias located on a first side thereof. The plating lead structure includes a first plating bus and a first plating branch disposed on the PCB board. The first plating bus connects all ground vias on the first side of the gold fingers together and extends to a second side edge and / or a third side edge of the PCB board, wherein the second side edge and the third side edge are opposite side edges of the PCB board. The first plating branch connects one or more non-ground network gold fingers to the first plating bus.

[0018] In one embodiment, after electroplating is completed, a cut-off structure for severing the connection between the non-ground network gold finger and the first electroplating bus is provided on the first electroplating branch line near the non-ground network gold finger.

[0019] In one embodiment, the truncated structure includes a hole structure.

[0020] In one embodiment, the first electroplating bus is formed as an integral metal sheet; or, the first electroplating bus is formed as a separate metal sheet, the separate metal sheet comprising: an intermediate section metal sheet between adjacent ground holes, a second side metal sheet extending from one or more ground holes on the first side of the gold finger to the second side edge of the PCB board, and / or a third side metal sheet extending from one or more ground holes on the first side of the gold finger to the third side edge of the PCB board.

[0021] In one embodiment, the first electroplating branch includes a lead extending from the non-ground network gold finger in a first direction and connected to the first electroplating bus.

[0022] In one embodiment, the PCIe gold fingers include: PCIe GEN5 gold fingers and / or PCIe GEN6 gold fingers.

[0023] Fourthly, a plating lead structure for a PCIe gold finger is provided, characterized in that the gold finger includes a ground network gold finger and a non-ground network gold finger disposed on a PCB board, the ground network gold finger being connected to a ground via located on its first side; the plating lead structure includes: a second plating bus and a second plating branch disposed on the PCB board; wherein the second plating bus includes at least: a second-side plating bus extending from one or more ground vias on the first side of the gold finger out of a second side edge of the PCB board, and / or a third-side plating bus extending from one or more ground vias on the first side of the gold finger out of a third side edge of the PCB board, wherein the second side edge and the third side edge are opposite side edges of the PCB board; and the second plating branch connects the non-ground network gold finger to one or more adjacent ground vias, so that the non-ground network gold finger is electrically connected to the second-side plating bus and / or the third-side plating bus.

[0024] In one embodiment, after electroplating is completed, a cutting-off structure is provided on the second electroplating branch near the non-ground network gold finger to cut off the electrical connection between the non-ground network gold finger and the second electroplating bus.

[0025] In one embodiment, the cut-off structure is a hole structure.

[0026] In one embodiment, the second electroplating branch includes: a bent lead from the non-ground network gold finger to a second adjacent ground hole adjacent thereto, and / or a bent lead from the non-ground network gold finger to a first adjacent ground hole adjacent thereto, the first adjacent ground hole being closer to a first side edge of the PCB board relative to the non-ground network gold finger (12), and the second adjacent ground hole being closer to a second side edge of the PCB board relative to the non-ground network gold finger (12).

[0027] In one embodiment, the PCIe gold fingers include: PCIe GEN5 gold fingers and / or PCIe GEN6 gold fingers.

[0028] Fifthly, a PCIe gold finger is provided, comprising: a PCIe gold finger obtained by processing using the method of the first or second aspect.

[0029] One of the advantages of the above-described embodiment of the electroplated lead structure for PCIe gold fingers is that the structure of the electroplated lead structure set on the PCB board is simple and the lead is short. Therefore, the amount of work and difficulty required for subsequent cutting or removing of the lead is also less, and it is easier to avoid the performance of the high-speed signal carried by the gold fingers being affected by too many residual leads.

[0030] One of the advantages of the above-described PCIe gold finger manufacturing method is that the electroplated lead structure on the PCB board is simple and the leads are short. Therefore, the electrical connection between the non-ground network gold finger and the ground hole can be cut off by a simple drilling process, and fewer residual leads are left on the PCB board, thus avoiding the performance of the high-speed signal carried by the gold finger being affected by too many residual leads.

[0031] Other advantages of the present invention will be explained in more detail below with reference to the accompanying drawings.

[0032] It should be understood that the above description is merely an overview of the technical solution of the present invention, so as to enable a clearer understanding of the technical means of the present invention, and thus to implement it in accordance with the contents of the specification. To make the above and other objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are illustrated below. Attached Figure Description

[0033] By reading the detailed description of the exemplary embodiments below, those skilled in the art will understand the advantages and benefits of this document, as well as other advantages and benefits. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0034] Figure 1 This is a schematic diagram of the structure of a PCIe gold finger;

[0035] Figure 2 This is a schematic diagram of the electroplated lead structure of a PCIe gold finger according to the prior art;

[0036] Figure 3 This is a schematic diagram of the electroplated lead structure of a PCIE gold finger according to an embodiment of the present invention;

[0037] Figure 4This is a schematic diagram of the structure of the electroplated lead structure of a PCIE gold finger according to an embodiment of the present invention after drilling.

[0038] Figure 5 This is a schematic diagram of the electroplated lead structure of a PCIE gold finger according to another embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram of the structure of the electroplated lead structure of the PCIE gold finger after drilling, according to another embodiment of the present invention.

[0040] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0041] The symbols in the attached diagram are briefly explained as follows:

[0042] Ground network gold finger-11; Non-ground network gold finger-12; Ground via-13; Lead-1'; Copper sheet-14; Third side edge of PCB board-15; First electroplating bus-31; First electroplating branch-32; Hole-33; Second electroplating bus-51; Third side electroplating bus-511; Second electroplating branch-52; First adjacent ground via-131; Second adjacent ground via-132; Hole-53. Specific Implementation

[0043] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0044] In the description of the embodiments of this application, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, numbers, steps, behaviors, components, portions or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence of one or more other features, numbers, steps, behaviors, components, portions or combinations thereof.

[0045] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.

[0046] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0047] To clearly illustrate the embodiments of this application, some concepts that may appear in subsequent embodiments will be introduced first.

[0048] Concept Description

[0049] PCIe (Peripheral Component Interconnect Express) is an abbreviation for a high-speed serial computer expansion bus standard. PCIe Gen 5 refers to the 5th generation of PCIe technology, and PCIe Gen 6 refers to the 6th generation of PCIe technology.

[0050] Gold fingers (connecting fingers) refer to numerous conductive copper plates fabricated on the top and bottom surfaces of a PCB. They are called gold fingers because their arrangement resembles fingers, and are used to connect components such as memory modules and graphics cards to their slots. To improve the gold fingers' oxidation resistance and reduce contact resistance, a layer of gold is electroplated onto the surface of the copper plates.

[0051] Figure 1 This illustrates an existing PCIe gold finger design architecture. It is understandable that... Figure 1 The PCIe gold finger architecture shown can be the gold finger architecture specified in PCIe Gen 5, or the gold finger architecture specified in PCIe Gen 6 and later versions, as long as it has similar characteristics to, etc. Figure 1 The gold finger architecture shown is sufficient; this application does not impose any specific limitations on it.

[0052] First, see Figure 1 The gold finger design includes multiple ground network gold fingers 11 and multiple non-ground network gold fingers 12. Multiple ground holes 13 are provided on the first side of the entire gold finger. Each ground network gold finger 11 has two ground holes 13 on its first side, and multiple independent ground holes 13 are also provided. The lengths of the ground network gold fingers 11 and the non-ground network gold fingers 12 are not the same. Therefore, on the first side of the gold finger, the ground network gold fingers 101 and the non-ground network gold fingers 102 are uneven in depth.

[0053] exist Figure 1 In this example, the lower side of the diagram is used as the "first side," but it is not limited to this. It can be understood that the "first side" in this embodiment specifically refers to one side of the gold finger along its length.

[0054] It's understandable that to achieve gold finger plating, a wire needs to be designed on the gold finger extending to the edge of the board, and this wire needs to be treated with anti-plating agents. Current is then applied to the wire to achieve gold plating. However, this designed wire needs to be removed after plating to avoid affecting the appearance or the quality of high-speed signals.

[0055] refer to Figure 2 The existing technology employs the following method for electroplating gold and removing residual leads: First, an electroplated lead 1' is fabricated on the gold finger. The electroplated lead extends from below each gold finger and is connected laterally. Then, the lead undergoes an anti-electroplating treatment, and the fabricated electroplated lead is then electroplated onto the gold finger. Finally, residual leads on the PCIe gold finger can be removed using chemical etching or mechanical grinding.

[0056] However, the aforementioned electroplated lead 1' is very long, which causes inconvenience for subsequent lead cutting or removal. Furthermore, since all non-ground network fingers in PCIe gold fingers designed according to the PCIe GEN5 protocol are shorter than the ground network fingers, it is impossible to effectively remove the lead residue of short gold fingers using a beveling machine. Chemical etching to remove residual leads is a complex and expensive process.

[0057] In order to at least partially solve one or more of the above-mentioned problems and other potential problems, exemplary embodiments of this disclosure provide a method for manufacturing PCIe gold fingers and an electroplated lead structure.

[0058] In this way, by changing the design of the gold finger electroplating leads and using a drilling method, a simple electroplating process for PCIE gold fingers is provided to manufacture PCIE gold fingers, with fewer residual leads on the PCB board.

[0059] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0060] Figure 3 This embodiment illustrates an electroplated lead structure for a PCIe gold finger; Figure 4 This embodiment illustrates the use of... Figure 3 The structure after drilling the electroplated lead structure of the PCIe gold fingers.

[0061] The following combination Figure 3 and Figure 4 The embodiments of this application will be explained in detail.

[0062] refer to Figure 3The PCB board features PCIe gold fingers, which include multiple ground network gold fingers 11 and multiple non-ground network gold fingers 12. Multiple ground vias 13 are provided on the first side of each gold finger. Each ground network gold finger 11 has two ground vias 13 on its first side, and each non-ground network gold finger 12 also has an independent ground via 13 on its first side. Figure 3 , 4 The lower side of the gold finger is described as an example of the first side, but it is not limited to this. In this embodiment, the first side can refer to one side of the gold finger in its length direction.

[0063] To construct the electroplated lead structure, firstly, the ground network gold fingers 11 are connected to the ground vias 13 located on their first side, specifically through copper plates 14. Then, a first electroplating bus 31 is provided on the PCB board, which laterally connects all the ground vias 13 on the first side of the gold fingers and extends beyond the second (not shown) and / or third edge 15 of the PCB board. The portion extending beyond the second or third edge is used to connect external electroplated conductors, and the second and third edges are opposite sides of the PCB board. Next, a first electroplating branch line 32 is provided on the PCB board, connecting each non-ground network gold finger 12 to the first electroplating bus 31.

[0064] This completes the electroplated lead structure. It can be seen that in this electroplated lead structure, the first electroplated bus 31 is electrically connected to all the non-ground network gold fingers 12 through the first electroplated branch 32. Furthermore, compared to existing solutions, Figure 3 The electroplating structure constructed in the proposed scheme has fewer leads and a simpler structure.

[0065] Then, the actual gold plating process is performed, using the first plating bus 31 and the first plating branch 32 to plating the gold fingers. Specifically, current can be introduced from the portion of the first plating bus 31 extending out of the edge of the PCB board, thereby achieving gold plating on the gold fingers.

[0066] refer to Figure 4 After electroplating is completed, holes 33 are drilled directly on the first electroplating branch 32 to cut off the connection between each non-ground network gold finger 12 and the first electroplating bus 31.

[0067] Therefore, by constructing such Figure 3 The gold finger electroplated lead structure shown can disconnect the electrical connection between the non-ground network gold finger and the ground network using only a simple process of drilling, while leaving fewer residual leads on the PCB board.

[0068] It can be understood that the aforementioned first electroplating bus 31 refers to the combination of conductive structures that connect all the ground holes 13 on the first side of the gold finger together.

[0069] In one embodiment, reference is made to... Figure 3 The first electroplating bus 31 is formed as a split metal sheet, which includes: a plurality of intermediate metal segments mounted between adjacent ground holes on the first side of the gold finger, a second side metal sheet extending from the ground hole on the first side of the gold finger to the second side edge of the PCB board, and a third side metal sheet extending from the ground hole on the first side of the gold finger to the third side edge of the PCB board.

[0070] As an alternative, in some embodiments, the first electroplated bus can also be formed as a single metal sheet, with its two ends extending from the second and / or third side edges of the PCB board, and its middle portion can simultaneously connect each ground hole 13 on the first side of the gold fingers. This application does not impose specific limitations in this regard.

[0071] In one embodiment, the first electroplating branch 32 includes leads extending from one or more non-ground network gold fingers 12 in a first direction and connected to the first electroplating bus, for example, in Figure 3 In this configuration, the first electroplating branch 32 is a combination of multiple parallel conductors. The aforementioned first direction refers to the direction from the non-ground network gold finger toward the first side.

[0072] In one embodiment, a hole 33 can be drilled on the first electroplated branch 32 near the non-ground network gold finger 12. Specifically, the hole is drilled as close to the gold finger as possible without damaging it, which can improve the quality of high-speed signals.

[0073] In one embodiment, the PCIe gold finger is a PCIe Gen5 gold finger, a PCIe Gen5 gold finger, or an upgraded version of the PCIe gold finger with the same or similar gold finger architecture. This application does not specifically limit it in this regard.

[0074] Figure 5 This embodiment shows another electroplated lead structure for the PCIe gold finger; Figure 6 This embodiment illustrates the use of... Figure 5 The structure of the electroplated lead wires of the PCIe gold fingers after drilling.

[0075] The following combination Figure 5 and Figure 6 The embodiments of this application will be explained in detail.

[0076] refer to Figure 5The PCB board features PCIe gold fingers, which include multiple ground network gold fingers 11 and multiple non-ground network gold fingers 12. Multiple ground vias 13 are provided on the first side of each gold finger. Each ground network gold finger 11 has two ground vias 13 on its first side, and each non-ground network gold finger also has an independent ground via 13 on its first side. Figure 5 , 6 The lower side of the gold finger is described as an example of the first side, but it is not limited to this. In this embodiment, the first side can refer to one side of the gold finger along its length. To construct the electroplating lead structure, firstly, the ground network gold finger 11 is connected to the ground hole 13 on its first side, specifically through a copper sheet 14; a second electroplating bus 51 is provided on the PCB board, the second electroplating bus 51 including at least: a second-side electroplating bus (not shown) extending from one or more ground holes 13 on the first side of the gold finger out of the second side edge of the PCB board, and / or a third-side electroplating bus 511 extending from one or more ground holes 13 on the first side of the gold finger out of the third side edge 15 of the PCB board. Furthermore, the portions of the second-side electroplating bus (not shown) and the third-side electroplating bus 511 extending out of the PCB board are used for conductivity during subsequent gold plating.

[0077] Then, a second electroplating branch line 52 is provided on the PCB board. The second electroplating branch line 52 connects the non-ground network gold finger 12 to the ground via 13 adjacent to the non-ground network gold finger 12, so that the non-ground network gold finger 12 is electrically connected to the second-side electroplating bus and / or the third-side electroplating bus.

[0078] Specifically, the second electroplating branch 52 can connect the non-ground network gold finger 12 in the gold finger to the first adjacent ground hole and / or the second adjacent ground hole adjacent to it, so that the non-ground network gold finger is electrically connected to the second side electroplating bus and / or the third side electroplating bus.

[0079] For example, targeting Figure 5 A non-ground network gold finger 12 has adjacent first adjacent ground vias 131 and second adjacent ground vias 132. A second electroplating branch line 52 can simultaneously connect the non-ground network gold finger 12 and its adjacent first adjacent ground vias 131 and second adjacent ground vias 132. It can be understood that if each non-ground network gold finger 12 is simultaneously connected to its adjacent first adjacent ground via and / or second adjacent ground via through the second electroplating branch line 52, then... Figure 5 The electroplated lead structure shown is similar to Figure 3 The electroplated lead structure shown has the same electrical connection effect.

[0080] However, in this embodiment, the second electroplating branch line 52 connects the non-ground network gold finger 12 and the ground via 13 in three ways, as shown in Figures a, b, and c. Specifically, a: the non-ground network gold finger 12 is connected to the second adjacent ground via 132 via the second electroplating branch line 52; b: the non-ground network gold finger 12 is connected to the first adjacent ground via 131 via the second electroplating branch line 52; and c: the non-ground network gold finger 12 is simultaneously connected to both the second adjacent ground via 132 and the first adjacent ground via 131 via the second electroplating branch line 52. Any method can be chosen according to the actual situation, as long as it ensures that any non-ground network gold finger 12 can achieve electrical conduction with the second-side electroplating bus (not shown) and / or the third-side electroplating bus 511.

[0081] This completes the electroplated lead structure. It can be seen that in this electroplated lead structure, the second electroplated bus 51 is electrically connected to all the non-ground network gold fingers 12 through the second electroplated branch 52. Furthermore, compared to existing solutions, Figure 5 The electroplated leads in the proposed solution are shorter in length and have a simpler structure.

[0082] Then, the actual gold plating process is performed, using the second plating bus 51 and the second plating branch 52 to plating the gold fingers. Specifically, current can be introduced from a portion of the second-side plating bus (not shown) and / or the third-side plating bus 511 extending out of the PCB board, thereby enabling the gold plating of the gold fingers.

[0083] refer to Figure 6 After electroplating is completed, a hole 53 is drilled directly on the second electroplating branch 52 to cut off the electrical connection between the non-ground network gold finger 12 and the second electroplating bus 51.

[0084] Therefore, by changing the structure of the gold finger electroplating leads, it is possible to disconnect the electrical connection between the non-ground network gold finger and the ground network using only a simple drilling process, thus completing the electroplating process of the PCIe gold finger, while leaving fewer residual leads on the PCB board.

[0085] In one embodiment, reference is made to... Figure 5 The second electroplating branch 52 includes: bent leads connecting one or more non-ground network gold fingers 12 to adjacent second adjacent ground vias, and / or bent leads connecting one or more non-ground network gold fingers to adjacent first adjacent ground vias 131. The first adjacent ground via 131 is located near a first side edge of the PCB board relative to the non-ground network gold fingers 12, and the second adjacent ground via 132 is located near a second side edge of the PCB board relative to the non-ground network gold fingers 12.

[0086] Specifically, before performing the actual electroplating gold work, anti-electroplating treatment can also be performed on the second electroplating bus 51 and the second electroplating branch 52.

[0087] In one embodiment, a hole can be drilled on the second electroplated branch 52 near the non-ground network gold finger. Specifically, the hole is drilled as close to the gold finger as possible without damaging it, which improves high-speed signal quality.

[0088] refer to Figure 3 Based on the same or similar technical concept, embodiments of the present invention also provide an electroplated lead structure for PCIE gold fingers.

[0089] The gold fingers include a ground network gold finger 11 and a non-ground network gold finger 12 disposed on the PCB board. The ground network gold finger 11 is connected to the ground hole 13 located on its first side, specifically through a copper sheet 14. The first side can be one side of the gold finger in its length direction.

[0090] The electroplating lead structure includes: a first electroplating bus 31 and a first electroplating branch line 32 disposed on the PCB board; the first electroplating bus 31 connects all the ground holes 13 on the first side of the gold fingers together and extends out of the second side edge and / or the third side edge 15 of the PCB board; the first electroplating branch line 32 connects one or more non-ground network gold fingers 12 among the gold fingers to the first electroplating bus 31.

[0091] It is understandable that the aforementioned electroplated lead structure is simple in design and has fewer leads, which is beneficial for lead processing after electroplating. For example, as mentioned above, lead processing after electroplating can be completed using only drilling. This lead structure is particularly suitable for the gold finger structure of PCIe Gen5 and PCIe Gen6.

[0092] In one embodiment, when electroplating is completed, a cut-off structure is provided on the first electroplating branch 32 near the non-ground network gold finger 12 to cut off the connection between the non-ground network gold finger 12 and the first electroplating bus 31.

[0093] In one embodiment, the cut-off structure is a hole 33 structure.

[0094] In one embodiment, the first electroplating bus 31 is formed as a single metal sheet; or, the first electroplating bus 31 is formed as a separate metal sheet, the separate metal sheet including: a plurality of intermediate metal sheets disposed between adjacent ground holes 13 on the first side of the gold finger, a second side metal sheet extending from the ground hole on the first side of the gold finger to the second side edge of the PCB board, and / or a third side metal sheet extending from the ground hole on the first side of the gold finger to the third side edge of the PCB board.

[0095] In one embodiment, the first electroplating branch 32 includes a lead extending from the non-ground network gold finger 12 in a first direction and connected to the first electroplating bus 31. The first direction is the direction from the non-ground network gold finger toward its first side.

[0096] In one embodiment, the PCIe gold fingers include: PCIe GEN5 gold fingers, PCIe GEN6 gold fingers, or other versions of PCIe gold fingers with the same or similar structure.

[0097] refer to Figure 5 Based on the same technical concept, embodiments of the present invention also provide another electroplated lead structure for PCIE gold fingers.

[0098] The gold fingers include ground network gold fingers 11 and non-ground network gold fingers 12 disposed on the PCB board. The ground network gold fingers 11 are connected to the ground hole 13 located on its first side, specifically through a copper sheet 14.

[0099] The electroplating lead structure includes: a second electroplating bus 51 and a second electroplating branch line 52 disposed on the PCB board; the second electroplating bus 52 includes at least: a second-side electroplating bus extending one or more ground holes on the first side of the gold fingers out of the second side edge of the PCB board, and / or a third-side electroplating bus extending one or more ground holes on the first side of the gold fingers out of the third side edge of the PCB board; and the second electroplating branch line connects one or more non-ground network gold fingers 12 in the gold fingers to adjacent ground holes, so that the non-ground network gold fingers 12 are electrically connected to the second-side electroplating bus and / or the third-side electroplating bus.

[0100] It is understandable that the aforementioned electroplated lead structure is simple in structure and has fewer leads, which is beneficial for lead processing after electroplating. For example, as mentioned above, lead processing after electroplating can be completed using only drilling. This lead structure is particularly suitable for gold finger structures such as PCIe Gen5 and PCIe Gen6.

[0101] In one embodiment, when electroplating is completed, a cut-off structure is provided on the second electroplating branch 52 near the non-ground network gold finger 12 to cut off the connection between the non-ground network gold finger 12 and the second electroplating bus 51.

[0102] In one embodiment, the cut-off structure is a hole 53 structure.

[0103] In one embodiment, the second electroplating branch 52 includes: bent leads respectively connected from one or more non-ground network gold fingers 12 to adjacent second adjacent ground holes, and / or bent leads respectively connected from one or more non-ground network gold fingers 12 to adjacent first adjacent ground holes, the first adjacent ground holes being closer to a first side edge of the PCB board relative to the non-ground network gold fingers 12, and the second adjacent ground holes being closer to a second side edge of the PCB board relative to the non-ground network gold fingers 12.

[0104] In one embodiment, the PCIe gold fingers include: PCIe Gen5 gold fingers, PCIe Gen6 gold fingers, and similar PCIe gold fingers in subsequent PCIe versions. Based on the same technical concept, embodiments of the present invention also provide a PCIe gold finger, comprising: a PCIe gold finger obtained by processing using any of the methods described above.

[0105] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined to achieve benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a PCIE golden finger, characterized in that, The gold finger is arranged on a PCB board, the gold finger includes a ground network gold finger (11) and a non-ground network gold finger (12), the method comprises: connecting the ground network gold finger (11) with a ground hole (13) located on the first side thereof; arranging a first electroplating bus (31) on the PCB board, the first electroplating bus (31) transversely connects all ground holes (13) located on the first side of the gold finger together and extends out of the second side edge and / or the third side edge of the PCB board, wherein the second side edge and the third side edge are opposite sides of the PCB board; the first electroplating bus (31) is formed as a split metal sheet, the split metal sheet includes: a plurality of intermediate segment metal sheets arranged between adjacent ground holes (13), a second side metal sheet extending out of the second side edge of the PCB board from the ground hole (13), and / or a third side metal sheet extending out of the third side edge of the PCB board from the ground hole (13); arranging a first electroplating branch line (32) on the PCB board, the first electroplating branch line (32) connects one or more non-ground network gold fingers (12) in the gold finger to the first electroplating bus (31); electroplating the gold finger by using the first electroplating bus (31) and the first electroplating branch line (32); and, after the electroplating is completed, drilling a hole (33) on the first electroplating branch line (32) to cut off the connection between the non-ground network gold finger (12) and the first electroplating bus (31).

2. The method according to claim 1, wherein, the first electroplating branch line (32) is formed as a lead wire respectively extending from one or more non-ground network gold fingers in a first direction and connected to the first electroplating bus (31).

3. The method of claim 1, wherein, drilling the hole (33) on the first electroplating branch line (32) close to the position of the non-ground network gold finger (12).

4. The method of claim 1, wherein, The PCIE gold finger includes a PCIE GEN5 gold finger and / or a PCIE GEN6 gold finger.

5. A method of manufacturing a PCIE golden finger, characterized in that, The gold finger is arranged on a PCB board, the gold finger includes a ground network gold finger and a non-ground network gold finger, the method comprises: connecting the ground network gold finger (11) with a ground hole (13) located on the first side thereof; arranging a second electroplating bus (51) on the PCB board, the second electroplating bus (51) at least includes: a second side electroplating bus extending out of the second side edge of the PCB board from one or more ground holes (13) on the first side of the gold finger, and / or a third side electroplating bus extending out of the third side edge of the PCB board from one or more ground holes (13) on the first side of the gold finger, wherein the second side edge and the third side edge are opposite sides of the PCB board; A second electroplating branch line (52) is arranged on the PCB board, and the second electroplating branch line (52) connects the non-ground network gold finger (12) to a ground hole (13) adjacent to the non-ground network gold finger (12) to electrically connect the non-ground network gold finger (12) to the second side electroplating bus and / or the third side electroplating bus; the second electroplating branch line (52) includes: a curved lead wire connected from the non-ground network gold finger (12) to a first adjacent ground hole adjacent thereto, and / or a curved lead wire connected from the non-ground network gold finger (12) to a second adjacent ground hole adjacent thereto; the first adjacent ground hole is close to a first side edge of the PCB board relative to the non-ground network gold finger (12), and the second adjacent ground hole is close to a second side edge of the PCB board relative to the non-ground network gold finger (12); The gold finger is electroplated by using the second electroplating bus (51) and the second electroplating branch line (52); and After electroplating is completed, a hole (53) is drilled on the second electroplating branch line (52) to cut off the electrical connection between the non-ground network gold finger (12) and the second electroplating bus (51).

6. The method of claim 5, wherein, A hole is drilled on the second electroplating branch line (52) close to the non-ground network gold finger (12).

7. The method of claim 5, wherein, The PCIE gold finger includes: a PCIE GEN5 gold finger, and / or a PCIE GEN6 gold finger.

8. A plating lead structure of a PCIE golden finger, characterized in that, The gold finger includes a ground network gold finger (11) and a non-ground network gold finger (12) arranged on a PCB board, and the ground network gold finger (11) is connected to a ground hole (13) located on a first side thereof; the electroplating lead wire structure includes: A first electroplating bus (31) and a first electroplating branch line (32) arranged on a PCB board; The first electroplating bus (31) connects all ground holes (13) on a first side of the gold finger together and extends out of a second side edge and / or a third side edge of the PCB board, wherein the second side edge and the third side edge are opposite side edges of the PCB board; the first electroplating bus (31) is formed as a split metal sheet, and the split metal sheet includes: an intermediate segment metal sheet arranged between adjacent ground holes (13), a second side metal sheet extending out of the second side edge of the PCB board from one or more ground holes (13) on the first side of the gold finger, and / or a third side metal sheet extending out of the third side edge of the PCB board from one or more ground holes (13) on the first side of the gold finger; The first electroplating branch line (32) connects one or more non-ground network gold fingers (12) in the gold finger to the first electroplating bus (31).

9. The structure of claim 8, wherein In the case where electroplating is completed, a cutting structure for cutting off the connection between the non-ground network gold finger (11) and the first electroplating bus (31) is arranged on the first electroplating branch line (32) close to the non-ground network gold finger (12).

10. The structure of claim 9, wherein The cutting structure includes a hole (33) structure.

11. The structure of claim 8, wherein, The first electroplating branch line (32) comprises a lead wire extending from the non-ground network golden finger (12) in a first direction and connected to the first electroplating bus line (31).

12. The structure of claim 8, wherein The PCIE golden finger comprises a PCIE GEN5 golden finger and / or a PCIE GEN6 golden finger.

13. A plating lead structure of a PCIE golden finger, characterized in that, The golden finger comprises a ground network golden finger (11) and a non-ground network golden finger (12) arranged on a PCB board, the ground network golden finger (11) being connected to a ground hole (13) located on a first side thereof; the electroplating lead wire structure comprises: a second electroplating bus line (51) and a second electroplating branch line (52) arranged on the PCB board; wherein, The second electroplating bus line (51) at least comprises a second side electroplating bus line extending from one or more ground holes (13) on a first side of the golden finger to an edge of a second side of the PCB board, and / or a third side electroplating bus line extending from one or more ground holes (13) on the first side of the golden finger to an edge of a third side of the PCB board, wherein the second side and the third side are opposite sides of the PCB board; and, The second electroplating branch line (52) connects the non-ground network golden finger (12) to an adjacent ground hole, so that the non-ground network golden finger (12) is electrically connected to the second side electroplating bus line and / or the third side electroplating bus line; The second electroplating branch line (52) comprises a curved lead wire connecting the non-ground network golden finger (12) to a first adjacent ground hole adjacent thereto, and / or a curved lead wire connecting the non-ground network golden finger (12) to a second adjacent ground hole adjacent thereto; the first adjacent ground hole is close to the first side edge of the PCB board relative to the non-ground network golden finger (12), and the second adjacent ground hole is close to the second side edge of the PCB board relative to the non-ground network golden finger (12).

14. The structure of claim 13, wherein In the case where electroplating is completed, a cutting structure for cutting the electrical connection between the non-ground network golden finger (12) and the second electroplating bus line (51) is arranged on the second electroplating branch line (52) close to the non-ground network golden finger (12).

15. The structure of claim 14, wherein The cutting structure is a hole (53) structure.

16. The structure of claim 13, wherein The PCIE golden finger comprises a PCIE GEN5 golden finger and / or a PCIE GEN6 golden finger.

17. A PCIE golden finger, characterized in that, Comprise: The PCIE golden finger obtained by the method of any one of claims 1-4 or claims 5-7. The PCIE golden finger obtained by the method of any one of claims 1-4 or claims 5-7.

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