Display substrate, method for manufacturing display substrate, and display device

Abstract

The embodiment of the present application discloses a display substrate, a manufacturing method of the display substrate and a display device, wherein the display substrate includes a substrate, a light shielding layer is arranged in the substrate; a low-temperature polysilicon thin film transistor is arranged on the substrate, including a first active layer, a first gate and a gate metal layer are sequentially stacked on the first active layer; an oxide thin film transistor includes a second active layer, a second gate is arranged on the second active layer; wherein the gate metal layer and the second gate are located in the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located within the orthographic projection area of ​​the light shielding layer on the substrate. The present application simplifies the manufacturing process of the display substrate and reduces the manufacturing cost of the display substrate by reducing the process procedures for manufacturing the film layer in the display substrate.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a display substrate, a method for manufacturing a display substrate, and a display device. Background Art

[0002] At present, in the field of display panels, in order to achieve high response speed, high contrast, and high brightness screen display, organic light-emitting diode technology has been greatly developed in the display field. However, with the development of wearable devices and wearable display fields, and in the context of the lack of significant breakthroughs in the current battery field technology, people have higher and higher requirements for the power consumption of display devices. Currently, low-temperature polycrystalline silicon technology used to drive thin-film transistors and switch thin-film transistors is a mainstream technology trend, and low-temperature polycrystalline silicon thin-film transistors have low power consumption. However, due to the large carrier mobility of low-temperature polycrystalline silicon, there is a problem of high leakage current. Therefore, LTPO (Low Temperature Polycrystalline-Si Oxide) technology came into being. It combines the advantages of both low-temperature polycrystalline silicon and oxide to form an LTPO solution with fast response speed and lower power consumption.

[0003] In the related art, the manufacturing process of the LTPO substrate is relatively complicated and the manufacturing cost is relatively high. Therefore, the structure of the existing LTPO display panel needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a display substrate, a method for manufacturing the display substrate, and a display device, which simplify the manufacturing process of the display substrate and reduce the manufacturing cost of the display substrate.

[0005] In a first aspect, an embodiment of the present application provides a display substrate, comprising:

[0006] A substrate, wherein a light shielding layer is disposed in the substrate;

[0007] A low-temperature polysilicon thin-film transistor is disposed on the substrate and comprises a first active layer, on which a first gate and a gate metal layer are sequentially stacked;

[0008] An oxide thin film transistor comprises a second active layer on which a second gate is arranged; wherein the gate metal layer and the second gate are located in the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located within the orthographic projection area of ​​the light shielding layer on the substrate.

[0009] Optionally, the first active layer is covered with a first gate insulating layer, the first gate insulating layer is arranged between the first active layer and the first gate, and the first gate is covered with a second gate insulating layer.

[0010] Optionally, a third gate insulating layer is arranged on the second gate insulating layer, the third gate insulating layer includes a first part and a second part, the first part of the third gate insulating layer is arranged between the second gate insulating layer and the gate metal layer, and the orthographic projection area of ​​the first part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the gate metal layer on the substrate.

[0011] Optionally, the second active layer is arranged on the second gate insulating layer, the second part of the third gate insulating layer is arranged between the second gate and the second active layer, and the orthographic projection area of ​​the second part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the second gate on the substrate.

[0012] Optionally, the first portion of the third gate insulating layer and the gate metal layer are covered with an interlayer insulating layer; and the second portion of the third gate insulating layer, the second gate and the second active layer are covered with the interlayer insulating layer.

[0013] Optionally, the substrate includes a first flexible base layer, a first barrier layer, a second flexible base layer, a second barrier layer and a buffer layer which are stacked in sequence, and the light shielding layer is arranged in the second barrier layer.

[0014] Optionally, an orthographic projection area of ​​the first active layer on the substrate is staggered or partially overlapped with an orthographic projection area of ​​the light shielding layer on the substrate.

[0015] In a second aspect, an embodiment of the present application provides a method for manufacturing a display substrate, comprising:

[0016] Providing a substrate, and depositing a light shielding layer in the substrate;

[0017] forming a first active layer of a low temperature polysilicon thin film transistor on the substrate;

[0018] forming a first gate and a gate metal layer in sequence on the first active layer, wherein the first gate is covered with a second gate insulating layer;

[0019] A second active layer of an oxide thin film transistor is formed on the second gate insulating layer, and a second gate is formed on the second active layer; wherein the gate metal layer and the second gate are located on the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located within the orthographic projection area of ​​the light shielding layer on the substrate.

[0020] Optionally, the method further includes:

[0021] A first gate insulating layer is formed on the first active layer, wherein the first gate insulating layer is disposed between the first active layer and the first gate.

[0022] Optionally, the method further includes:

[0023] forming a third gate insulating layer and a metal layer in sequence on the second gate insulating layer;

[0024] The third gate insulating layer and the metal layer are etched to obtain a first part and a second part corresponding to the third gate insulating layer, and a gate metal layer and a second gate corresponding to the metal layer; wherein the first part of the third gate insulating layer is arranged between the second gate insulating layer and the gate metal layer, and the orthographic projection area of ​​the first part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the gate metal layer on the substrate; the second part of the third gate insulating layer is arranged between the second gate and the second active layer, and the orthographic projection area of ​​the second part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the second gate on the substrate.

[0025] Optionally, the method further includes:

[0026] An interlayer insulating layer is formed on the second gate insulating layer, wherein the interlayer insulating layer covers a first portion of the third gate insulating layer and the gate metal layer, and the interlayer insulating layer covers a second portion of the third gate insulating layer, the second gate, and the second active layer.

[0027] In a third aspect, an embodiment of the present application further provides a display device, comprising a display substrate as described in any one of the above items.

[0028] The display substrate provided by the embodiment of the present application includes a substrate, a light shielding layer is arranged in the substrate; a low-temperature polysilicon thin film transistor is arranged on the substrate, including a first active layer, a first gate and a gate metal layer are sequentially stacked on the first active layer; an oxide thin film transistor includes a second active layer, a second gate is arranged on the second active layer; wherein the gate metal layer and the second gate are located in the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located within the orthographic projection area of ​​the light shielding layer on the substrate. The present application simplifies the manufacturing process of the display substrate by reducing the process procedures for manufacturing the film layer in the display substrate, and reduces the manufacturing cost of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The technical solution and beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0030] Figure 1It is a structural schematic diagram of a display substrate in the related technology provided in an embodiment of the present application.

[0031] Figure 2 It is a schematic diagram of the structure of the display substrate provided in an embodiment of the present application.

[0032] Figure 3 It is a schematic flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application.

[0033] Figure 4 It is a schematic structural diagram of a first intermediate product of a display substrate provided in an embodiment of the present application.

[0034] Figure 5 It is a schematic structural diagram of the second intermediate product of the display substrate provided in an embodiment of the present application.

[0035] Figure 6 It is a schematic structural diagram of the third intermediate product of the display substrate provided in an embodiment of the present application.

[0036] Figure 7 It is a schematic structural diagram of the fourth intermediate product of the display substrate provided in an embodiment of the present application.

[0037] Figure 8 It is a schematic structural diagram of the fifth intermediate product of the display substrate provided in an embodiment of the present application.

[0038] Fig. 9 It is a schematic structural diagram of the sixth intermediate product of the display substrate provided in an embodiment of the present application.

[0039] Fig.10 It is a schematic structural diagram of the seventh intermediate product of the display substrate provided in an embodiment of the present application.

[0040] Fig.11 It is a schematic structural diagram of the eighth intermediate product of the display substrate provided in an embodiment of the present application.

[0041] Fig.12 It is a schematic structural diagram of the ninth intermediate product of the display substrate provided in an embodiment of the present application.

[0042] Fig.13 It is a schematic structural diagram of the tenth intermediate product of the display substrate provided in an embodiment of the present application.

[0043] Fig.14 It is a schematic structural diagram of the eleventh intermediate product of the display substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] The directional terms mentioned in the present invention, such as [upper], [lower], [front], [back], [left], [right], [inner], [outer], [side], etc., are only used to refer to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention. In the drawings, units with similar structures are represented by the same reference numerals.

[0046] The display substrate is the main component of the display device, which includes a substrate and a display unit arranged on the substrate. The display unit may include a TFT (Thin Film Transistor), an LTPS (Low Temperature Poly-Silicon) substrate refers to a display substrate in which the thin film transistor in the display unit is a low temperature polycrystalline silicon thin film transistor, and an oxide substrate refers to a display substrate in which the thin film transistor in the display unit is an oxide thin film transistor. The mobility of the low temperature polycrystalline silicon active layer is relatively large, which makes the leakage current of the low temperature polycrystalline silicon thin film transistor relatively large. The power consumption of the low temperature polycrystalline silicon substrate under low frequency driving is relatively large, and it is difficult to maintain a static black screen well, and the picture quality is relatively poor; and in order to better expand the gray scale, in the low temperature polycrystalline silicon substrate, the channel of the driving thin film transistor needs to be made very long, so it is difficult to achieve the high resolution of the low temperature polycrystalline silicon substrate, and the resolution refers to the number of pixels set per inch; in addition, the hysteresis of the low temperature polycrystalline silicon active layer is relatively large, so the low temperature polycrystalline silicon substrate is prone to the problem of image retention. The oxide active layer has a low mobility, which makes the leakage current of the oxide thin film transistor small. The oxide substrate has low power consumption under low-frequency driving, which can well maintain a static black screen and improve the picture quality. In addition, the oxide active layer has a low hysteresis, and the oxide substrate is not prone to image retention. Furthermore, the uniformity of the oxide thin film transistor is better than that of the low-temperature polysilicon thin film transistor.

[0047] From the above description, it can be seen that the oxide thin film transistor process can well make up for some of the shortcomings of the low-temperature polysilicon thin film transistor process, but both have their own advantages and disadvantages. Therefore, the combination of oxide thin film transistors and low-temperature polysilicon thin film transistors can obtain LTPO technology. However, due to the difficulty in compatibility between low-temperature polysilicon thin film transistors and oxide thin film transistors, the stability of LTPO technology is insufficient.

[0048] In the related art, the display substrate based on LTPO technology is an LTPO substrate, in which each display unit includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor. Figure 1 , Figure 1 1 is a schematic diagram of the structure of a display substrate in the related art provided by an embodiment of the present application. The display substrate 100 includes a substrate 101, a low-temperature polysilicon active layer 102 disposed on the substrate 101, a first gate insulating layer 103 covering the low-temperature polysilicon active layer 102, a low-temperature polysilicon gate 104 disposed on the first gate insulating layer 103, a second gate insulating layer 105 covering the low-temperature polysilicon gate 104, a gate metal layer 106 and a light shielding layer 107 disposed on the second gate insulating layer 105, a first interlayer insulating layer 108 covering the gate metal layer 106 and the light shielding layer 107, and a An oxide active layer 109 is formed on the first interlayer insulating layer 108, a third gate insulating layer 110 covering the oxide active layer 109, an oxide gate 111 is formed on the third gate insulating layer 110, and a second interlayer insulating layer 112 is formed on the oxide gate 111, wherein the gate metal layer 106 and the light shielding layer 107 are in the same layer, an antistatic layer 113 is formed on the substrate 101, and an orthographic projection area of ​​the oxide gate 111 on the substrate 101 is staggered from an orthographic projection area of ​​the antistatic layer 113 on the substrate.

[0049] Figure 1 The manufacturing process of the LTPO substrate shown in the figure requires the deposition of at least three gate insulating layers and two interlayer insulating layers, which makes the manufacturing process of the LTPO substrate more complicated and the manufacturing cost higher. In addition, the above-mentioned LTPO substrate has more film layers, making the overall film layer thicker, which is not conducive to the development of ultra-thin display technology.

[0050] To solve the above problems, the present invention provides a display substrate, a method for manufacturing the display substrate, and a display device. Figure 2 , Figure 2 2 is a schematic diagram of the structure of a display substrate provided in an embodiment of the present application. The display substrate 200 may include a substrate 20 , a low-temperature polysilicon thin film transistor 30 , and an oxide thin film transistor 40 .

[0051] A light shielding layer 201 is arranged in the substrate 20, and the substrate 20 may include a first flexible base layer 202, a first barrier layer 203, a second flexible base layer 204, a second barrier layer 205 and a buffer layer 206 which are stacked in sequence. The light shielding layer 201 is arranged in the second barrier layer 205, and the light shielding layer 201 is a metal material, which may be molybdenum, aluminum, copper, titanium, etc. The light shielding layer 201 may also be an alloy material, and its thickness is 2000-8000 angstroms, and has a certain pattern, that is, the light shielding layer 201 does not occupy the entire area of ​​the second barrier layer 205, but is arranged in the second barrier layer 205 in the form of a certain pattern.

[0052] It should be noted that the first barrier layer 203 can be used to isolate air and water vapor to ensure the stability of the display substrate 200. The light shielding layer 201 disposed in the second barrier layer 205 can not only shield light but also prevent static electricity. When the light shielding layer 201 prevents static electricity, the second barrier layer 205 includes two CVD sub-film layers, and the light shielding layer 201 is disposed between the two CVD sub-film layers.

[0053] Among them, the low-temperature polycrystalline silicon thin film transistor 30 is arranged on the substrate 20, and the low-temperature polycrystalline silicon thin film transistor 30 includes a first active layer 301, the first active layer 301 is an a-Si amorphous silicon material, both sides of the first active layer 301 are doped to form a first source-drain overlapping region, and a first gate 302 and a gate metal layer 303 are stacked on the first active layer 301. A first gate insulating layer 304 is covered on the first active layer 301, and a part of the first gate insulating layer 304 is arranged between the first active layer 301 and the first gate 302. The first gate insulating layer 304 can be an oxide silicide (SiOx) layer, a nitride silicide (SiNx) layer or a multilayer structure film, etc., and its thickness is 1000-3000 angstroms. The device characteristics made of the oxide silicide (SiOx) layer, the nitride silicide (SiNx) layer or the multilayer structure film are better, and the oxide silicide (SiOx) layer, the nitride silicide (SiNx) layer or the multilayer structure film have better stress matching with polysilicon. The first gate 302 is a metal material, which can be molybdenum, aluminum, copper, titanium, etc., and its thickness is 2000-8000 angstroms. The gate metal layer 303 can be used to form one of the plates of the storage capacitor in the pixel circuit on the display substrate 200, and the other plate of the storage capacitor can be formed by the first gate 302.

[0054] A second gate insulating layer 305 is covered on the first gate 302. The second gate insulating layer 305 can be made of the same material as the first gate insulating layer 304, such as an oxide silicide layer, a nitride silicide layer or a multi-layer structure film, etc., and its thickness is 1000-3000 angstroms. A third gate insulating layer 306 is arranged on the second gate insulating layer 305. The third gate insulating layer 306 can be an oxide silicide (SiOx) layer, a nitride silicide (SiNx) layer or a multi-layer structure film, etc., and its thickness is 1000-3000 angstroms. The third gate insulating layer 306 includes a first part and a second part. The first part of the third gate insulating layer 306 is arranged between the second gate insulating layer 305 and the gate metal layer 303, and the orthographic projection area of ​​the first part of the third gate insulating layer 306 on the substrate 20 is the same as the orthographic projection area of ​​the gate metal layer 303 on the substrate 20, that is, the first part of the third gate insulating layer 306 exists only below the film layer of the gate metal layer 303. The gate metal layer 303 is made of metal material, which may be molybdenum, aluminum, copper, titanium, etc., or an alloy, and has a thickness of 2000-8000 angstroms.

[0055] The oxide thin film transistor 40 includes a second active layer 401. The second active layer 401 may be a semiconductor layer made of semiconductor materials, such as IGZO, IZTO or IGZTO, with a thickness of 100-1000 angstroms. The semiconductor material in the second active layer 401 is subjected to conductor processing, so that a second source-drain overlap region is formed on both sides of the second active layer 401. A second gate 402 is arranged on the second active layer 401. The second gate 402 is made of a metal material, such as molybdenum, aluminum, copper, titanium, etc., or an alloy, with a thickness of 2000-8000 angstroms. The second gate 402 is located in the same layer as the gate metal layer 303 in the low-temperature polysilicon thin film transistor 30, that is, the second gate 402 and the gate metal layer 303 are made by a one-time manufacturing process.

[0056] Among them, the second part of the third gate insulating layer 306 is arranged between the second gate 402 and the second active layer 401, the first part and the second part of the third gate insulating layer 306 are made by a one-time manufacturing process, and the orthographic projection area of ​​the second part of the third gate insulating layer 306 on the substrate 20 is the same as the orthographic projection area of ​​the second gate 402 on the substrate 20, that is, the second part of the third gate insulating layer 306 exists only under the film layer of the second gate 402.

[0057] In addition, an interlayer insulating layer 307 is covered on the first portion of the third gate insulating layer 306 and the gate metal layer 303, and the second portion of the third gate insulating layer 306, the second gate 402 and the second active layer 401 are covered with the interlayer insulating layer 307. The interlayer insulating layer 307 can be a silicide (SiOx) layer, a silicide (SiNx) layer or an organic material, etc., and has a thickness of 2000-10000 angstroms.

[0058] It should be noted that the orthographic projection area of ​​the second active layer 402 on the substrate 20 is located within the orthographic projection area of ​​the light shielding layer 201 on the substrate 20, that is, the light shielding layer 201 has multiple uses, and can not only play an antistatic role for the display substrate 200, but also play a light shielding role for the oxide thin film transistor 40. Figure 1 As shown, in the related art, the light-shielding layer for the oxide thin-film transistor is a light-shielding layer 107 arranged below the oxide active layer 109, and the light-shielding layer 107 is made in a single process together with the gate metal layer 106. In the embodiment of the present application, since the light-shielding layer 201 is arranged in the substrate 20, there is no need to consider the light-shielding problem of the oxide thin-film transistor 40 when preparing the display substrate 200, that is, there is no need to add a process for preparing the light-shielding layer below the second active layer 401 when preparing the gate metal layer 303, so that in the process of preparing the gate insulating layer 303, the position where the light-shielding layer is originally prepared is used to prepare the second gate 402 of the oxide thin-film transistor 40, thereby reducing the preparation process of the metal film layer once, simplifying the manufacturing process of the display substrate 200, and reducing the manufacturing cost of the display substrate 200.

[0059] In one embodiment, the oxide thin film transistor 40 may be a double-deletion structure, and may include a third gate in addition to the second gate 402. Specifically, the third gate may be disposed between the buffer layer 206 and the second barrier layer 205 in the substrate 20, and the third gate constitutes the bottom gate portion of the oxide thin film transistor 40.

[0060] In addition, in the related art, two interlayer insulating layers are used to cover the two metal film layers respectively, that is, the first interlayer insulating layer 108 covers the light-shielding layer 107, and the second interlayer insulating layer 112 covers the oxide gate 111. However, in the present application, since the light-shielding layer 201 is set on the substrate 20, there is no need to cover the light-shielding layer with an interlayer insulating layer. The second gate 402 only needs to be covered with a layer of interlayer insulating layer, and the gate metal layer 303 is covered at the same time as the second gate 402 is covered, that is, the interlayer insulating layer 307 covers the gate metal layer 303 and the second gate 402. Compared with the related art, the preparation of one interlayer insulating layer can be reduced, and the thickness of the overall film layer of the display substrate 200 can be reduced, which is conducive to the development of ultra-thin display technology.

[0061] After forming the interlayer insulating layer 307, source-drain overlapping holes can be formed by opening vias at corresponding positions of the source-drain overlapping regions, wherein a first source-drain overlapping region is arranged on the first active layer 301 in the low-temperature polycrystalline silicon thin film transistor 30, and a first source-drain overlapping hole is formed on the first source-drain overlapping region; a second source-drain overlapping region is arranged on the second active layer 401 in the oxide thin film transistor 40, and a second source-drain overlapping hole is formed on the second source-drain overlapping region; a third source-drain overlapping region is arranged on the light-shielding layer 201, and a third source-drain overlapping hole is formed on the third source-drain overlapping region.

[0062] The source-drain electrode pattern is defined by depositing the source-drain metal layer, and the source-drain metal layer may include a first source-drain metal layer 51, a second source-drain metal layer 52, and a third source-drain metal layer 53. The first source-drain metal layer 51, the second source-drain metal layer 52, and the third source-drain metal layer 53 are all arranged on the interlayer insulating layer 307, and the first source-drain metal layer 51 is connected to the first source-drain overlapping region through a first routing line arranged in the first source-drain overlapping hole; the second source-drain metal layer 52 is connected to the second source-drain overlapping region through a second routing line arranged in the second source-drain overlapping hole; and the third source-drain metal layer 53 is connected to the third source-drain overlapping region through a third routing line arranged in the third source-drain overlapping hole. The first source-drain metal layer 51, the second source-drain metal layer 52, and the third source-drain metal layer 53 can be formed by the same photomask process, thereby reducing the photomask process.

[0063] Among them, the source and drain in the first source-drain metal layer and the first gate 302 respectively constitute the source, drain and gate of the low-temperature polysilicon thin film transistor 30; the source and drain in the second source-drain metal layer and the second gate 402 respectively constitute the source, drain and gate of the oxide thin film transistor 40.

[0064] The first drain metal layer, the second source-drain metal layer and the third source-drain metal layer are covered with a passivation layer 50, thereby completing the manufacture of the display substrate 200. The display substrate 200 can be a flexible display substrate or a rigid display substrate, and the display substrate 200 can be applied to wearable devices such as smart bracelets, smart watches, VR (Virtual Reality) and other devices, and can also be applied to e-books, e-newspapers, televisions, portable computers, and foldable, rollable and other OLED flexible displays and lighting.

[0065] As can be seen from the above, the display substrate 200 provided in this embodiment includes a substrate, a light shielding layer is arranged in the substrate; a low-temperature polysilicon thin film transistor is arranged on the substrate, including a first active layer, a first gate and a gate metal layer are sequentially stacked on the first active layer; an oxide thin film transistor includes a second active layer, and a second gate is arranged on the second active layer; wherein the gate metal layer and the second gate are located in the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located in the orthographic projection area of ​​the light shielding layer on the substrate. By reducing the process procedures for manufacturing the film layer in the display substrate, the manufacturing process of the display substrate is simplified and the manufacturing cost of the display substrate is reduced.

[0066] The present application also provides a method for manufacturing a display substrate. Figure 3 , Figure 3 1 is a flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application. The method for manufacturing a display substrate may include the following steps:

[0067] 501. Provide a substrate and deposit a light shielding layer in the substrate.

[0068] See also Figure 4 , Figure 4 2 is a schematic diagram of the structure of the first intermediate product in the display substrate provided in an embodiment of the present application. The display substrate 200 provides a substrate 20, and the substrate 20 may include a first flexible base layer 202, a first barrier layer 203, a second flexible base layer 204, a second barrier layer 205 and a buffer layer 206 stacked in sequence. Among them, a light shielding layer 201 is deposited in the substrate 20, and the light shielding layer 201 is arranged in the second barrier layer 205. The light shielding layer 201 is a metal material, which can be molybdenum, aluminum, copper, titanium, etc. The light shielding layer 201 can also be an alloy material with a thickness of 2000-8000 angstroms and a certain pattern, that is, the light shielding layer 201 does not occupy the entire area of ​​the second barrier layer 205, but is arranged in the second barrier layer 205 in the form of a certain pattern.

[0069] It should be noted that the first barrier layer 203 can be used to isolate air and water vapor to ensure the stability of the display substrate 200. The light shielding layer 201 disposed in the second barrier layer 205 can not only shield light but also prevent static electricity. When the light shielding layer 201 prevents static electricity, the second barrier layer 205 includes two CVD sub-film layers, and the light shielding layer 201 is disposed between the two CVD sub-film layers.

[0070] 502. Form a first active layer of a low-temperature polysilicon thin film transistor on a substrate.

[0071] See also Figure 5 , Figure 5A layer of a-Si amorphous silicon material is deposited on the substrate 20 , and the a-Si amorphous silicon material is patterned to form a first active layer 301 of a polysilicon thin film transistor 30 .

[0072] See also Figure 6 , Figure 6 Schematic diagram of the structure of the third intermediate product of the display substrate provided in the embodiment of the present application. A first gate insulating layer 304 is deposited on the first active layer 301, and the first gate insulating layer 304 covers the first active layer 301. The first gate insulating layer 304 can be a silicide (SiOx) layer, a silicide (SiNx) layer, or a multilayer structure film, etc., and its thickness is 1000-3000 angstroms.

[0073] A metal layer is deposited on the first gate insulating layer 304. The material of the metal layer may be molybdenum, aluminum, copper, titanium, etc., and the thickness thereof is 2000-8000 angstroms.

[0074] 503. A first gate and a gate metal layer are sequentially formed on the first active layer, wherein the first gate is covered with a second gate insulating layer.

[0075] See also Figure 7 , Figure 7 is a schematic structural diagram of a fourth intermediate product of a display substrate provided in an embodiment of the present application. Figure 6 The metal layer in the first active layer 301 is patterned to form a first gate 302, and both sides of the first active layer 301 are doped to form a first source-drain overlap region. A first gate insulating layer 304 is formed on the first active layer 301, and a portion of the first gate insulating layer 304 is disposed between the first active layer 301 and the first gate 302.

[0076] See also Figure 8 , Figure 8 1 is a schematic diagram of the structure of the fifth intermediate product of the display substrate provided in the embodiment of the present application. A layer of silicon oxide (SiOx) layer, silicon nitride (SiNx) layer or a multi-layer structure film is deposited on the first gate 302 to form a second gate insulating layer 305, and the second gate insulating layer 305 covers the first gate 302, and the second gate insulating layer 305 can be made of the same material as the first gate insulating layer 304, and the thickness thereof is 1000-3000 angstroms.

[0077] 504 . Form a second active layer of the oxide thin film transistor on the second gate insulating layer, and form a second gate on the second active layer.

[0078] See also Fig. 9 , Fig. 9Schematic diagram of the structure of the sixth intermediate product of the display substrate provided in the embodiment of the present application. A layer of metal oxide semiconductor material is deposited on the second gate insulating layer 305 as a semiconductor layer, and the semiconductor layer is patterned to form a second active layer 401. The semiconductor layer can be made of IGZO, IZTO or IGZTO, etc., and has a thickness of 100-1000 angstroms.

[0079] See also Fig.10 , Fig.10 Schematic diagram of the structure of the seventh intermediate product of the display substrate provided in the embodiment of the present application. A layer of silicon oxide (SiOx) layer, silicon nitride (SiNx) layer or a multi-layer structure film is deposited on the second active layer 305 to form a third gate insulating layer 306, and the third gate insulating layer 306 covers the second active layer 305. The material of the third gate insulating layer 306 can be the same as that of the first gate insulating layer 304 and the second gate insulating layer 305, and the thickness is 1000-3000 angstroms.

[0080] A metal layer is deposited on the third gate insulating layer 306. The metal layer may be made of molybdenum, aluminum, copper, titanium, etc., or an alloy, and has a thickness of 2000-8000 angstroms. That is, the third gate insulating layer 306 and a metal layer are sequentially formed on the second gate insulating layer 305.

[0081] See also Fig.11 , Fig.11 It is a schematic diagram of the structure of the eighth intermediate product of the display substrate provided by the embodiment of the present application. The third gate insulating layer 306 and the metal layer are etched to obtain the first part and the second part corresponding to the third gate insulating layer 306, and the gate metal layer 303 and the second gate 402 corresponding to the metal layer; wherein the first part of the third gate insulating layer 306 is arranged between the second gate insulating layer 305 and the gate metal layer 303, and the orthographic projection area of ​​the first part of the third gate insulating layer 306 on the substrate 20 is the same as the orthographic projection area of ​​the gate metal layer 303 on the substrate 20; the second part of the third gate insulating layer 306 is arranged between the second gate 402 and the second active layer 401, and the orthographic projection area of ​​the second part of the third gate insulating layer 306 on the substrate 20 is the same as the orthographic projection area of ​​the second gate 402 on the substrate 20.

[0082] The gate metal layer 303 can be used to form one of the plates of the storage capacitor in the pixel circuit on the display substrate 200, and the other plate of the storage capacitor can be formed by the first gate 302. The semiconductor material in the second active layer 401 is subjected to conductor processing, so that a second source-drain overlap region is formed on both sides of the second active layer 401.

[0083] Specifically, the etching process Fig.10The metal layer in the substrate 20 is etched to form a gate metal layer 303, and the third gate insulating layer 306 is etched through a self-alignment process to form a first portion of the third gate insulating layer 306, so that the orthographic projection area of ​​the first portion of the third gate insulating layer 306 on the substrate 20 is the same as the orthographic projection area of ​​the gate metal layer 303 on the substrate 20.

[0084] Through the etching process Fig.10 The metal layer in the substrate 20 is etched to form the second gate 402, and the third gate insulating layer 306 is etched through a self-alignment process to form a second portion of the third gate insulating layer 306, so that the orthographic projection area of ​​the second portion of the third gate insulating layer 306 on the substrate 20 is the same as the orthographic projection area of ​​the second gate 402 on the substrate 20.

[0085] It can be understood that the gate metal layer 303 and the second gate 402 are located in the same layer, and the orthographic projection area of ​​the second active layer 401 on the substrate 20 is located in the orthographic projection area of ​​the light shielding layer 201 on the substrate 20. The gate metal layer 303 and the second gate 402 are obtained by etching the same metal layer, that is, the second gate 402 and the gate metal layer 303 are made by a one-time manufacturing process. The first part and the second part of the third gate insulating layer 306 are obtained by etching the third gate insulating layer 306, that is, the first part and the second part of the third gate insulating layer 306 are made by a one-time manufacturing process.

[0086] It should be noted that the orthographic projection area of ​​the second active layer 402 on the substrate 20 is located within the orthographic projection area of ​​the light shielding layer 201 on the substrate 20, that is, the light shielding layer 201 has multiple uses, and can not only play an antistatic role for the display substrate 200, but also play a light shielding role for the oxide thin film transistor 40. Figure 1 As shown, in the related art, the light-shielding layer for the oxide thin-film transistor is a light-shielding layer 107 arranged below the oxide active layer 109, and the light-shielding layer 107 is made in a single process together with the gate metal layer 106. In the embodiment of the present application, since the light-shielding layer 201 is arranged in the substrate 20, there is no need to consider the light-shielding problem of the oxide thin-film transistor 40 when preparing the display substrate 200, that is, there is no need to add a process for preparing the light-shielding layer below the second active layer 401 when preparing the gate metal layer 303, so that in the process of preparing the gate insulating layer 303, the position where the light-shielding layer is originally prepared is used to prepare the second gate 402 of the oxide thin-film transistor 40, thereby reducing the preparation process of the metal film layer once, simplifying the manufacturing process of the display substrate 200, and reducing the manufacturing cost of the display substrate 200.

[0087] In addition, in the related art, two interlayer insulating layers are used to cover the two metal film layers respectively, that is, the first interlayer insulating layer 108 covers the light-shielding layer 107, and the second interlayer insulating layer 112 covers the oxide gate 111. However, in the present application, since the light-shielding layer 201 is set on the substrate 20, there is no need to cover the light-shielding layer with an interlayer insulating layer. The second gate 402 only needs to be covered with a layer of interlayer insulating layer, and the gate metal layer 303 is covered at the same time as the second gate 402 is covered, that is, the interlayer insulating layer 307 covers the gate metal layer 303 and the second gate 402. Compared with the related art, the preparation of one interlayer insulating layer can be reduced, and the thickness of the overall film layer of the display substrate 200 can be reduced, which is conducive to the development of ultra-thin display technology.

[0088] See also Fig.12 , Fig.12 Schematic diagram of the structure of the ninth intermediate product of the display substrate provided in the embodiment of the present application. A layer of silicon oxide (SiOx) layer, silicon nitride (SiNx) layer or organic material is deposited on the second gate insulating layer 305 to form an interlayer insulating layer 307, wherein the interlayer insulating layer 307 covers the first part of the third gate insulating layer 306 and the gate metal layer 303, and the interlayer insulating layer 307 covers the second part of the third gate insulating layer 306, the second gate 402 and the second active layer 401, and the thickness of the interlayer insulating layer 307 is 2000-10000 angstroms.

[0089] See also Fig.13 , Fig.13 It is a structural schematic diagram of the tenth intermediate product of the display substrate provided by the embodiment of the present application. After the interlayer insulating layer 307 is formed, a source-drain overlap hole can be formed by opening a via hole at the corresponding position of the source-drain overlap region, wherein a first source-drain overlap region is provided on the first active layer 301 in the low-temperature polysilicon thin film transistor 30, and a first source-drain overlap hole is formed on the first source-drain overlap region; a second source-drain overlap region is provided on the second active layer 401 in the oxide thin film transistor 40, and a second source-drain overlap hole is formed on the second source-drain overlap region; a third source-drain overlap region is provided on the light shielding layer 201, and a third source-drain overlap hole is formed on the third source-drain overlap region.

[0090] See also Fig.14 , Fig.14It is a structural schematic diagram of the eleventh intermediate product of the display substrate provided in an embodiment of the present application. The source-drain electrode pattern is defined by depositing the source-drain metal layer, and the source-drain metal layer may include a first source-drain metal layer 51, a second source-drain metal layer 52, and a third source-drain metal layer 53. Among them, the first source-drain metal layer 51, the second source-drain metal layer 52, and the third source-drain metal layer 53 are all arranged on the interlayer insulating layer 307, and the first source-drain metal layer 51 is connected to the first source-drain overlapping area through a first routing line arranged in the first source-drain overlapping hole; the second source-drain metal layer 52 is connected to the second source-drain overlapping area through a second routing line arranged in the second source-drain overlapping hole; the third source-drain metal layer 53 is connected to the third source-drain overlapping area through a third routing line arranged in the third source-drain overlapping hole. Among them, the first source-drain metal layer 51, the second source-drain metal layer 52, and the third source-drain metal layer 53 can be formed by the same photomask process, thereby reducing the photomask process.

[0091] Among them, the source and drain in the first source-drain metal layer and the first gate 302 respectively constitute the source, drain and gate of the low-temperature polysilicon thin film transistor 30; the source and drain in the second source-drain metal layer and the second gate 402 respectively constitute the source, drain and gate of the oxide thin film transistor 40.

[0092] A passivation layer 50 is deposited on the first drain metal layer, the second source-drain metal layer and the third source-drain metal layer, thereby completing the manufacture of the display substrate 200. Figure 2 The display substrate 200 shown. The display substrate 200 can be a flexible display substrate or a rigid display substrate. The display substrate 200 can be applied to wearable devices such as smart bracelets, smart watches, VR (Virtual Reality) devices, and can also be applied to e-books, e-newspapers, televisions, portable computers, and foldable, rollable OLED flexible displays and lighting.

[0093] The embodiment of the present application further provides a display device, which may include the display substrate provided in the above embodiment. The display device may be a full-screen display device, for example, the display device may be a wearable device such as a watch or a bracelet, or the display device may be an electronic device such as a mobile phone or a tablet computer, or the display device may be a product or component with a display function such as a television, a monitor, a laptop computer, a digital photo frame or a navigator.

[0094] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0096] The display substrate, the manufacturing method of the display substrate and the display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display substrate, characterized in that: include: The substrate comprises a first flexible base layer, a first barrier layer, a second flexible base layer, a second barrier layer and a buffer layer which are sequentially stacked, wherein a light shielding layer is provided in the second barrier layer; A low temperature polysilicon thin film transistor is arranged on the substrate, comprising a first active layer, on which a first gate and a gate metal layer are sequentially stacked; An oxide thin film transistor comprises a second active layer on which a second gate is arranged; wherein the gate metal layer and the second gate are located in the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located within the orthographic projection area of ​​the light shielding layer on the substrate.

2. The display substrate according to claim 1, characterized in that: The first active layer is covered with a first gate insulating layer, the first gate insulating layer is arranged between the first active layer and the first gate, and the first gate is covered with a second gate insulating layer.

3. The display substrate according to claim 2, characterized in that: A third gate insulating layer is arranged on the second gate insulating layer, and the third gate insulating layer includes a first part and a second part. The first part of the third gate insulating layer is arranged between the second gate insulating layer and the gate metal layer, and an orthographic projection area of ​​the first part of the third gate insulating layer on the substrate is the same as an orthographic projection area of ​​the gate metal layer on the substrate.

4. The display substrate according to claim 3, characterized in that: The second active layer is arranged on the second gate insulating layer, the second part of the third gate insulating layer is arranged between the second gate and the second active layer, and the orthographic projection area of ​​the second part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the second gate on the substrate.

5. The display substrate according to claim 3 or 4, characterized in that: The first portion of the third gate insulating layer and the gate metal layer are covered with an interlayer insulating layer; and the second portion of the third gate insulating layer, the second gate and the second active layer are covered with the interlayer insulating layer.

6. The display substrate according to claim 1, characterized in that: The orthographic projection area of ​​the first active layer on the substrate is staggered or partially overlapped with the orthographic projection area of ​​the light shielding layer on the substrate.

7. A method for manufacturing a display substrate, characterized in that: include: Providing a substrate, and depositing a light shielding layer in the substrate, wherein the substrate comprises a first flexible base layer, a first barrier layer, a second flexible base layer, a second barrier layer and a buffer layer stacked in sequence, and the light shielding layer is disposed in the second barrier layer; forming a first active layer of a low temperature polysilicon thin film transistor on the substrate; forming a first gate and a gate metal layer in sequence on the first active layer, wherein the first gate is covered with a second gate insulating layer; A second active layer of an oxide thin film transistor is formed on the second gate insulating layer, and a second gate is formed on the second active layer; wherein the gate metal layer and the second gate are located on the same layer, and the orthographic projection area of ​​the second active layer on the substrate is located within the orthographic projection area of ​​the light shielding layer on the substrate.

8. The method for manufacturing a display substrate according to claim 7, characterized in that: The method further comprises: A first gate insulating layer is formed on the first active layer, wherein the first gate insulating layer is disposed between the first active layer and the first gate.

9. The method for manufacturing a display substrate according to claim 7, wherein: The method further comprises: forming a third gate insulating layer and a metal layer in sequence on the second gate insulating layer; The third gate insulating layer and the metal layer are etched to obtain a first part and a second part corresponding to the third gate insulating layer, and a gate metal layer and a second gate corresponding to the metal layer; wherein the first part of the third gate insulating layer is arranged between the second gate insulating layer and the gate metal layer, and the orthographic projection area of ​​the first part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the gate metal layer on the substrate; the second part of the third gate insulating layer is arranged between the second gate and the second active layer, and the orthographic projection area of ​​the second part of the third gate insulating layer on the substrate is the same as the orthographic projection area of ​​the second gate on the substrate.

10. The method for manufacturing a display substrate according to claim 9, wherein: The method further comprises: An interlayer insulating layer is formed on the second gate insulating layer, wherein the interlayer insulating layer covers a first portion of the third gate insulating layer and the gate metal layer, and the interlayer insulating layer covers a second portion of the third gate insulating layer, the second gate, and the second active layer.

11. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 6.

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