Array substrate and manufacturing method thereof, and display panel

Abstract

The present application provides an array substrate, a manufacturing method thereof, and a display panel, which include: a substrate; a first thin film transistor layer located on the substrate, the first thin film transistor layer having a first control thin film transistor; and a second thin film transistor layer located on the substrate, the second thin film transistor layer having a second control thin film transistor, wherein the first thin film transistor layer and the second thin film transistor layer are located on the same layer, and the first control thin film transistor includes a first active layer located on one side of the substrate, the second control thin film transistor includes a second active layer located on the same layer as the first active layer, and the material of the first active layer is different from the material of the second active layer.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Flat panel display technology based on TFT (Thin Film Transistor) array is the mainstream of today's display technology. This is mainly because the processing technology of TFT is relatively simple, the process cost is low, and it is suitable for large-scale production. With the development of TFT flat panel display technology, more and more display drivers and other functional modules may be implemented using TFT integrated circuits. The row and column drive circuits, power supply circuits, photoelectric sensor circuits, etc. are made with TFT as the main components and integrated on the display panel to form a screen SoP (System on Panel). For example, an optical sensor is integrated in the display panel to realize the optical fingerprint recognition function.

[0003] In the traditional display panel sensing technology, the display panel for display fingerprint recognition is mostly an under-screen structure, that is, the display device emits light to illuminate the fingerprint, and the fingerprint reflected light is recognized by the under-screen photosensitive device. The display device and the sensor device need to be processed separately, and then the display device layer and the sensor device layer are bonded with OCA glue (Optically Clear Adhesive). The process is complicated and can only be used on OLED (Organic Light Emitting Diode). The structure is complex and cannot meet the application requirements of large-generation lines.

[0004] Therefore, there are defects in the prior art, which need to be solved urgently. Summary of the invention

[0005] The present application provides an array substrate, a display panel and a method for manufacturing the array substrate, which can form a display device layer and a sensing device layer on the same layer, have a simple structure and can meet the technical problems of application requirements of large-generation lines.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] An array substrate, comprising:

[0008] substrate;

[0009] a first thin film transistor layer located on the substrate, wherein the first thin film transistor layer has a first control thin film transistor; and

[0010] A second thin film transistor layer is located on the substrate, and the second thin film transistor layer has a second control thin film transistor, wherein the first thin film transistor layer and the second thin film transistor layer are located in the same layer, and the first control thin film transistor includes a first active layer located on one side of the substrate, and the second control thin film transistor includes a second active layer located in the same layer as the first active layer, and the material of the first active layer is different from the material of the second active layer.

[0011] In some embodiments of the present invention, the electron mobility of the first active layer is in the range of 50 to 200 cm 2 / Vs.

[0012] In some embodiments of the present invention, the first active layer includes a polycrystalline silicon layer located on one side of the substrate and a first upper amorphous silicon layer formed on a surface of the polycrystalline silicon layer, and a projection of the first upper amorphous silicon layer on the substrate covers a projection of the polycrystalline silicon layer on the substrate.

[0013] In some embodiments of the present invention, the second active layer includes a lower amorphous silicon layer located at the same layer as the polysilicon layer and a second upper amorphous silicon layer located on the surface of the lower amorphous silicon layer, and the second upper amorphous silicon layer belongs to the same layer as the first upper amorphous silicon layer.

[0014] In some embodiments of the present invention, the thickness of the polysilicon layer is greater than the thickness of the first upper amorphous silicon layer.

[0015] In some embodiments of the present invention, both the first control thin film transistor and the second control thin film transistor are bottom gate structures.

[0016] A display panel, comprising:

[0017] substrate;

[0018] A first thin film transistor layer located on the substrate, wherein the first thin film transistor layer has a first control thin film transistor;

[0019] A display device connected to the first thin film transistor layer, the display device is used to display information, and the first control thin film transistor is used to send or receive signals to the display device;

[0020] a second thin film transistor layer located on the substrate, wherein the second thin film transistor layer has a second control thin film transistor; and

[0021] A sensing device connected to the second thin film transistor layer, the sensing device is used to sense external environmental information, and the second control thin film transistor is used to send or receive a signal to the sensing device;

[0022] The first thin film transistor layer and the second thin film transistor layer are located in the same layer, and the first control thin film transistor includes a first active layer located on one side of the substrate, and the second control thin film transistor includes a second active layer located in the same layer as the first active layer, and the material of the first active layer is different from the material of the second active layer.

[0023] In some embodiments of the present invention, the display device is Mini-LED or Micro-LED; the sensing device is a light sensing device, a pressure sensing device or a temperature sensing device.

[0024] A method for manufacturing an array substrate comprises the following steps:

[0025] providing a substrate; and

[0026] A first thin film transistor layer and a second thin film transistor layer located in the same layer are manufactured on one side of the substrate, wherein the first thin film transistor layer comprises a first control thin film transistor, and the first control thin film transistor comprises a first active layer located on one side of the substrate; and the second thin film transistor layer comprises a second control thin film transistor, so that the second active layer included in the second control thin film transistor is located in the same layer as the first active layer, and the material of the first active layer is different from the material of the second active layer.

[0027] In some embodiments of the present invention, manufacturing the first thin film transistor layer comprises the following steps:

[0028] forming a first gate on the substrate;

[0029] forming a gate insulating layer on the first gate;

[0030] forming a lower amorphous silicon layer on the gate insulating layer;

[0031] Using a blue laser diode annealing technique to locally crystallize a preset area of ​​the lower amorphous silicon layer to obtain a polycrystalline silicon layer;

[0032] Depositing an amorphous silicon doping layer on the amorphous silicon layer;

[0033] forming a source-drain electrode layer on the amorphous silicon doped layer; and

[0034] The source and drain electrode layer is etched to form a source electrode and a drain electrode, so as to form the first thin film transistor layer.

[0035] The beneficial effects of the present application are as follows: the array substrate and its manufacturing method and display panel provided by the present application, the array substrate includes a first thin film transistor layer located on the substrate, the first thin film transistor layer has a first control thin film transistor; and includes a second thin film transistor layer located on the substrate, the second thin film transistor layer has a second control thin film transistor, wherein the first thin film transistor layer and the second thin film transistor layer are located on the same layer, and the first control thin film transistor includes a first active layer located on one side of the substrate, the second control thin film transistor includes a second active layer located on the same layer as the first active layer, and the material of the first active layer is different from that of the second active layer. That is to say, the active layers of the thin film transistors for display requirements and control requirements of the sensing device are located on the same layer, the structure is simple, and then the active layers that meet the respective appropriate electron mobility can be prepared according to the display requirements and the control requirements of the sensing device, thereby meeting the actual application requirements of the large generation line. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 It is a cross-sectional schematic diagram of a substrate provided in the first embodiment of the present application, a first gate and a second gate formed on the substrate, and a gate insulating layer formed on the surfaces of the first gate and the second gate.

[0038] Figure 2 For Figure 1 A schematic cross-sectional view of a lower amorphous silicon layer deposited on the basis of FIG.

[0039] Figure 3 It is a cross-sectional schematic diagram of hydrogenating and crystallizing the amorphous silicon in the area of ​​the lower amorphous silicon layer corresponding to the first gate by using the BLDA technology.

[0040] Figure 4 For Figure 3 A cross-sectional schematic diagram of forming a first upper amorphous silicon layer and a second upper amorphous silicon layer on the basis of.

[0041] Figure 5 For Figure 4 A cross-sectional schematic diagram of an amorphous silicon doped layer formed on the basis of.

[0042] Figure 6 For Figure 5 A cross-sectional schematic diagram of a source and drain layer formed on the basis of.

[0043] Figure 7 For Figure 6A schematic cross-sectional view of patterning the source and drain electrode layer to form a source electrode, a drain electrode, a passivation layer, a first pixel electrode, and a second pixel electrode.

[0044] Figure 8 For Figure 7 A display device and a sensing device are formed on the basis of the display device to obtain a schematic diagram of a display panel.

[0045] Fig. 9 A schematic diagram of a top-down structure of a pixel provided in an embodiment of the present invention.

[0046] Description of Reference Numerals

[0047] 200-display panel; 100-array substrate; 1-display device;

[0048] 2-sensing device; 210-scanning line; 212-data line; 6-passivation layer; 60-first pixel electrode;

[0049] 62-second pixel electrode; 3-substrate; 4-first thin film transistor layer; 5-second thin film transistor layer;

[0050] 40 - a first control thin film transistor; 50 - a second control thin film transistor; 430 - a polysilicon layer;

[0051] 432 - first upper amorphous silicon layer; 434 - amorphous silicon doping layer;

[0052] 41 - first gate; 42 - gate insulating layer; 43 - first active layer; 44 - source and drain layer;

[0053] 440 - first source; 442 - first drain; 401 - first channel region; 51 - second gate;

[0054] 53 - second active layer; 530 - lower amorphous silicon layer; 201 - pixel point;

[0055] 532 - second upper amorphous silicon layer; 540 - second source; 542 - second drain. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0057] In the description of the present application, it should be understood that the terms "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0058] The present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not indicate the relationship between the various embodiments and / or settings discussed. The detection method of the present application is described in detail below in conjunction with specific examples.

[0059] See also Figure 1-9 , Figure 1-9 A display panel 200 is provided in accordance with the first embodiment of the present invention. The display panel 200 comprises: an array substrate 100, a display device 1 (DISLAY) and a sensing device 2 (SENSOR). The array substrate 100 comprises a substrate 3, a first thin film transistor layer 4 and a second thin film transistor layer 5.

[0060] The substrate 3 may be a rigid material or a flexible material. When the substrate 3 is a rigid material, it may be silicon or glass; when the substrate 3 is a flexible material, it may be PI (polyimide) or PET (polyethylene terephthalate). Preferably, the substrate 3 includes a base plate and a buffer layer; the buffer layer is used to buffer the damage to the base plate caused by the high temperature of crystallization during the manufacturing process of the array substrate 100. The buffer layer is made of an insulating material. For example, the material of the buffer layer may include a single-layer film formed by any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc., or a composite film layer formed by any of multiple materials.

[0061] The first thin film transistor layer 4 is located on the substrate 3. The first thin film transistor layer 4 has a first control thin film transistor 40. The first control thin film transistor 40 includes a first gate electrode 41 formed on the substrate 3, a gate insulating layer 42 formed on the first gate electrode 41, a first active layer 43 formed on the gate insulating layer 42, and a source-drain electrode layer 44 formed on the first active layer 43. The source-drain electrode layer 44 includes a first source electrode 440 and a first drain electrode 442.

[0062] In this embodiment, the first active layer 43 at least includes a polycrystalline silicon layer 430 located on the substrate 3 and a first upper amorphous silicon layer 432 formed on the surface of the polycrystalline silicon layer 430. The polycrystalline silicon layer 430 is obtained by locally crystallizing a preset area of ​​the amorphous silicon layer through a blue laser diode annealing (BLDA) technology. The BLDA technology uses a solid laser, which includes an array-arranged laser light source. When the laser light source is turned on, it can emit a directional light beam with high energy, so that BLDA can achieve local crystallization of the amorphous silicon layer and achieve high electron mobility.

[0063] The BLDA technology has the advantages of high mobility, low cost, local crystallization, and high compatibility with a-Si process, and can be applied to the production of large-size array substrates 100. Compared with traditional a-Si TFT and IGZO TFT, the TFT device produced by the BLDA technology has high electron mobility, can isolate water and oxygen to avoid water and oxygen intrusion, and thus has high stability.

[0064] In this embodiment, the thickness of the polysilicon layer 430 is greater than the thickness of the first upper amorphous silicon layer 432. The thickness of the polysilicon layer 430 is 500-1400 angstroms, and the thickness of the first upper amorphous layer is 100-300 angstroms. This is set to ensure that the grain size in the polysilicon is larger, and the larger particles can improve the electron mobility when used as a TFT device for controlling the display device 1.

[0065] In this embodiment, the first active layer 43 further includes an amorphous silicon doping layer 434 located on the surface of the first upper amorphous silicon layer 432. The function of the amorphous silicon doping layer 434 is to form an ohmic contact with the source-drain electrode layer 44, so that the voltage drop of the first control thin film transistor 40 is not above the contact surface between the source-drain electrode layer 44 and the semiconductor. The first active layer 43 composed of three silicon layers is more conducive to improving electron mobility.

[0066] In this embodiment, the projection of the first upper amorphous silicon layer 432 on the substrate 3 covers the projection of the polycrystalline silicon layer 430 on the substrate 3. That is, the first upper amorphous silicon layer 432 completely covers the polycrystalline silicon layer 430, and such a configuration can prevent the polycrystalline silicon layer 430 from warping; secondly, the leakage current of the first control thin film transistor 40 can also be reduced.

[0067] The display device 1 is connected to the first thin film transistor layer 4, more specifically, connected to the drain of the first control thin film transistor 40. The display device 1 is used to display information, the first control thin film transistor 40 is a control device of the display device 1, and the first control thin film transistor 40 is used to send or receive signals to the display device 1. The display device 1 is a Mini-LED or Micro-LED.

[0068] The second thin film transistor layer 5 is located on the substrate 3, and the second thin film transistor layer 5 has a second control thin film transistor 50. The second thin film transistor layer 5 and the first thin film transistor layer 4 are located in the same layer.

[0069] More specifically, the second control thin film transistor 50 includes a second gate 51 formed on the substrate 3, a gate insulating layer 42 formed on the second gate 51, a second active layer 53 formed on the gate insulating layer 42, and a source-drain electrode layer 44 formed on the second active layer 53. The source-drain electrode layer 44 includes a second source electrode 540 and a second drain electrode 542. The second active layer 53 is located at the same layer as the first active layer 43, and the source-drain electrode layer 44 included in the second control thin film transistor 50 belongs to the same layer as the source-drain electrode layer 44 included in the first control thin film transistor 40. The second active layer 53 includes a lower amorphous silicon layer 530 located at the same layer as the polycrystalline silicon layer 430 and a second upper amorphous silicon layer 532 located on the surface of the lower amorphous silicon layer 530, and the second upper amorphous silicon layer 532 belongs to the same layer as the first upper amorphous silicon layer 432. The second active layer 53 also includes an amorphous silicon doping layer 434 located on the surface of the second upper amorphous silicon layer 532, and the principle is the same as that of the first active layer 43. Since the second control thin film transistor 50 and the first control thin film transistor 40 are located in the same structural layer, the structure of the array substrate 100 is simple. In this embodiment, the first control thin film transistor 40 and the second control thin film transistor 50 are both bottom gate structures.

[0070] In this embodiment, the electron mobility of the first active layer 43 is greater than the electron mobility of the second active layer 53. The first active layer 43 includes a polysilicon layer 430 formed by BLDA technology. The electron mobility of the first active layer 43 is in the range of 50 to 200 cm 2 / Vs; The material of the second active layer 53 is mainly amorphous silicon (a-Si), and the electron mobility of amorphous silicon is about 0.3-1cm 2 / Vs, the second active layer 53 is mainly used to form a TFT for controlling the sensing device 2. The TFT of the sensing device 2 does not have high requirements for electron mobility, but has high requirements for photosensitivity stability, and amorphous silicon as an active layer can just reflect such advantages. Although the electron mobility of low-temperature polysilicon (LTPS) formed by indium gallium zinc oxide (IGZO) in traditional technology can reach 100cm2 / Vs, IGZO is sensitive to water and oxygen, and more importantly, the photosensitivity stability is poor. It is easy to affect the characteristics of thin-film transistors (for example, the starting voltage (threshold voltage)) due to light irradiation, so that the stability is difficult to control when used for the control switch of the sensing device 2. In the present invention, the polycrystalline silicon (p-Si) obtained by the blue laser diode annealing technology is used as the first active layer 43, and its electron mobility ranges from 50 to 200cm 2 / Vs, so such a display panel 200 has a better light-emitting effect when used to drive the display device 1.

[0071] The sensing device 2 is connected to the second thin film transistor layer 5, the sensing device 2 is used to sense external environmental information, and the second control thin film transistor 50 is used to send or receive signals to the sensing device 2. The sensing device 2 is a light sensing device, a pressure sensing device or a temperature sensing device.

[0072] See also Fig. 9 , Fig. 9 A schematic diagram of a top view structure of a pixel (PIXEL) 201 provided for an embodiment of the present invention. The display device 1 is connected to the scan line 210 and the data line 212 included in the display panel 200, and the sensing device 2 is connected to the scan line 210 and the data line 212 included in the display panel 200. Specifically, the first gate 41 in the first control thin film transistor 40 is connected to the scan line 210, the first source 440 or the first drain 442 is connected to the data line 212, and the first drain 442 or the first source 440 is connected to the first pixel electrode 60; the second gate 51 in the second control thin film transistor 50 is connected to the scan line 210, the second source 540 or the second drain 542 is connected to the data line 212, and the second drain 542 or the second source 540 is connected to the second pixel electrode 62.

[0073] In this embodiment, a passivation layer 6 is also formed on the source-drain electrode layer 44. The passivation layer 6 is usually made of inorganic insulating materials such as SiOx, SiNx, SiOxNy, Al2O3, TiOx, Y2O3, etc., and may also be made of an organic insulating layer such as a resin material and an acrylic material. A first pixel electrode 60 and a second pixel electrode 62 are formed on the surface of the passivation layer 6. The display device 1 is connected to the first control thin film transistor 40 through the first pixel electrode 60, and the sensing device 2 is connected to the second control thin film transistor 50 through the second pixel electrode 62.

[0074] See also Figure 1-8 The second embodiment of the present invention further relates to a method for manufacturing an array substrate 100, which comprises the following steps:

[0075] S1: Please refer to Figure 1 , providing a substrate 3; the substrate 3 may be a rigid material or a flexible material. When the substrate 3 is a rigid material, it may be silicon or glass; when the substrate 3 is a flexible material, it may be PI (polyimide) or PET (polyethylene terephthalate).

[0076] S2: A first thin film transistor layer 4 and a second thin film transistor layer 5 in the same layer as the first thin film transistor layer 4 are fabricated on one side of the substrate 3, wherein the first thin film transistor layer 4 has a first control thin film transistor 40; the second thin film transistor layer 5 has a second control thin film transistor 50, wherein the first thin film transistor layer 4 and the second thin film transistor layer 5 are located in the same layer. Fabricating the first thin film transistor layer 4 and the second thin film transistor layer 5 specifically includes the following steps:

[0077] S21: Please continue reading Figure 1 , a first gate 41 and a second gate 51 are formed on the substrate 3. The material of the first gate 41 and the second gate 51 may be a metal or an alloy, and the metal or alloy layer may be formed of metal molybdenum (Mo), metal aluminum (Al), metal copper (Cu), metal tungsten (W) or at least two alloys of metal molybdenum (Mo), metal aluminum (Al), metal copper (Cu), and metal tungsten (W). Preferably, the material of the first gate 41 and the second gate 51 is Mo. The first gate 41 and the second gate 51 are first deposited by a PVD process and then made by a yellow light process and an etching process. The thickness of the first gate 41 and the second gate 51 is 3000 to 8000 angstroms. The first gate 41 is used as a gate of a TFT for controlling the display device 1, and the second gate 51 is used as a gate of a TFT for controlling the sensing device 2.

[0078] S22: Please continue reading Figure 1, a gate insulating layer 42 is deposited on the substrate 3 by plasma enhanced chemical vapor deposition (PECVD), and the gate insulating layer 42 also covers the first gate 41 and the second gate 51. The present invention does not limit the material of the gate insulating layer 42, for example, it can be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), a silicon oxynitride layer (SiON), or a composite layer of a silicon oxide layer and a silicon nitride layer (SiNx). In this embodiment, the gate insulating layer 42 is a composite layer of a silicon oxide layer and a silicon nitride layer (SiNx), with a thickness of 600-1500 angstroms, and is post-treated with N2O after deposition.

[0079] S23: Please refer to Figure 2 A lower amorphous silicon layer 530 is formed on the gate insulating layer 42, and the lower amorphous silicon layer 530 completely covers the gate insulating layer 42. A high-temperature annealing or BLDA pretreatment is performed on the region of the lower amorphous silicon layer 530 corresponding to the first gate 41 to reduce the hydrogen content in the region of the lower amorphous silicon layer 530 corresponding to the first gate 41 to avoid hydrogen explosion during the crystallization of the amorphous silicon. The temperature range of the high-temperature annealing is 350-500°C. If BLDA is used for pretreatment, the energy of BLDA dehydrogenation is recommended to be 250-250kw / cm 2 .

[0080] S24: Please refer to Figure 3 The BLDA technology is used to partially crystallize the region of the lower amorphous silicon layer 530 corresponding to the first gate 41 to obtain a polycrystalline silicon layer 430. The energy range of the BLDA technology to crystallize the amorphous silicon is 350 to 450 kw / cm 2 Since the BLDA technology uses a semiconductor solid laser, the energy of the laser beam emitted by the semiconductor solid laser is much greater than the energy of the existing excimer laser beam, so that the amorphous silicon layer in the area corresponding to the first gate 41 is crystallized to form a polysilicon layer 430 for use as the first channel region 401 of the first control thin film transistor 40, and the electron mobility is high.

[0081] S25: Remove SiOx on the surface of the polysilicon layer 430 by washing with hydrofluoric acid (HFC), then oxidize the polysilicon layer 430 with H2O2 to remove the oxidized SiOx, and then wash with HFC (hydrofluoric acid) to remove SiOx again, see Figure 4-5 After cleaning, a first upper amorphous silicon layer 432 and a second upper amorphous silicon layer 532 are sequentially deposited on the common surface of the lower amorphous silicon layer 530 and the polycrystalline silicon layer 430 , and an amorphous silicon doping layer 434 is deposited on the common surface of the first upper amorphous silicon layer 432 and the second upper amorphous silicon layer 532 .

[0082] After this step, the first active layer 43 of the first control thin film transistor 40 and the second active layer 53 of the second control thin film transistor 50 are formed. The first active layer 43 includes a polysilicon layer 430 , a first upper amorphous silicon layer 432 and an amorphous silicon doping layer 434 .

[0083] The second active layer 53 includes a lower amorphous silicon layer 530 located at the same layer as the polycrystalline silicon layer 430 and a second upper amorphous silicon layer 532 located on the surface of the lower amorphous silicon layer 530, and the second upper amorphous silicon layer 532 belongs to the same layer as the first upper amorphous silicon layer 432. In other words, the second active layer 53 is not crystallized, that is, the active layer of the second control thin film transistor 50 (sensing TFT) is made of amorphous silicon, which can meet the requirements of the sensing stability of the sensing TFT, especially the light-sensing stability, and can prevent the invasion of water and oxygen.

[0084] The amorphous silicon doping layer 434 includes at least two doping layers with different concentrations instead of a single doping layer, which can increase the energy barrier between the source and drain and the semiconductor composite layer, improve the barrier for hole transmission, and reduce the leakage current in the channel region of the switching device. The amorphous silicon doping layer 434 can be an n-type or p-type doped semiconductor layer, which is not limited here. The thickness of the amorphous silicon doping layer 434 is 100 to 500 angstroms.

[0085] S26: Please refer to Figure 6 , a source-drain electrode layer 44 is formed on the amorphous silicon doped layer 434, and the source-drain electrode layer 44 is etched to form a first source electrode 440 and a first drain electrode 442 of the first control thin film transistor 40, and a second source electrode 540 and a second drain electrode 542 of the second control thin film transistor 50, so as to obtain the first thin film transistor layer 4 and the second thin film transistor layer 5. Thus, the area between the first source electrode 440 and the first drain electrode 442 forms the first channel region 401 of the first control thin film transistor 40. The material of the source-drain electrode layer 44 includes but is not limited to one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi, etc. Preferably, the material of the source-drain electrode layer 44 can be a Mo / Al / Mo laminated composite material, which not only meets the low resistance characteristics of the source and drain, but also prevents the source and drain from being invaded by water vapor and affecting their performance.

[0086] S27: Please refer to Figure 7 A passivation layer 6 is formed on the source-drain electrode layer 44. The passivation layer 6 is usually made of inorganic insulating materials such as SiOx, SiNx, SiOxNy, Al2O3, TiOx, Y2O3, etc., and may also be made of organic insulating layers such as resin materials and acrylic materials.

[0087] S28: Please continue reading Figure 7A first pixel electrode 60 and a second pixel electrode 62 are formed on the surface of the passivation layer 6 , and the first pixel electrode 60 is connected to the first control thin film transistor 40 , and the second pixel electrode 62 is connected to the second control thin film transistor 50 .

[0088] S29: Please refer to Figure 8 A display device 1 and a sensing device 2 are arranged on the surface of the passivation layer 6 to obtain a display panel 200. The display device 1 is connected to the first control thin film transistor 40 through the first pixel electrode 60, and the sensing device 2 is connected to the second control thin film transistor 50 through the second pixel electrode 62. The display device 1 is used to display information, such as displaying corresponding image information. The sensing device 2 is used to sense external environmental information. The sensing device 2 is a light sensing device, a pressure sensing device or a temperature sensing device. For example, when the sensing device 2 senses external light information, the display device 1 displays a corresponding graphic.

[0089] In summary, the present invention uses the BLDA technology with the advantages of high mobility, low cost, and high compatibility with amorphous silicon processes to form an array substrate 100 and a display panel 200. The BLDA local laser annealing technology is used to perform laser irradiation dehydrogenation and crystallization on a local area of ​​the amorphous silicon layer to form a first active layer 43 of the first control thin film transistor 40 of a bottom-gate control display device 1, which can achieve the technical advantages of high color gamut, low energy consumption, and light weight of the micro-light-emitting device as the display device 1; the uncrystallized amorphous silicon is used as the second active layer 53 of the second control thin film transistor 50 of the control sensing device 2, which can meet the requirements of the control sensing device 2 for light sensitivity stability and prevent the invasion of water and oxygen.

[0090] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A first thin film transistor layer located on the substrate, wherein the first thin film transistor layer has a first control thin film transistor; as well as A second thin film transistor layer is located on the substrate, and the second thin film transistor layer has a second control thin film transistor, wherein the first thin film transistor layer and the second thin film transistor layer are located in the same layer, and the first control thin film transistor includes a first active layer located on one side of the substrate, and the second control thin film transistor includes a second active layer located on the same layer as the first active layer, the material of the first active layer is different from that of the second active layer, the first active layer includes a polycrystalline silicon layer located on one side of the substrate and a first upper amorphous silicon layer formed on the surface of the polycrystalline silicon layer, the projection of the first upper amorphous silicon layer on the substrate covers the projection of the polycrystalline silicon layer on the substrate; the first active layer also includes an amorphous silicon doping layer located on the surface of the first upper amorphous silicon layer.

2. The array substrate according to claim 1, characterized in that: The second active layer includes a lower amorphous silicon layer located at the same layer as the polysilicon layer and a second upper amorphous silicon layer located on a surface of the lower amorphous silicon layer, and the second upper amorphous silicon layer and the first upper amorphous silicon layer belong to the same layer.

3. The array substrate according to claim 2, characterized in that: The electron mobility of the first active layer is greater than that of the second active layer, and the electron mobility of the first active layer is in the range of 50 to 200 cm 2 / Vs.

4. The array substrate according to claim 1, characterized in that: The thickness of the polysilicon layer is greater than the thickness of the first upper amorphous silicon layer.

5. The array substrate according to claim 1, characterized in that: The first control thin film transistor and the second control thin film transistor are both bottom gate structures.

6. A display panel, characterized in that: include: substrate; A first thin film transistor layer located on the substrate, wherein the first thin film transistor layer has a first control thin film transistor; A display device connected to the first thin film transistor layer, the display device is used to display information, and the first control thin film transistor is used to send or receive signals to the display device; a second thin film transistor layer located on the substrate, wherein the second thin film transistor layer has a second control thin film transistor; as well as A sensing device connected to the second thin film transistor layer, the sensing device is used to sense external environmental information, and the second control thin film transistor is used to send or receive a signal to the sensing device; Among them, the first thin film transistor layer and the second thin film transistor layer are located in the same layer, and the first control thin film transistor includes a first active layer located on one side of the substrate, the second control thin film transistor includes a second active layer located on the same layer as the first active layer, the material of the first active layer is different from the material of the second active layer, the first active layer includes a polycrystalline silicon layer located on one side of the substrate and a first upper amorphous silicon layer formed on the surface of the polycrystalline silicon layer, the projection of the first upper amorphous silicon layer on the substrate covers the projection of the polycrystalline silicon layer on the substrate; the first active layer also includes an amorphous silicon doping layer located on the surface of the first upper amorphous silicon layer.

7. The display panel according to claim 6, characterized in that: The display device is Mini-LED or Micro-LED; the sensing device is a light sensing device, a pressure sensing device or a temperature sensing device.

8. A method for manufacturing an array substrate, characterized in that: The steps include: providing a substrate; as well as A first thin film transistor layer and a second thin film transistor layer located at the same layer are manufactured on one side of the substrate, wherein the first thin film transistor layer has a first control thin film transistor, and the first control thin film transistor includes a first active layer located on one side of the substrate; The second thin film transistor layer has a second control thin film transistor, so that the second active layer included in the second control thin film transistor is located in the same layer as the first active layer, and the material of the first active layer is different from the material of the second active layer, the first active layer includes a polycrystalline silicon layer located on one side of the substrate and a first upper amorphous silicon layer formed on the surface of the polycrystalline silicon layer, the projection of the first upper amorphous silicon layer on the substrate covers the projection of the polycrystalline silicon layer on the substrate; the first active layer also includes an amorphous silicon doping layer located on the surface of the first upper amorphous silicon layer.

9. The method for manufacturing an array substrate according to claim 8, characterized in that: The manufacturing of the first thin film transistor layer comprises the following steps: forming a first gate on the substrate; forming a gate insulating layer on the first gate; forming a lower amorphous silicon layer on the gate insulating layer; Using a blue laser diode annealing technique to locally crystallize a preset area of ​​the lower amorphous silicon layer to obtain a polycrystalline silicon layer; Depositing an amorphous silicon doping layer on the common surface of the lower amorphous silicon layer and the polycrystalline silicon layer; forming a source-drain electrode layer on the amorphous silicon doped layer; as well as The source and drain electrode layer is etched to form a source electrode and a drain electrode, so as to form the first thin film transistor layer.

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