Method for optimizing FBAR cavity flattening defects and cavity-type FBAR and its application

Abstract

The present invention discloses a method for optimizing defects in the FBAR cavity flattening process, comprising: providing a cavity on the surface of a substrate, depositing a sacrificial layer in the cavity; flattening the sacrificial layer so that the dished pits on the surface of the sacrificial layer are positive values to obtain a flattened device; heating the flattened device to 1000°C-1200°C and annealing for 30-60 minutes to obtain a heat-treated device; sputtering a layer of TaN on the surface of the heat-treated device, and polishing the TaN layer to the surface of the substrate using a chemical mechanical polishing method to obtain a second flattened device; depositing a piezoelectric oscillator stack and a metal pad layer on the surface of the second flattened device, and removing the sacrificial layer to obtain a cavity-type FBAR. This method can enable the FBAR resonator to have a more electrode-stable structure and a higher Q value. The present invention also discloses an FBAR resonator prepared using this method, and the application of the FBAR resonator in preparing a wafer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for optimizing FBAR cavity planarization process defects, a cavity-type FBAR and its application. Background Art

[0002] With the rapid development of 5G mobile communication technology, especially the rapid increase in the number of mobile phones and various transceiver devices, the market demand for high-frequency resonators and filters is growing. Although traditional microwave ceramic resonators and surface acoustic wave resonators are relatively mature in technology and have been commercialized earlier, they are widely used in fields such as low-resonance frequency filters and sensors. However, their application in high-frequency fields has been limited in principle. In addition, their power consumption and other performance are far from meeting the needs of today's increasingly miniaturized and ultra-highly integrated terminal devices. Compared with ceramic and surface acoustic wave resonators, film bulk acoustic resonators (FBARs) have the advantages of small size, high resonant frequency, low power loss, high quality factor (Q), and large power capacity. Therefore, they have broad application and development prospects in related fields, especially in the transceiver function of high-frequency communication filters, and have become a hot research topic in industry and academia.

[0003] Currently, there are three main types of mainstream FBAR structures: back-etched, air-gap, and solid-state assembly. From a performance perspective, the first two structures, which use air as the acoustic impedance material, achieve the best Q values. However, from the perspectives of process stability, complexity, yield, and cost, back-etching reduces device robustness due to the large amount of substrate removed. Solid-state assembly requires the preparation of multiple layers of films, resulting in a complex and tedious process and high cost. Therefore, from a performance and process perspective, the air-gap structure has gained widespread industry recognition and is the most common structure in commercial applications.

[0004] The actual manufacturing process of cavity FBAR involves: 1. Cavity fabrication; 2. Sacrificial layer filling; 3. Sacrificial layer polishing; 4. Surface electrode fabrication and subsequent processes; 5. Sacrificial layer release. The surface flatness control of the first three steps will determine the performance of the subsequent devices. The actual chemical mechanical polishing (CMP) process will produce the following differences due to the difference in removal rate between the cavity and the silicon substrate: Figure 1 The cross section of the dishing pit (b) and the canine defect (Fang defect) caused by chemical corrosion of the edge, the cross section is as follows Figure 1 a, and Figure 1 c shows an erosion pit defect. The size of the dishing pit can be controlled by adjusting the pH of the slurry and the abrasive concentration or optimizing the chemical correction time. Fang defects are relatively difficult to solve in the industry. Fang defects will cause steps at the edge of the cavity, such as Figure 2As shown in the figure, under a microscope, the black edge of the device plan view is the Fang defect.

[0005] Therefore, it is urgent to develop a process to reduce Fang defects and Dishing during the manufacturing process of FBAR, to prevent the above defects from affecting the flatness of the lower electrode film and causing loss of device Q value, or even collapse due to unstable electrode structure after the sacrificial layer is released. Summary of the Invention

[0006] The present invention provides a method for optimizing FBAR cavity flattening process defects, which can make the FBAR resonator have fewer Fang defects and Dishing defects, thereby achieving the purpose of stable electrode structure and higher Q value.

[0007] A method for optimizing FBAR cavity planarization process defects, comprising:

[0008] Providing a substrate having a cavity therein, and depositing a sacrificial layer in the cavity;

[0009] The sacrificial layer is planarized by chemical mechanical polishing so that the dished pit value on the surface of the sacrificial layer is positive to obtain a first planarization device;

[0010] The first planarization device is subjected to heat treatment to obtain a heat-treated device, wherein the heat treatment process is: heating to 1000° C.-1200° C. and annealing for 30 min-60 min;

[0011] An inert alloy layer is sputtered on the surface of the heat-treated device, and the inert alloy layer is polished to the substrate surface using chemical mechanical polishing to obtain a second flattening device; a piezoelectric oscillator stack and a metal pad layer are deposited on the surface of the second flattening device, and then the sacrificial layer is removed to obtain a cavity-type FBAR.

[0012] The present invention uses a heat treatment process to make the sacrificial layer flexible so as to fill the steps caused by Fang defects. Since the inert alloy layer is an inert material and it is difficult for it to undergo electrochemical or chemical reactions with the sacrificial layer and the substrate to form new steps, an inert alloy layer is deposited on the surface of the heat-treated device to fill the remaining step space. Based on the above process, the cavity-type FBAR provided by the present invention has fewer Fang defects and Dishing defects, a higher Q value, and a stable structure.

[0013] The substrate material is silicon, silicon carbide, quartz, or lithium molybdate. The sacrificial layer material is phosphorus-doped silicon oxide (PSG), α-Si, or single-crystal silicon. At the heat treatment temperature, the substrate material remains unchanged, while the sacrificial layer becomes fluid enough to fill the steps caused by Fang defects.

[0014] The depth of the cavity is greater than or equal to the thickness of the sacrificial layer.

[0015] The depth of the cavity is 1 μm-10 μm.

[0016] The thickness of the sacrificial layer is 2 μm-20 μm.

[0017] The depth of the cavity is greater than or equal to the thickness of the sacrificial layer. The depth of the cavity is 1 μm-10 μm, and the thickness of the sacrificial layer is 2 μm-20 μm.

[0018] The Dishing value is 30nm-200nm.

[0019] The thickness of the TaN layer is 30nm-200nm.

[0020] The piezoelectric oscillator stack includes a first electrode, a single crystal piezoelectric film and a second electrode. The first electrode is formed on the surface of the substrate and the sacrificial layer, the second electrode is formed on the surface of the single crystal piezoelectric film, and the metal pad layer is respectively located on the first electrode and the second electrode.

[0021] The metal pad layer is divided into a first metal pad layer and a second metal pad layer, the first metal pad layer passes through the single crystal piezoelectric film and is located on the first electrode and is separated from the second electrode;

[0022] The chemical mechanical polishing process parameters of the planarized sacrificial layer so that the dished pits on the surface of the sacrificial layer are positive values are: the suspension pH is 8.0-10.3, the polishing pressure is 4psi-6psi, and the sacrificial layer polishing rate is 6000A / min-9000A / min.

[0023] The chemical mechanical polishing process parameters for polishing the inert alloy layer to the substrate surface to obtain the second flattened device are: polishing liquid pH is 10-12, polishing pressure: 4psi-6psi, inert alloy layer removal rate is 400A / min-600A / min, and the inert alloy layer is TaC, TiN or CrN layer.

[0024] A cavity-type FBAR is prepared by utilizing the method for optimizing the process defects of FBAR cavity flattening. The Q value of the cavity-type FBAR is 1600-2500.

[0025] The application of the cavity-type FBAR in the preparation of circular wafers.

[0026] Houndstooth defects can cause discontinuity in the first electrode of the sputtered layer, or the presence of step defects. After the sacrificial layer below is released, the supporting force at the connection is insufficient, causing the piezoelectric sandwich structure to collapse into the cavity, resulting in device failure. The present invention reduces houndstooth defects, resulting in a higher Q value for the cavity-type FBAR, thereby improving the yield of wafer products.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention controls the fluidity of the sacrificial layer through a heat treatment process to fill the steps caused by Fang, and then uses the inertness of TaN to further flatten the sacrificial layer, reducing Fang defects, improving the Q value of the cavity-type FBAR, and improving the structural stability of the cavity-type FBAR, so that the wafer prepared based on the cavity-type FBAR has a higher yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Figure 1 is a diagram of three common CMP defect types provided in the background technology, wherein: Figure 1 a is Fang defect, Figure 1 b is Dishing defect, Figure 1 c is the corrosion pit defect (Erosion);

[0030] Figure 2 A micrograph of a Fang defect in a sacrificial layer of an FBAR provided in the background art;

[0031] Figure 3 A cross-sectional view of etching a cavity on a silicon wafer and growing a sacrificial layer PSG provided in Example 1;

[0032] Figure 4 This is a cross-sectional view of the sacrificial layer after planarization by chemical mechanical polishing (CMP) provided in Example 1;

[0033] Figure 5 This is a cross-sectional view of the planarized sacrificial layer provided in Example 1 after high-temperature annealing;

[0034] Figure 6 This is a cross-sectional view of the heat treatment device after a layer of TaN is physically sputtered on the surface provided in Example 1;

[0035] Figure 7 A plan view of a TaN surface after CMP polishing provided in Example 1;

[0036] Figure 8 This is a graph showing the surface step profile of the sacrificial layer in the FBAR prepared in Comparative Example 1;

[0037] Figure 9A step profiler data diagram of the surface of a second planarized device prepared by the method for optimizing FBAR cavity planarization process defects provided in Example 1;

[0038] Figure 10 A plane microscope photograph of the sacrificial layer of the second planarization device prepared by the method for optimizing the defects of the FBAR cavity planarization process provided in Example 1. DETAILED DESCRIPTION

[0039] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more apparent. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] Example 1

[0041] A process for preparing a cavity FBAR by optimizing the defects of the FBAR cavity planarization process:

[0042] (1) Figure 3 As shown, a cavity with an area of 200um*200um is photoetched on a substrate. The substrate is a 6-inch silicon wafer, the cavity depth is 3um, the etching gas is SF6, CF4 or N2, and a PSG sacrificial layer with a thickness of 5±0.2um is deposited in the cavity by plasma enhanced chemical vapor deposition (PECVD). The phosphorus content is controlled at 4±0.5%. The appropriate phosphorus content will accelerate the release rate.

[0043] (2) Figure 4 As shown, the sacrificial layer is polished by CMP to make the sacrificial layer flat, wherein the polishing liquid is Z40, the pH is adjusted to 10.3, the polishing rate is 7200 A / min, the Dishing value is 100nm-200nm, and the surface roughness is 0.6nm;

[0044] (3) Figure 5 As shown, the planarized device is placed in a high-temperature furnace and heated to 1000°C-1200°C for annealing for 30min-60min to change the fluidity of PSG so that the flowing PSG fills the steps caused by Fang defects;

[0045] (4) Figure 6 As shown, a layer of TaN is physically sputtered on the surface of the device after heat treatment. The thickness of the TaN layer is 150 nm, and the thickness uniformity (TTV) is 3 nm to further fill the remaining steps.

[0046] (5) Figure 7As shown, the TaN layer is polished by CMP and most of the TaN is removed at a removal rate of 300±10A / min. The second planarized device is obtained by polishing to the surface of the silicon wafer. Figure 9 As shown in the figure, the Fang defect angle has basically disappeared. The bulge in the sacrificial layer area is caused by Dishing. Dishing can be reduced by polishing without affecting the evaluation of the Fang angle. Figure 10 As shown in the figure, there is no "black edge" defect in the plane microscope photo, indicating that the Fang defect is well controlled;

[0047] (6) A first electrode is deposited on the surface of the sacrificial layer of the second planarization device by magnetron sputtering, wherein the first electrode is molybdenum, and a single crystal piezoelectric film is deposited on the surface of the first electrode by magnetron sputtering. A first through hole and a second through hole are provided in the single crystal piezoelectric film, and a first metal pad layer is applied into the first through hole. The material of the metal pad layer is gold, so that the first metal pad layer is connected to the first electrode, and an HF etching solution is added into the second through hole. The sacrificial layer is removed by fumigation to form a cavity, and a second electrode layer is applied to the surface of the single crystal piezoelectric film. The second metal pad layer is deposited on the surface of the second electrode layer to obtain a cavity-type FBAR. The Q value of the cavity-type FBAR is 2400.

[0048] Comparative Document 1

[0049] The difference from the above embodiment 1 is that in step (2) of embodiment 1, the sacrificial layer is polished by CMP to make the sacrificial layer flat, and then step (6) is directly performed to obtain a cavity type FBAR, such as Figure 8 As shown in FIG. 3 , the Fangdefect angle in the CMP-polished sacrificial layer is obvious, and the aspect ratio is about 80 nm / 50 μm.

[0050] Application examples:

[0051] Application of Cavity FBAR in Wafer Preparation

[0052] 1) Cleaning the silicon substrate by ultrasonic washing with acetone and isopropyl alcohol, wherein the orientation of the silicon substrate 300 is (111) or (100);

[0053] 2) using ICP etching based on the BOSCH process to etch a cavity 301 with a depth of 3 μm and a lateral width of 200 μm on the silicon substrate;

[0054] 3) Depositing 3-5 μm of phosphosilicate glass (PSG) as a sacrificial layer material on the surface of the cavity-containing substrate 300 using a conventional low-pressure chemical vapor deposition (LPCVD) process, planarizing the sacrificial layer using the method described in the above embodiment, and repairing the canine tooth defect through a secondary TaN filling and planarization process;

[0055] 4) Depositing 300 nm of metallic molybdenum (ie, the first metal) on the surface of the material obtained in 3) by thermal evaporation or magnetron sputtering, and patterning the surface by plasma or wet etching.

[0056] 5) growing a 350 nm thick layer of non-etchable borosilicate glass (NEBSG) by chemical vapor deposition in step 4), and forming a planarization layer 305 by CMP;

[0057] 6) Photolithographic patterning and plasma etching are performed on the surface of the material obtained in 5) to obtain a groove of the 108 structure, and a 150 nm thick metal tungsten electrode framework structure (i.e., the second metal) is deposited by thermal evaporation or magnetron sputtering, and planarized by chemical mechanical polishing (CMP), thereby obtaining a composite lower electrode layer 302;

[0058] 7) In step 6), a position for the non-piezoelectric region seed layer 309 is left by photolithographic patterning and development, SiO250A is grown by LPCVD, and then the photoresist is removed. The patterned non-piezoelectric layer seed layer and the exposed composite bottom electrode layer 102 are used to grow the piezoelectric layer AlN.

[0059] 8) A 1 μm thick AlN piezoelectric layer with a c-axis orientation is sputtered on the surface of the wafer obtained in 7); due to the presence of the SiO2 seed layer in the non-piezoelectric layer, the AlN tends to grow into amorphous non-piezoelectric layer 306, while the AlN in the area without the SiO2 seed layer maintains the c-axis orientation and grows into a polycrystalline piezoelectric layer AlN 303.

[0060] 9) Depositing a 150nm metal tungsten electrode frame structure layer on the surface of the pattern obtained in 8) by thermal evaporation or magnetron sputtering, and performing photolithographic patterning and plasma etching on the surface of the material to obtain a 307 structure.

[0061] 10) Depositing 250 nm of metal molybdenum by thermal evaporation or magnetron sputtering to form the top electrode 304; and planarizing the composite top electrode layer by CMP.

[0062] 11) The sacrificial layer is removed by wet etching or HF fumigation to form a lateral cavity 301 .

[0063] The sacrificial layer is made of silicon oxide, silicon nitride, organic matter, phosphate glass, doped silicon oxide, or polycrystalline silicon, and has a thickness of 3 μm. In this embodiment, the bottom electrode is 300 nm thick, the top electrode is 250 nm thick, the piezoelectric layer is 1 μm thick, and its lateral width is 5 to 500 μm. The heterogeneous electrode frame is 20 μm wide. The electrodes are made of tungsten and molybdenum in any combination.

Claims

1. A method for optimizing FBAR cavity planarization process defects, characterized in that: include: Providing a substrate having a cavity therein, and depositing a sacrificial layer in the cavity; The sacrificial layer is planarized by chemical mechanical polishing so that the dished pit value on the surface of the sacrificial layer is positive to obtain a first planarization device; The first planarization device is subjected to heat treatment to obtain a heat-treated device, wherein the heat treatment process is: heating to 1000° C.-1200° C. and annealing for 30 min-60 min; sputtering an inert alloy layer on the surface of the heat-treated device, and polishing the inert alloy layer to the substrate surface using chemical mechanical polishing to obtain a second planarization device; depositing a piezoelectric oscillator stack and a metal pad layer on the surface of the second planarization device, and then removing the sacrificial layer to obtain a cavity-type FBAR; The chemical mechanical polishing process parameters for planarizing the sacrificial layer so that the dished pits on the surface of the sacrificial layer are positive and the first planarized device are: suspension pH 8.0-10.3, polishing pressure 4psi-6psi, and sacrificial layer polishing rate 6000A / min-9000A / min; The piezoelectric oscillator stack includes a first electrode, a single crystal piezoelectric film, and a second electrode. The first electrode is formed on the surface of the substrate and the sacrificial layer, the second electrode is formed on the surface of the single crystal piezoelectric film, and the metal pad layer is respectively located on the first electrode and the second electrode. The chemical mechanical polishing process parameters for polishing the inert alloy layer to the substrate surface to obtain the second flattened device are: polishing liquid pH is 10-12, polishing pressure: 4psi-6psi, inert alloy layer removal rate is 400A / min-600A / min, and the inert alloy layer is TaC, TiN or CrN layer.

2. The method for optimizing FBAR cavity planarization process defects according to claim 1, characterized in that: The substrate material is silicon, silicon carbide, quartz sheet or lithium molybdate.

3. The method for optimizing FBAR cavity planarization process defects according to claim 1, characterized in that: The sacrificial layer material is phosphorus-doped silicon oxide, α-Si or single crystal silicon.

4. The method for optimizing FBAR cavity planarization process defects according to claim 1, characterized in that: The thickness of the sacrificial layer is 2 μm-20 μm.

5. The method for optimizing FBAR cavity planarization process defects according to claim 1, characterized in that: The disc-shaped pit value is 30nm-200nm.

6. The method for optimizing FBAR cavity planarization process defects according to any one of claims 1 to 5 for preparing a cavity-type FBAR, characterized in that: The Q value of the cavity-type FBAR is 1600-2500.

7. Application of the method for optimizing FBAR cavity planarization process defects according to claim 6 in preparing cavity-type FBAR in preparing wafers.

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