Parallel power supply protection circuit and electronic equipment

Abstract

The present disclosure relates to the field of power supply technology, and provides a parallel power supply protection circuit and electronic equipment, wherein the parallel power supply protection circuit includes: at least two power supply branches; each power supply branch includes a positive power supply interface, a negative power supply interface, a power NMOS tube, a gate bias circuit, a switch tube and a comparator; the power NMOS tube is connected in series to the negative power supply line, and the drain of the power NMOS tube, the first input end of the comparator and the negative power supply interface are interconnected, the source of the power NMOS tube, the second input end of the comparator and the negative load end are interconnected, the gate of the power NMOS tube is connected to the gate bias end of the gate bias circuit, the output end of the comparator is connected to the control end of the switch tube, and the passage end of the switch tube is connected to the gate bias circuit. The disclosed technical solution not only has very small power loss, but also has strong versatility, and can be applied to the "48V" power supply system.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power supply, and in particular to a parallel power supply protection circuit and electronic equipment. Background Art

[0002] The circuit architecture of multiple power supply units connected in parallel is often used in high-power electronic devices or circuit systems that require backup power to reduce the failure rate.

[0003] A conventional parallel power supply protection circuit is to connect a diode in series on the power line to prevent reverse connection and current backflow. The obvious disadvantage of this circuit is that the diode conduction voltage drop is too large, which causes too much heat loss when the current is large, and it is not suitable for occasions with strict power consumption requirements. Another parallel power supply protection circuit uses NMOS tubes and ORing controllers to realize a circuit close to an ideal diode. Although this method can solve the heat loss problem caused by ordinary diodes, it has a high implementation cost. The forward and reverse withstand voltages of the ORing controller limit its scope of use. In addition, in the communication equipment room, the power distribution scheme often uses a "-48V" power supply system, that is, the power supply "+" is grounded. This method cannot be applied to the above-mentioned "-48V" power supply system. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a parallel power supply protection circuit and an electronic device, which, by adopting a simple circuit structure, simultaneously realizes the anti-current backflow protection, short circuit protection, reverse connection protection and automatic power supply selection of the communication power supply, thereby ensuring the miniaturization, high reliability and low cost of the communication power supply.

[0005] The embodiment of the present disclosure provides a parallel power supply protection circuit, comprising at least two power supply branches; each of the power supply branches comprises a positive power supply interface, a negative power supply interface, a power NMOS tube, a gate voltage bias circuit, a switch tube and a comparator;

[0006] The positive power interface and the negative power interface are used to connect to the power supply unit, the positive power interface is directly connected to the positive end of the load through the positive power line, and the negative power interface is connected to the negative end of the load through the negative power line;

[0007] The power NMOS tube is connected in series to the negative power line, and the drain of the power NMOS tube, the first input end of the comparator and the negative power interface are connected to each other, the source of the power NMOS tube, the second input end of the comparator and the negative load end are connected to each other, the gate of the power NMOS tube is connected to the gate bias end of the gate bias circuit, the output end of the comparator is connected to the control end of the switch tube, and the passage end of the switch tube is connected to the gate bias circuit;

[0008] When the source voltage of the power NMOS tube is greater than the drain voltage of the power NMOS tube, the comparator outputs a first control signal to enable the switch tube to control the gate voltage bias circuit to provide a gate voltage for the power NMOS tube; when the source voltage of the power NMOS tube is less than the drain voltage of the power NMOS tube, the comparator outputs a second control signal to enable the switch tube to control the gate voltage bias circuit to stop providing a gate voltage for the power NMOS tube.

[0009] In the circuit provided by the embodiment of the present disclosure, the first end of the gate bias circuit is connected to the positive end of the load, the first path end of the switch tube is connected to the gate bias end, and the second end of the gate bias circuit, the second path end of the switch tube and the negative end of the load are connected to each other.

[0010] In the circuit provided by the embodiment of the present disclosure, the switch tube is an NMOS tube, the first channel end of the switch tube is the drain, the second channel end of the switch tube is the source, the control end of the switch tube is the gate, the first input end of the comparator is the non-inverting input end, and the second input end of the comparator is the inverting input end.

[0011] The circuit provided in the embodiment of the present disclosure also includes a voltage limiting circuit connected between the drain of the power NMOS tube and the input terminal of the comparator, which is used to limit the voltage difference between the first input terminal and the second input terminal of the comparator.

[0012] In the circuit provided by the embodiment of the present disclosure, the voltage limiting circuit includes a first resistor and a diode, the first end of the first resistor is connected to the drain of the power NMOS tube, the second end of the first resistor, the anode of the diode and the first input end of the comparator are connected to each other, and the cathode of the diode is connected to the second input end of the comparator.

[0013] In the circuit provided by the embodiment of the present disclosure, the resistance range of the first resistor is 10 5 Up to 10 6 Ohm magnitude.

[0014] The circuit provided in the embodiment of the present disclosure also includes a power supply circuit connected to the positive power terminal of the comparator, which is used to supply power to the comparator and limit the amplitude of the high level output by the comparator.

[0015] In the circuit provided by the embodiment of the present disclosure, the power supply circuit includes a second resistor and a voltage-stabilizing diode, the first end of the second resistor is connected to the positive electrode interface of the power supply, the second end of the second resistor is connected to the cathode of the voltage-stabilizing diode, and the anode of the voltage-stabilizing diode is connected to the negative terminal of the load.

[0016] In the circuit provided by the embodiment of the present disclosure, the negative power terminal of the comparator is connected to the negative power terminal of the load.

[0017] An embodiment of the present disclosure further provides an electronic device, comprising a device body and any one of the parallel power supply protection circuits described above; the device body comprises the load positive terminal and the load negative terminal.

[0018] The technical solution provided by the embodiment of the present disclosure has the following advantages compared with the prior art: a power NMOS tube is connected in series on the negative power line, the drain of the power NMOS tube is connected to the first input terminal of the comparator, the source of the power NMOS tube is connected to the second input terminal of the comparator, the output terminal of the comparator is connected to the control terminal of the switch tube, the passage terminal of the switch tube is connected to the gate bias circuit, and the gate of the power NMOS tube is connected to the gate bias terminal of the gate bias circuit. In this way, once the drain voltage of the power NMOS tube is greater than the source voltage, that is, there is a current backflow trend or the power supply unit is reversed, the comparator controls the gate bias circuit through the switch tube to stop providing the gate voltage to the power NMOS tube, so that the power NMOS tube is turned off. At this time, the power NMOS tube is equivalent to a reverse-biased diode, and its equivalent resistance is very large, thereby preventing current backflow and effectively preventing the power supply unit from being reversed. Moreover, the on-resistance of the power NMOS tube when it is fully turned on is only in the milliohm range, and the on-resistance is extremely small, so that the power loss is very small. More importantly, the ground of the power supply system is not restricted by the components in the parallel power supply protection circuit disclosed in the present invention, and the positive pole can be grounded or the negative pole can be grounded. Therefore, the parallel power supply protection circuit disclosed in the present invention has strong versatility and can be applied to the "-48V" power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 This is a simplified structural diagram of an existing parallel power supply protection circuit;

[0022] Figure 2 It is a simplified structural diagram of another existing parallel power supply protection circuit;

[0023] Figure 3 A structural block diagram of a parallel power supply protection circuit provided in an embodiment of the present disclosure;

[0024] Figure 4 A structural block diagram of another power supply branch in the parallel power supply protection circuit provided in an embodiment of the present disclosure;

[0025] Figure 5 A structural block diagram of another power supply branch in the parallel power supply protection circuit provided in an embodiment of the present disclosure;

[0026] Figure 6 A circuit diagram of a parallel power supply protection circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0028] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0029] Figure 1 The circuit structure shown is a conventional parallel power supply protection circuit, in which diodes are connected in series on the positive power lines of each power supply unit (power supply). For example, diode D5 is connected in series on the positive power line of power supply unit PSU1, and diode D4 is connected in series on the positive power line of power supply unit PSU2. Diodes are used to prevent reverse connection and backflow of current. However, the conduction voltage drop of the diode is too large, and the heat loss is too large when the current is large. It is not suitable for occasions with strict power consumption requirements. Figure 2 The circuit structure shown is another conventional parallel power supply protection circuit, in which NMOS tubes are connected in series on the positive power lines of each power supply unit, for example, NMOS tube K1 is connected in series on the positive power line of power supply unit PSU1, and NMOS tube K2 is connected in series on the positive power line of power supply unit PSU2, and an ORing controller is connected in parallel to the NMOS tube to realize a circuit close to an ideal diode. This circuit structure solves the heat consumption problem of ordinary diodes while preventing reverse connection and current backflow, but the access method of the ORing controller and the NMOS tube limits the power supply unit to adopt the negative grounding method, resulting in the circuit being unsuitable for power supply systems with positive grounding of the power supply unit, such as communication systems.

[0030] In view of the above technical problems, the embodiments of the present disclosure provide a parallel power supply protection circuit. Specifically, Figure 3 FIG. 1 is a structural block diagram of a protection circuit for connecting two power supply units in parallel according to an embodiment of the present disclosure. Figure 3As shown, the circuit includes at least two power supply branches 10 (only two power supply branches are schematically shown in the figure); each power supply branch 10 includes a positive power supply interface IN+, a negative power supply interface IN-, a power NMOS tube 11, a gate voltage bias circuit 12, a switch tube 13 and a comparator 14; the positive power supply interface IN+ and the negative power supply interface IN- are used to access the power supply unit, the positive power supply interface IN+ is directly connected to the positive end of the load through the positive power line, and the negative power supply interface IN- is connected to the negative end of the load through the negative power line; the power NMOS tube 11 is connected in series to the negative power line, and the drain D of the power NMOS tube 11, the first input terminal A1 of the comparator 14 and the negative power supply interface IN- are connected to each other, and the source S of the power NMOS tube 11, the source S of the comparator 14 The second input terminal A2 and the negative terminal of the load are connected to each other, the gate G of the power NMOS tube 11 is connected to the gate bias terminal C1 of the gate bias circuit 12, the output terminal A3 of the comparator 14 is connected to the control terminal B1 of the switch tube 13, and the first channel terminal B2 of the switch tube 13 is connected to the gate bias circuit 12; when the source voltage of the power NMOS tube 11 is greater than the drain voltage of the power NMOS tube 11, the comparator 14 outputs a first control signal to enable the switch tube 13 to control the gate bias circuit 12 to provide a gate voltage for the power NMOS tube 11; when the source voltage of the power NMOS tube 11 is less than the drain voltage of the power NMOS tube 11, the comparator 14 outputs a second control signal to enable the switch tube 13 to control the gate bias circuit 12 to stop providing a gate voltage for the power NMOS tube 11.

[0031] In the above-mentioned parallel power supply protection circuit, the power NMOS tube 11 is a high-power NMOS tube, so that it can work for a long time in a high-power environment (such as powering a high-power electronic device) while reducing heat power consumption. In the disclosed embodiment, the comparator 14 is composed of an ordinary operational amplifier working in an open-loop state, and the first control signal and the second control signal output by the comparator 14 are high level or low level. Correspondingly, the switch tube 13 is a voltage-controlled switch device, such as a MOS tube. Optionally, the first input terminal A1 of the comparator 14 is a non-inverting input terminal, and the second input terminal A2 of the comparator 14 is an inverting input terminal. At this time, when the drain voltage of the power NMOS tube 11 is greater than the source voltage, that is, the voltage of the non-inverting input terminal of the comparator 14 is greater than the voltage of the inverting input terminal of the comparator 14, the second control signal output by the comparator 14 is a high level. Alternatively, the first input terminal A1 of the comparator 14 is an inverting input terminal, and the second input terminal A2 of the comparator 14 is a non-inverting input terminal. At this time, when the drain voltage of the power NMOS tube 11 is greater than the source voltage, that is, the voltage of the inverting input terminal of the comparator 14 is greater than the voltage of the non-inverting input terminal of the comparator 14, the second control signal output by the comparator 14 is a low level. This embodiment does not limit the type and connection structure of the switch tube. Corresponding to the two settings of the input terminal of the comparator 14, as long as the switch tube 13 can output the first control signal based on the comparator 14, the gate voltage bias circuit 12 is controlled to provide the gate voltage for the power NMOS tube 11, and the gate voltage bias circuit 12 is controlled to stop providing the gate voltage for the power NMOS tube 11 based on the output of the second control signal by the comparator 14. In addition, it can be understood that since the power NMOS tube 11 is connected in series to the negative power supply line, the withstand voltage of the power NMOS tube 11 needs to be greater than the working voltage of the load.

[0032] Based on the above technical solution, the working principle of the parallel power supply protection circuit is as follows: for any power supply branch 10, when the power supply unit is correctly connected to the parallel power supply protection circuit, that is, the positive pole of the power supply unit is connected to the positive pole interface IN+ of the power supply, and the negative pole of the power supply unit is connected to the negative pole interface IN- of the power supply, and the power supply is normal, the source voltage of the power NMOS tube 11 will be slightly greater than its drain voltage. At this time, the voltage of the first input terminal A1 of the comparator 14 is less than the voltage of the second input terminal A2 of the comparator 14. The comparator 14 outputs a first control signal by comparing the voltage of the first input terminal A1 of the comparator 14 with the voltage of the second input terminal A2 of the comparator 14. The switch tube 13 turns itself off or on based on the first control signal, so that the gate voltage bias circuit 12 provides a gate voltage for the power NMOS tube 11, thereby ensuring the normal operation of the power NMOS tube 11. When the corresponding power supply unit is reversely connected or there is a current backflow trend, the drain voltage of the power NMOS tube 11 will be greater than its source voltage. At this time, the voltage of the first input terminal A1 of the comparator 14 is greater than the voltage of the second input terminal A2 of the comparator 14. The comparator 14 outputs a second control signal by comparing the voltage of the first input terminal A1 of the comparator 14 with the voltage of the second input terminal A2 of the comparator 14. The switch tube 13 turns itself on or off based on the second control signal, so that the gate voltage bias circuit 12 stops providing the gate voltage to the power NMOS tube 11. At this time, the gate voltage of the power NMOS tube 11 is close to 0, and the power NMOS tube 11 is in a closed state, which is equivalent to a reverse-biased diode. The reverse-biased equivalent resistance is very large, thereby preventing current from flowing from the drain D of the power NMOS tube 11 to the source S. It should be noted that, at the moment of power-on, the internal body diode of the power NMOS tube 11 is forward-conducted, and then, the gate voltage bias circuit 12 provides the power NMOS tube 11 with a fully-conducting gate voltage, so that the internal body diode is bypassed and no current flows. The power NMOS tube 11 is fully turned on and the on-resistance when fully turned on is only a few ohms to tens of ohms, and the power loss is very small.

[0033] In addition, the parallel power supply protection circuit provided in the embodiment of the present disclosure can also be applied to scenarios where power backup is required. Specifically, when the power supply voltage of the power supply unit corresponding to one of the power supply branches 10 is low, the difference between the drain voltage and the source voltage of the power NMOS tube 11 in the power supply branch 10 is the difference between the higher power supply voltage and the lower power supply voltage, and is greater than zero. In this way, through the cooperation of the comparator 14, the switch tube 13 and the gate voltage bias circuit 12, the power NMOS tube 11 in the power supply branch 10 is turned off, so that the power supply unit connected to the power supply branch 10 becomes a backup power supply. When the voltages of the power supply units are the same or very similar, due to the voltage drop in the power transmission line, the voltage reaching the load power port is exactly the same, and the power supply units will provide current to the load. It can be understood that the closer the voltages of the power supply units are, the closer the output currents are.

[0034] The parallel power supply protection circuit provided in the above embodiment has a power NMOS tube connected in series on the negative power supply line, the drain of the power NMOS tube is connected to the first input terminal of the comparator, the source of the power NMOS tube is connected to the second input terminal of the comparator, the output terminal of the comparator is connected to the control terminal of the switch tube, the passage terminal of the switch tube is connected to the gate voltage bias circuit, and the gate of the power NMOS tube is connected to the gate voltage bias terminal of the gate voltage bias circuit. In this way, once the drain voltage of the power NMOS tube is greater than the source voltage, that is, there is a current backflow trend or the power supply unit is reversed, the comparator controls the gate voltage bias circuit through the switch tube to stop providing the gate voltage to the power NMOS tube, so that the power NMOS tube is turned off. At this time, the power NMOS tube is equivalent to a reverse biased diode, and its equivalent resistance is very large, thereby preventing current backflow and effectively preventing the power supply unit from being reversed. Moreover, the on-resistance of the power NMOS tube when it is fully turned on is only in the milliohm range, and the on-resistance is extremely small, so that the power loss is very small. More importantly, the ground of the power supply system is not restricted by the components in the parallel power supply protection circuit disclosed in the present invention, and the positive pole can be grounded or the negative pole can be grounded. Therefore, the parallel power supply protection circuit disclosed in the present invention has strong versatility and can be applied to the "-48V" power supply system.

[0035] In some embodiments, the first end of the gate bias circuit is connected to the positive end of the load, the first channel end of the switch tube is connected to the gate bias end, and the second end of the gate bias circuit, the second channel end of the switch tube and the negative end of the load are interconnected.

[0036] For details, see Figure 3, connect the first end C2 of the gate bias circuit 12 to the positive end of the load, connect the first channel end B2 of the switch tube 13 to the gate bias end C1, and connect the second end C3 of the gate bias circuit 12, the second channel end B3 of the switch tube 13 and the negative end of the load to each other. In this way, on the one hand, when the control end B1 of the switch tube 13 receives the first control signal, the first channel end B2 to the second channel end B3 of the switch tube 13 is in an open circuit state, and the voltage divided between the second end C3 of the gate bias circuit 12 and the gate bias end C1 provides a gate voltage for the power NMOS tube 11; when the control end B1 of the switch tube 13 receives the second control signal, the first channel end B2 to the second channel end B3 of the switch tube 13 is in a short circuit state, and the part between the second end C3 of the gate bias circuit 12 and the gate bias end C1 is bypassed, which is equivalent to the gate G of the power NMOS tube 11 being directly connected to the negative terminal of the load, and the gate voltage of the power NMOS tube 11 is close to 0; thereby, the switch tube 13 controls the closing and conducting of the power NMOS tube 11 through the gate bias circuit 12. On the other hand, the first channel end B2 of the switch tube 13 is connected to the gate bias end C1, and the second channel end B3 of the switch tube 13 is connected to the negative end of the load, which is equivalent to connecting the first channel end B2 of the switch tube 13 to the gate G of the power NMOS tube 11, and connecting the second channel end B3 of the switch tube 13 to the source of the power NMOS tube 11, so that the switch tube 13 does not need a very high withstand voltage, but only needs to be greater than the gate withstand voltage of the power NMOS tube 11. In some embodiments, the gate bias circuit 12 can be a resistor voltage divider circuit.

[0037] Further, the switch tube is an NMOS tube, the first channel end of the switch tube is the drain, the second channel end of the switch tube is the source, the control end of the switch tube is the gate, the first input end of the comparator is the in-phase input end, and the second input end of the comparator is the inverting input end. In this way, by setting the switch tube to an ordinary small signal N-channel MOS tube, while realizing the conduction and shutdown of the power NMOS tube, the response speed of the switch is improved and the thermal power consumption of the switch tube is reduced. Specifically, based on the above embodiment, when the drain voltage of the power NMOS tube is less than its source voltage, the comparator outputs a low level, so that the gate of the switch tube has no conduction voltage and its source to drain is in an open circuit state, thereby not affecting the normal operation of the power NMOS tube; when the drain voltage of the power NMOS tube is greater than its source voltage, the comparator outputs a high level, so that the switch tube is fully turned on, the source and drain of the switch tube are equivalent to a short circuit, and the gate bias circuit is bypassed, so that the gate voltage of the power NMOS tube is close to 0, and the power NMOS tube is turned off, thereby preventing current backflow.

[0038] Based on the above technical solution, in some embodiments, the parallel power supply protection circuit may also include a voltage limiting circuit connected between the drain of the power NMOS tube and the input of the comparator, for limiting the voltage difference between the first input and the second input of the comparator.

[0039] Specifically, Figure 4 The figure shows the structure of another power supply branch in the parallel power supply protection circuit. Figure 4 As shown, the parallel power supply protection circuit also includes a voltage limiting circuit 15, which is connected between the drain D of the power NMOS tube 11 and the input end (including the first input end A1 and the second input end A2) of the comparator 14. Considering that when the power supply unit is short-circuited or reversely connected, the voltage difference between the drain and the source of the power NMOS tube 11 in the corresponding power supply branch 10 will be greater than or equal to the voltage of the power supply unit. If the voltage limiting circuit 15 is not provided between the drain D of the power NMOS tube 11 and the input end of the comparator 14, the voltage difference between the first input end A1 and the second input end A2 of the comparator 14 will be very large, so as to damage the comparator 14. Therefore, by providing the voltage limiting circuit 15 between the drain D of the power NMOS tube 11 and the input end of the comparator 14, the voltage difference between the first input end A1 and the second input end A2 of the comparator can be limited to a smaller range, so as to avoid the large input voltage difference from damaging the comparator 14 when the power supply unit is short-circuited or reversely connected. Optionally, the voltage limiting circuit includes a first resistor and a diode, the first end of the first resistor is connected to the drain of the power NMOS tube, the second end of the first resistor, the anode of the diode and the first input end of the comparator are connected to each other, and the cathode of the diode is connected to the second input end of the comparator. In this way, the voltage difference between the first input end A1 and the second input end A2 of the comparator can be limited to the conduction voltage of the diode (such as 0.7V). Further, the resistance range of the first resistor is 10 5 Up to 10 6 The order of magnitude of the first resistor is equal to the order of magnitude of the equivalent resistance of the reverse-biased diode when the power NMOS tube is turned off. In this way, when the power NMOS tube is turned off due to abnormal access to the power supply unit or a current backflow trend, the reverse-biased diode equivalent to the power NMOS tube when it is turned off is connected in parallel with the voltage limiting circuit. Since the order of magnitude of the first resistor is equal to the order of magnitude of the equivalent resistance of the reverse-biased diode, there is only a very weak reverse current, which will not affect the load or the power supply unit.

[0040] In some embodiments, the parallel power supply protection circuit may further include a power supply circuit for the comparator, which is connected to the positive terminal of the power supply of the comparator, and is used to supply power to the comparator and limit the amplitude of the high level output by the comparator.

[0041] Specifically, Figure 5The figure shows the structure of another power supply branch in the parallel power supply protection circuit. Figure 5 As shown, the power supply circuit 16 is connected to the positive power supply terminal of the comparator 14. By setting the power supply circuit 16, the amplitude of the high level output by the comparator 14 can be limited, thereby ensuring that the switch tube 13 will not burn out due to excessive gate voltage. Optionally, the power supply circuit includes a second resistor and a voltage regulator diode, the first end of the second resistor is connected to the positive power supply interface, the second end of the second resistor is connected to the cathode of the voltage regulator diode, and the anode of the voltage regulator diode is connected to the negative load terminal. In this way, the first end of the second resistor is connected to the positive power supply interface, so that the second resistor directly draws power from the power supply unit, and the voltage regulator diode enables the comparator to operate within a safe voltage range and limits the amplitude of the high level output by the comparator. In addition, the power supply circuit may also include a filter capacitor connected in parallel with the voltage regulator diode for filtering the voltage.

[0042] In some embodiments, the negative power terminal of the comparator is connected to the negative load terminal, so as to avoid burning the comparator due to reverse connection of the power supply unit when the negative power terminal of the comparator is connected to the negative power interface.

[0043] In specific implementation, the comparator can be a single-power operational amplifier, that is, two or more comparators are integrated into one, a positive power pin and a negative power pin are led out, and a power supply is powered by a power supply, and the pins of each comparator are connected to the corresponding power supply branch. In addition, the embodiment of the present disclosure can also use two or more independent comparators, each of which is powered separately.

[0044] Based on the above embodiments, in a specific embodiment of the present disclosure, a parallel power supply protection circuit for two power supply branches is provided. Figure 6 The circuit diagram of the parallel power supply protection circuit provided by the embodiment of the present disclosure is shown in FIG. Figure 6As shown, the comparator is a single-power operational amplifier, including comparator U1A and comparator U1B, the power supply unit includes PSU1 and PSU2, one of the power supply branches includes power interface Power Port1, power NMOS tube K1, comparator U1A, a first voltage limiting circuit, a first power supply circuit, a switch tube K2 and a first gate voltage bias circuit, wherein the first voltage limiting circuit includes a resistor R3 (corresponding to the first resistor) and a diode D1, the first power supply circuit includes a resistor R4 (corresponding to the second resistor), a voltage regulator diode D2 and a filter capacitor C1, and the first gate voltage bias circuit includes a resistor R1 and a resistor R2 connected in series. Another power supply branch includes a power supply interface Power Port2, a power NMOS tube K3, a comparator U1B, a second voltage limiting circuit, a second power supply circuit, a switch tube K2, and a second gate bias circuit, wherein the second voltage limiting circuit includes a resistor R7 (corresponding to the first resistor) and a diode D3. Since the comparator is a single-power operational amplifier, the second power supply circuit is the same as the first power supply circuit, that is, the second power supply circuit includes a resistor R4 (corresponding to the second resistor), a voltage stabilizing diode D2, and a filter capacitor C1, and the second gate bias circuit includes a resistor R5 and a resistor R6 connected in series. Interface 1 of the power supply interface Power Port1 and the power supply interface Power Port2 are both positive power supply interfaces, and interface 2 are both negative power supply interfaces. The switch tube K2 and the switch tube K4 are switch MOS tubes.

[0045] Specifically, the power NMOS tube K1 (or K3) is connected in series to the negative power line, so the withstand voltage of the power NMOS tube K1 (or K3) needs to be higher than the working voltage of the load LOAD. The source of the power NMOS tube K1 (or K3) is connected to the negative end of the load LOAD, and the drain is connected to the "-" end of PSU1 (or PSU2). The gate voltage of the power NMOS tube is provided by the two resistors R1 and R2 (or R5 and R6) of the gate bias circuit from the positive and negative power supply ends on the load side. The two positive power lines are connected together, and the negative power line is connected to the drain of the power NMOS tube K1 (or K3). At the moment of power-on, the internal body diode of the power NMOS tube K1 (or K3) is forward-conducted, and then the gate bias circuit R1 and R2 (or R5 and R6) provide the power NMOS tube K1 (or K3) with a fully conductive gate voltage, so that the internal body diode is equivalent to being bypassed and no current flows. When the power NMOS tube K1 (or K3) is fully turned on, the on-resistance is only a few mΩ to tens of mΩ, and the power loss is very small.

[0046] The gate voltage of the power NMOS tube K1 (or K3) is controlled by the switch MOS tube K2 (or K4). The switch MOS tube K2 (or K4) is a common small signal N-channel MOS tube. The drain and source are respectively connected to the two ends of the low potential resistor R2 (or R6) of the gate bias circuit of the power NMOS tube K1 (or K3) (i.e., the gate and source of the power NMOS tube). Therefore, the switch MOS tube K2 (or K4) does not need a very high drain-source withstand voltage, but only needs to be greater than the gate voltage of the power NMOS tube K1 (or K3). The gate of the switch MOS tube K2 (or K4) is directly driven by the output end of the comparator U1A (or U1B). The inverting input end of the comparator is connected to the source level of the power NMOS tube K1 (or K3) (i.e., the working ground GND_SIGNAL of the op amp chip), and the non-inverting input end detects the drain of the power NMOS tube K1 (or K3) after voltage limiting.

[0047] When the circuit is working normally, the current direction of the power NMOS tube K1 (or K3) is from the source to the drain and then to the "-" pole of PSU1 (or PSU2), then the source voltage must be slightly greater than the drain voltage, that is, the voltage at the inverting input terminal of the comparator U1A (or U1B) is greater than the voltage at the non-inverting input terminal, then the comparator U1A (or U1B) outputs a low level, so that the gate of the switch MOS tube K2 (or K4) has no conduction voltage and its drain and source are in an open circuit state, thereby not affecting the normal operation of the power NMOS tube K1 (or K3).

[0048] When the power NMOS tube K1 (or K3) has a current trend from the drain to the source, that is, the drain voltage is greater than the source voltage, that is, the voltage at the non-inverting input terminal of the comparator is greater than the voltage at the inverting input terminal, the comparator outputs a high level, driving the switch MOS tube K2 (or K4) to be fully turned on, and the drain and source of the switch MOS tube K2 (or K4) are equivalent to a short circuit, that is, the low potential resistor R2 (or R6) of the gate voltage bias circuit of the power NMOS tube is equivalent to being bypassed, that is, the gate voltage of the high-power NMOS tube K1 (or K3) is close to 0, and the power NMOS tube K1 (or K3) is in a closed state. At this time, the power NMOS tube K1 (or K3) is equivalent to a reverse-biased diode, and the reverse-biased equivalent resistance is very large, thereby preventing this current backflow.

[0049] Furthermore, when the voltage of one of the PSUs is low, the drain-source voltage difference of the power NMOS tube connected to the PSU is the difference between the voltages of the higher voltage PSU and the lower voltage PSU, which is greater than zero, so that the power NMOS tube connected to the lower voltage PSU unit is turned off, and the lower voltage PSU becomes a backup power supply. When the voltages of the two power supply units are the same or very close, due to the voltage drop of the power transmission line, the voltage reaching the power port of the electronic device is exactly the same, and both PSUs will provide current to the load LOAD.

[0050] When one of the PSUs is short-circuited and the other PSU is connected normally, the drain-source voltage difference of the power NMOS tube on the power supply branch corresponding to the short-circuited PSU is the voltage of the other PSU, then the power NMOS tube on the power supply branch is turned off, and the power NMOS tube is equivalent to a reverse-biased diode, which is connected in parallel with the comparator input voltage limiting circuit. The resistor R3 (or R7) in the voltage limiting circuit is a large resistor of about 1MΩ, which is of the same order of magnitude as the reverse-biased equivalent resistance of the diode. Therefore, there is only a very weak reverse current, which will not affect the load LOAD or PSU.

[0051] When one of the PSUs is reversely connected and the other PSU is connected normally, the drain-source voltage difference of the power NMOS tube on the power supply branch corresponding to the reverse-connected PSU is the sum of the voltages of the two PSUs. Therefore, the drain-source withstand voltage of the power NMOS tube should be greater than twice the input voltage. At the same time, the comparator is protected by adding a voltage limiting circuit at the input end.

[0052] When both PSUs are reversely connected, the two power NMOS tubes are reverse biased and cut off, there is no voltage on the load LOAD side, the comparator has no supply voltage, and the entire circuit is protected.

[0053] In the disclosed embodiment, both the input voltage and the supply voltage of the comparator are limited by a very simple resistor and diode circuit, which has a simple structure and low cost, so that the withstand voltage of the entire circuit is not limited by the peripheral devices of the power NMOS tube. As long as the drain-source withstand voltage of the power NMOS tube is sufficient, the entire circuit can be easily operated at a higher voltage, which can be fully applicable to the power supply system with a voltage range of 36V to 72V commonly used in communication equipment rooms.

[0054] Based on the above embodiments, an embodiment of the present disclosure further provides an electronic device, which includes a device body and a parallel power supply protection circuit as provided in any embodiment of the present disclosure; in an embodiment of the present disclosure, the device body is the load in the above embodiments, and the device body includes a positive terminal of the load and a negative terminal of the load.

[0055] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0056] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parallel power supply protection circuit, characterized in that: It comprises at least two power supply branches; each of the power supply branches comprises a positive power supply interface, a negative power supply interface, a power NMOS tube, a gate bias circuit, a switch tube and a comparator; The positive power interface and the negative power interface are used to connect to the power supply unit, the positive power interface is directly connected to the positive end of the load through the positive power line, and the negative power interface is connected to the negative end of the load through the negative power line; The power NMOS tube is connected in series to the negative power line, and the drain of the power NMOS tube, the first input end of the comparator and the negative power interface are connected to each other, the source of the power NMOS tube, the second input end of the comparator and the negative load end are connected to each other, the gate of the power NMOS tube is connected to the gate bias end of the gate bias circuit, the output end of the comparator is connected to the control end of the switch tube, and the passage end of the switch tube is connected to the gate bias circuit; When the source voltage of the power NMOS tube is greater than the drain voltage of the power NMOS tube, the comparator outputs a first control signal, the switch tube is in a first switch state, and the gate voltage bias circuit provides a gate voltage for the power NMOS tube; when the source voltage of the power NMOS tube is less than the drain voltage of the power NMOS tube, the comparator outputs a second control signal, the switch tube is in a second switch state, and the gate voltage bias circuit stops providing a gate voltage for the power NMOS tube; The first end of the gate bias circuit is connected to the positive terminal of the load, the first channel end of the switch tube is connected to the gate bias end, and the second end of the gate bias circuit, the second channel end of the switch tube and the negative terminal of the load are connected to each other.

2. The parallel power supply protection circuit according to claim 1, characterized in that: The switch tube is an NMOS tube, the first channel end of the switch tube is a drain, the second channel end of the switch tube is a source, the control end of the switch tube is a gate, the first input end of the comparator is a non-inverting input end, and the second input end of the comparator is an inverting input end.

3. The parallel power supply protection circuit according to claim 2, characterized in that: It also includes a voltage limiting circuit, which is connected between the drain of the power NMOS tube and the input end of the comparator and is used to limit the voltage difference between the first input end and the second input end of the comparator.

4. The parallel power supply protection circuit according to claim 3, characterized in that: The voltage limiting circuit includes a first resistor and a diode, the first end of the first resistor is connected to the drain of the power NMOS tube, the second end of the first resistor, the anode of the diode and the first input end of the comparator are connected to each other, and the cathode of the diode is connected to the second input end of the comparator.

5. The parallel power supply protection circuit according to claim 4, characterized in that: The resistance range of the first resistor is 10 5 Up to 10 6 Ohm magnitude.

6. The parallel power supply protection circuit according to claim 2, characterized in that: It also includes a power supply circuit connected to the positive power supply terminal of the comparator, which is used to supply power to the comparator and limit the amplitude of the high level output by the comparator.

7. The parallel power supply protection circuit according to claim 6, characterized in that: The power supply circuit includes a second resistor and a voltage regulator diode, the first end of the second resistor is connected to the positive electrode interface of the power supply, the second end of the second resistor is connected to the cathode of the voltage regulator diode, and the anode of the voltage regulator diode is connected to the negative terminal of the load.

8. The parallel power supply protection circuit according to claim 1, characterized in that: The negative power terminal of the comparator is connected to the negative load terminal.

9. An electronic device, characterized in that: It comprises a device body and a parallel power supply protection circuit as described in any one of claims 1 to 8; the device body comprises the load positive terminal and the load negative terminal.

Images