Atomic layer etching and ion beam etching patterning

By combining atomic layer etching and ion beam etching methods, the difficulty of etching small feature size MRAM stacks in the existing technology is solved, effective etching and sidewall cleaning of high aspect ratio features are achieved, and the patterning quality of MRAM devices is improved.

CN114430858BActive Publication Date: 2025-10-03LAM RES CORP
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Patent Information

Application Number
CN202080064672.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-09-17
Filing Date
2020-09-09
Publication Date
2025-10-03
Estimated Expiration
2040-09-09

AI Technical Summary

Technical Problem

Existing technologies have difficulty in effectively etching tiny CDs less than 100 nm or tight-pitch MRAM stacks, resulting in tapered profiles and sidewall redeposition, causing device failure. Conventional methods also severely damage the MgO layer.

Method used

A combination of atomic layer etching (ALE) and ion beam etching (IBE) is used. ALE is first used to form volatile etching byproducts, and then IBE is used to remove the residues, ensuring a vertical sidewall profile and reducing redeposition.

Benefits of technology

This enables efficient etching of high aspect ratio features, avoids tapered profiles and sidewall redeposition, protects the MgO layer, and improves the patterning accuracy and reliability of MRAM stacks.

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Abstract

A method for selectively etching a stack relative to a mask is provided. Atomic layer etching is provided to at least partially etch the stack, wherein the atomic layer etching forms at least some residue. An ion beam is provided to etch the stack, wherein the ion beam etching removes at least some of the residue from the atomic layer etching.
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Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 62 / 901,702, filed September 17, 2019, which is incorporated herein by reference for all purposes. Background Art

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. Nothing described in this background section, nor any underlying aspects of the written description, is admitted, either explicitly or implicitly, to be prior art to the present application.

[0004] The present disclosure relates to methods of forming semiconductor devices on semiconductor wafers. More particularly, the present disclosure relates to selective etching of semiconductor devices.

[0005] During the formation of semiconductor devices, a pattern transfer process can be used to form magnetic random access memory (MRAM). Such a pattern transfer process uses an etching process. MRAM stacks contain non-volatile and ferromagnetic materials such as cobalt (Co), iron (Fe), manganese (Mn), nickel (Ni), platinum (Pt), palladium (Pd), and ruthenium (Ru), which are extremely difficult to pattern without complex methods such as ion beam etching (IBE), reactive ion etching (RIE), and wet chemicals. Despite many years of development, current patterning techniques still have many disadvantages, such as sidewall redeposition that causes tapered profiles and shorts from the magnetic tunnel junction (MTJ) to the fixed layer, and corrosion that causes damage to the MTJ layer. In some conventional techniques, chlorine-containing chemicals are used to etch metal, but the byproducts of the etching include non-volatile compounds. The non-volatile compounds may subsequently redeposit on the sidewalls of the features. However, as devices shrink and the processing of various structure types becomes more complex, some etched byproducts may redeposit on other exposed areas of the substrate, potentially causing defects and ultimately device failure.

[0006] For large critical dimension (CD) structures with wide pitches, single-step or multi-step IBE recipes may be sufficient. However, for small CDs less than 100 nm or tight-pitch features, patterning using IBE is difficult. The fundamental limitation is that ion injection is blocked by the mask, which prevents efficient MRAM stack etching and trimming. Summary of the Invention

[0007] To achieve the foregoing and in accordance with the purposes of the present disclosure, a method for selectively etching a stack relative to a mask is provided. Atomic layer etching is provided to at least partially etch the stack, wherein the atomic layer etching forms at least some residue. Ion beam etching is provided to etch the stack, wherein the ion beam etching removes at least some of the residue from the atomic layer etching.

[0008] In another embodiment, a device for selectively etching a stack relative to a mask is provided. A vacuum transfer module is provided. An atomic layer etching chamber is connected to the vacuum transfer module. An ion beam etching chamber is connected to the vacuum transfer module. An encapsulation chamber is connected to the vacuum transfer module. A controller is controllably connected to the vacuum transfer module, the atomic layer etching chamber, the ion beam etching chamber, and the encapsulation chamber. The controller is configured to: control the vacuum transfer module to move the stack from the vacuum transfer module to the atomic layer etching chamber; control the atomic layer etching chamber to provide atomic layer etching of the stack; control the vacuum transfer module to move the stack to the ion beam etching chamber; control the ion beam etching chamber to provide ion beam etching of the stack; control the vacuum transfer module to move the stack from the ion beam etching chamber to the encapsulation chamber; and control the encapsulation chamber to provide encapsulation of the stack.

[0009] These and other features of the present disclosure will be described in more detail in the detailed description of the present disclosure and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references refer to like elements and in which:

[0011] Figure 1 A high-level flow chart of one implementation scheme is shown.

[0012] Figures 2A-2C is a schematic cross-sectional view of a stack processed according to one embodiment.

[0013] Figure 3 This is a more detailed flow chart of the atomic layer etching process.

[0014] Figure 4 It is a more detailed flow chart of the modification stage.

[0015] Figures 5A-5C is a more detailed cross-sectional view of a metal layer processed according to an embodiment.

[0016] Figure 6 is a schematic diagram of the atomic layer etching chamber system.

[0017] Figure 7 is a schematic diagram of the ion beam etching chamber.

[0018] Figure 8 is a schematic top view of a processing tool that can be used in one embodiment.

[0019] Figure 9 is a schematic diagram of a computer system that can be used to implement an embodiment. DETAILED DESCRIPTION

[0020] The present disclosure will now be described in detail with reference to several preferred embodiments of the present disclosure depicted in the accompanying drawings. In the following description, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be implemented without some or all of these specific details. In other cases, conventional processing steps and / or structures are not described in detail to avoid unnecessarily obscuring the present disclosure.

[0021] During processing of semiconductor wafers, features may be etched through metal-containing layers. In the formation of magnetic random access memory (MRAM), multiple thin metal layers, or films, may be etched sequentially to form a magnetic tunnel junction stack.

[0022] A magnetic tunnel junction (MTJ) consists of a thin dielectric barrier between two magnetic materials. Electrons tunnel through the barrier via a process called quantum tunneling. This serves as the basis for magnetic memory devices that utilize spin-transfer torque.

[0023] Spin transfer torque is an effect in which a spin-polarized current can be used to change the orientation of the magnetic layers in an MTJ. Charge carriers (e.g., electrons) have a property called spin. Spin is a small amount of angular momentum inherent to the carrier. The current is normally unpolarized (50% spin-up and 50% spin-down electrons). By passing a current through a thick magnetic layer (often called the "pinned layer"), a spin-polarized current with more electrons of either spin can be generated. If this spin-polarized current is directed into a second, thinner magnetic layer (the "free layer"), angular momentum can be transferred to that layer, changing its orientation. This effect can be used to stimulate oscillations, or even flip the orientation of a magnet.

[0024] Spin-transfer torque can be used to flip the active elements in magnetic random access memory (MRAM). Compared to traditional magnetoresistive random access memory (MRAM), spin-transfer torque-based magnetic random access memory (STT-RAM or STT-MRAM) offers advantages such as lower power consumption and better scalability. MRAM uses a magnetic field to flip the active elements.

[0025] Spin-transfer torque random access memory (STT-RAM) device patterning has been demonstrated using reactive ion etching followed by ion beam etching (IBE), or followed by a complete inert gas angled IBE strategy. Reactive ion etching (RIE) processes typically result in tapered profiles and heavy sidewall redeposition of etch byproducts. Furthermore, chemical damage to the MgO layer limits MRAM patterning to RIE alone.

[0026] IBE technology was developed for pattern transfer in MRAM while minimizing MTJ damage caused by reactive species. A common approach is to first perform IBE at a normal incidence angle to shape the MTJ and minimize footing, followed by sidewall cleaning by applying IBE at a grazing incidence angle to remove redeposition from the initial step. Because IBE relies on sputtering of inert ions, sidewall redeposition can occur during pattern transfer. Generally, IBE and oxidation cycles are performed to remove short-circuit paths, stopping at a MgO tunneling barrier to preserve a pristine and continuous free layer for spin transfer.

[0027] A plasma dry etching method for an MRAM stack is described in U.S. Patent No. 9,806,252 to Tan et al., entitled “Dry Plasma Etch Method To Pattern MRAM Stack,” issued on October 31, 2017, which is incorporated by reference for all purposes. A method for providing ion beam etching is described in U.S. Patent No. 9,257,295 to Singh et al., entitled “Ion Beam Etching System,” issued on February 9, 2016, which is incorporated by reference for all purposes.

[0028] For large critical dimension (CD) structures with wide pitches, single-step or multi-step IBE recipes may be sufficient. However, for small CDs less than 100 nm or tight-pitch features, patterning using IBE is difficult. The fundamental limitation is that the ion injection is blocked by the mask. This limitation hinders efficient MRAM stack etching and trimming.

[0029] In one embodiment, the initial pattern transfer is achieved via atomic layer etching (ALE). For cobalt (Co) and iron (Fe) containing materials, the ALE process introduces Si species to form volatile etching byproducts. The chemical etching mechanism minimizes redeposition on the sidewalls. Therefore, ALE can pattern tight pitches without being limited by aspect ratio. Since the Ar step in the ALE cycle removes and sweeps reactive species, the ALE process minimizes MgO damage compared to RIE, although the ALE process involves halogen plasma. The ALE process opens the MRAM stack and defines the overall outline.

[0030] In this embodiment, a second IBE process step is applied to the MRAM pillars defined by ALE. This IBE step facilitates the removal of sidewall residues to minimize potential damage from surface-adsorbed halogen species. IBE further trims the MRAM sidewalls to a vertical profile. Because ALE is used to etch the MTJ stack, which forms volatile byproducts, this IBE step is not used in an incident angle mode to pattern the MRAM. Instead, it is cleaned at a grazing angle to remove residues and / or footing from the stack.

[0031] The integrated processing of ALE and IBE has two advantages. 1) The IBE step effectively removes halogen species on the surface and sidewalls of the MRAM stack. For ALE patterning, residual halogen species, such as from the chamber walls, can cause problems with a residual chlorinated surface layer. Sidewall residues deteriorate electrical properties and cause device shorts or degraded electrical signals. In addition, inert ions further remove the halogenated surface layer to leave a minimum amount of halogen residue. 2) The integrated process circumvents the limitations of IBE for patterning high aspect ratio or tight pitch structures. Since the chemical etching from ALE initially defines the MRAM pillars, the patterning restrictions are no longer limited by the ion incident angle of the IBE. The integration used in the embodiment provides a solution for patterning high-density MRAM arrays without redeposition or corrosion on the entire MTJ sidewall.

[0032] For ease of understanding, Figure 1 FIG. 1 is a high-level flow chart of one embodiment. In this embodiment, a stack is subjected to atomic layer etching (step 104). The stack may include multiple layers of different materials. For example, the stack may include one or more layers of magnetic material used in a typical MRAM. Figure 2A is a schematic cross-sectional view of an exemplary stack 200, wherein the stack 200 may be used Figure 1The stack 200 is processed according to the process shown in FIG. The stack 200 has a silicon or silicon oxide (Si / SiO2) layer 204 on a substrate. A first tantalum (Ta) layer 208 is on the Si / SiO2 layer 204. A platinum (Pt) layer 212 is on the first Ta layer 208. A cobalt platinum alloy (CoPt) layer 216 is on the Pt layer 212. A magnesium oxide (MgO) layer 220 is on the CoPt layer 216. A cobalt iron boron (CoFeB) layer 224 is on the MgO layer 220. A second Ta layer 228 is on the CoFeB layer 224. A ruthenium (Ru) layer 232 is on the second Ta layer 228. A patterned mask is formed on the stack 200. In this embodiment, the patterned mask includes a Ru layer 244, a SiO2 layer 240 below the Ru layer 244, and a titanium nitride layer 236 below the SiO2 layer 240. In this embodiment, an optional opening etch of the Ru layer 244 is provided prior to the atomic layer etch (step 104). The opening etch of the Ru layer 244 is provided using an oxygen-containing plasma.

[0033] Figure 3 3 is a more detailed flow chart of the atomic layer etching (step 104). The atomic layer etching includes multiple cycles, wherein each cycle includes a modification phase (step 304) and an activation phase (step 308). Figure 4 4 is a more detailed flow chart of the modification phase. A modifying gas is provided (step 404). The modifying gas can be any suitable gas that can modify the surface to facilitate the activation phase. For example, the modifying gas can be a halogen-containing gas. In one embodiment, the modifying gas includes between 5 and 200 seem of silicon tetrachloride (SiCl4). The modifying gas is converted into a plasma (step 408). In some exemplary embodiments, a plasma power between about 100 W (watts) and 900 W can be used to generate the plasma. The temperature during this operation can be between about 60° C. and about 200° C. The chamber pressure during this operation can be between about 1 mTorr and about 500 mTorr. Without being limited to a particular theory, it is believed that the plasma decomposes SiCl4 molecules to produce chlorine and Si-Cl species. In some cases, a pulsed bias can be applied. The Si-Cl species forms a modified layer of Si-Cl components, wherein the Si-Cl components are adsorbed into the metal layer. For different metals M in different layers, chlorine and Si—Cl species are adsorbed into the different metals M to form MSiClx atomic layers, where x is an integer between 1 and 3 (inclusive). The atomic layer can be a monolayer, thicker than a monolayer, or incomplete.

[0034] Figures 5A-5C The molecular interactions of the stack as it is processed are shown. In particular, Figures 5A-5C Shows the processing Figure 2A of stacked pieces. Figure 5A 2 is an enlarged schematic diagram of a portion of the CoFeB layer 224. The modified gas of SiCl4 has formed a plasma containing Si 508 and Cl 512. The substance in the plasma is SiCl x , wherein x is an integer from 1 to 3 (inclusive). In addition, there may be independent chloride ions. x The material is accelerated to the CoFeB layer 224. The SiCl x The substance bonds to the top exposed surface of the CoFeB layer 224 to form a monolayer.

[0035] In this embodiment, the modification phase (step 304) is stopped after the monolayer is formed. Figure 5B The SiCl layer is formed on the top surface of the CoFeB layer 224. x A single layer is formed to form an enlarged schematic diagram of a portion of the CoFeB layer 224 after modifying the surface of the portion of the CoFeB layer 224. The bias voltage, and / or the flow of the modifying gas, and / or the plasma power may be stopped.

[0036] After the atomic layer is formed and the modification phase (step 304) is completed, the stack 200 is subjected to an activation phase (step 308). The activation phase may include providing a gas that can be activated, such as a gas that can be used to generate a plasma. For example, the activation gas may be a rare gas. In this embodiment, the stack 200 is subjected to an argon (Ar) plasma to provide the activation phase (step 308). In this embodiment, an activation gas comprising Ar is provided. The activation gas is activated. The activation of the activation gas may be by forming the activation gas into a plasma. A plasma power between about 100W and 900W may be used to generate the plasma. The temperature during this operation may be between about 60°C and about 300°C. The chamber pressure during this operation may be between about 1mTorr and about 500mTorr. The Ar plasma causes the MSiCl x The molecules evaporate, allowing the removal of MSiCl x molecules. Thus, the modified surface of the metal layer is selectively etched away relative to the mask. Thus, the surface modification is used to etch the stack 200. In other embodiments, thermal activation can be used to activate the activation gas.

[0037] Figure 5C is an enlarged schematic diagram of a portion of the CoFeB layer 224 during the activation phase. Argon ions 516 are accelerated toward the CoFeB layer 224 by a bias voltage. The Ar ions 516 convert MSiCl x Complex activation to form volatile MSiCl xcomplex 520, where M represents a metal, which in this example is CoFeB. The bias provides sufficient energy to the Ar ions 516 to cause the MSiCl x The complex 520 is volatilized, but with insufficient energy to etch the redeposited residue. The steps of providing a modification phase (step 304) and an activation phase (step 308) are cyclically repeated multiple times to provide atomic layer etching of the stack 200 (step 104).

[0038] Figure 2B A schematic cross-sectional view of stack 200 after ALE (step 104) is provided. A residue layer 248 of redeposited residue material forms on the sidewalls of stack 200. This residue layer 248 includes metal material, silicon, and chlorine residues. Some chlorine may migrate to and attack certain layers, such as MgO layer 220, to form MgO regions infiltrated with chlorine 252. As indicated by the non-vertical side, the deposition of residue layer 248 on the sidewalls of stack 200 causes the stack to be etched obliquely.

[0039] After completing ALE of the stack 200 (step 104), the stack 200 is subjected to IBE (step 108). Ion beam etching refers to the removal of atoms by physical sputtering using an inert gas. Physical sputtering is provided by the exchange of momentum between ions of the inert gas and the material being etched by collision with the ions. In one embodiment, the chamber pressure is maintained at less than 20 mTorr. The low pressure reduces collisions between the ions and the gas and reduces the possibility of plasma formation. In this embodiment, the ions are Ar ions. In other embodiments, other ions different from the ions provided by the activated gas may be used. The ions are accelerated to an energy in the range of 50 volts (V) to 1800 V. The ions have sufficient energy to sputter the residue layer 248 and the M atoms or molecules.

[0040] Figure 2C FIG2 is a schematic cross-sectional view of stack 200 after IBE (step 108) has been performed. The IBE (step 108) removes residue layer 248 and chlorine 252 that has penetrated into MgO layer 220. Furthermore, the IBE (step 108) eliminates or reduces the slope. In this example, the sidewalls of stack 200 are vertical due to the elimination of the slope by the IBE (step 108).

[0041] ALE (step 104) can etch features with a higher aspect ratio than IBE alone. In addition, the features provided by the above-described embodiments can have a higher pitch than features formed using IBE alone. ALE alone can result in a more sloped stack with sidewall deposition. If IBE (step 108) is not provided, the chlorine 252 that penetrates and attacks the MgO layer 220 will etch away some of the MgO layer 220. The IBE process (step 108) can reduce or eliminate the slope and the residue layer 248. The IBE process (step 108) can remove the chlorine 252 that penetrates the MgO layer 220 without etching away some of the MgO layer 220.

[0042] In this embodiment, ALE (step 104) can utilize a recipe to etch all layers in the stack 200. Because the stack 200 is relatively thin (e.g., less than 30 nm thick), ALE (step 104) is performed in less than 15 minutes. The IBE process (step 108) can also remove or reduce the footing at the bottom of the stack 200. In other embodiments, ALE (step 104) at least partially etches the stack 200.

[0043] In various embodiments, stack 200 can be a stack used in an MRAM. In various embodiments, stack 200 can be a magnetic tunnel junction (MTJ) formed by a thin dielectric barrier layer between two magnetic materials. In various embodiments, stack 200 includes at least one metal-containing layer. The metal-containing layer can include at least one of Cr, Mo, Ir, Ti, Ru, Mn, Ni, Pd, Ta, Co, Fe, Mg, and Pt. In one example, the stack includes at least one MgO layer. Other stacks can have other transition metals (e.g., Group IV transition metals, Group V transition metals, and Group VI transition metals) in the first, second, and third rows, including metals such as Cu.

[0044] In the above embodiment, the modifying gas includes SiCl4. In other embodiments, the modifying gas includes halosilanes. Examples of halosilanes are iodosilane, bromosilane, chlorosilane, hydrochlorosilane, and fluorosilane. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di(tert-butyl)chlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, SiHCl-(N(CH3)2)2, and the like. In some embodiments, germanium, carbon, titanium, or tin may be used to replace silicon in the modifying gas. In various embodiments, the modifying gas includes a halogen-containing gas including an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin. In other embodiments, metallic silicon and chlorine molecules (MSiCl x ) is more broadly described as a metal tetrel halogen molecule. In this specification and claims, the metal tetrel halogen molecule is defined as a molecule having at least one metal atom, at least one halogen atom, and at least one of silicon, germanium, silicon, titanium, and tin. When the metal tetrel halogen molecule includes silicon, the metal tetrel halogen molecule is a volatile metal silo complex. In another embodiment, SiCl4 and CO precursors can be used to produce M(SiCl3)(CO). In another embodiment, Cl2 precursors and H2O can be used to produce MCl x (H2O) y In another embodiment, a methanol (CH3OH) precursor may be used.

[0045] In other embodiments, the reactant gas may be another noble gas other than Ar. In other embodiments, the reactant gas may be one or more of carbon monoxide (CO), water (H2O), CH3OH, or ammonia (NH3). The reactant gas is converted into reactant gas ions.

[0046] In some embodiments, ALE (step 104) can be used to provide an overetch. This overetch etches some of the silicon or silicon oxide (Si / SiO2) layer 204. This overetch reduces the slope of the stack 200 etched by ALE (step 104). During the etching of the overetched silicon or silicon oxide (Si / SiO2) layer 204, less material is redeposited, causing the residue layer 248 to be etched away and reducing the slope. This overetch can also be used to reduce or remove stack footing.

[0047] One or more additional processes may be performed on the stack before, after, or during the above steps in the above embodiments. For example, an additional IBE opening step may be used to partially open the stack 200 before ALE (step 104). This process may open the CoFeB layer, allowing it to be opened without exposing the CoFeB to halogen. In another embodiment, ALE (step 104) and IBE (step 108) may be performed cyclically for at least two cycles. This process may have a slower throughput rate.

[0048] Furthermore, the order and sequence of the exemplary processes described above can be modified in any practical manner. For example, other embodiments may provide IBE before ALE to etch multiple layers, and then use IBE after ALE to remove residue. However, other embodiments may use IBE to etch one or more layers, then use ALE to etch one or more layers, then use IBE to etch one or more layers, and then use ALE to etch one or more layers.

[0049] To provide an embodiment of a process chamber that can be used for an ALE process (step 104), Figure 6An example of an ALE chamber system 600 that can be used for ALE processing is schematically depicted. The ALE chamber system 600 includes a plasma reactor 602 having a plasma processing confinement chamber 604 therein. A plasma power supply 606, regulated by a plasma matching network 608, provides power to a transformer coupled plasma (TCP) coil 610 located near a dielectric induction power window 612 to generate a plasma 614 within the plasma processing confinement chamber 604 by providing inductively coupled power. A peak 672 extends from a chamber wall 676 of the plasma processing confinement chamber 604 to the dielectric induction power window 612, forming a peak ring. The peak 672 is angled relative to the chamber wall 676 and the dielectric induction power window 612 such that the internal angles between the peak 672 and the chamber wall 676 and the internal angles between the peak 672 and the dielectric induction power window 612 are each greater than 90° and less than 180°. As shown, the peak 672 provides an angled ring near the top of the plasma processing confinement chamber 604. The TCP coil (upper power supply) 610 can be configured to produce a uniform diffusion profile within the plasma processing confinement chamber 604. For example, the TCP coil 610 can be configured to produce a toroidal power distribution in the plasma 614. A dielectric induction power window 612 is provided to separate the TCP coil 610 from the plasma processing confinement chamber 604 while allowing energy to be transferred from the TCP coil 610 to the plasma processing confinement chamber 604. The TCP coil 610 acts as an electrode to provide radio frequency (RF) power to the plasma processing confinement chamber 604. A wafer bias power supply 616, regulated by a bias matching network 618, provides power to an electrode 620 to set a bias voltage on a substrate 666. The substrate 666 is supported by the electrode 620 to serve as a substrate support. A controller 624 controls the plasma power supply 606 and the wafer bias power supply 616.

[0050] The plasma power supply 606 and the wafer bias power supply 616 can be configured to operate at a specific radio frequency, such as, for example, 13.56 megahertz (MHz), 27 MHz, 2 MHz, 60 MHz, 400 kilohertz (KHz), 2.54 gigahertz (GHz), or a combination thereof. The plasma power supply 606 and the wafer bias power supply 616 can be appropriately sized to supply a range of powers to achieve desired process performance. For example, in one embodiment, the plasma power supply 606 can supply a power range of 50 to 5000 watts, while the wafer bias power supply 616 can supply a bias voltage range of 20 to 2000 volts (V). Furthermore, the TCP coil 610 and / or electrode 620 can be comprised of two or more sub-coils or sub-electrodes. The sub-coils or sub-electrodes can be powered by a single power supply or by multiple power supplies.

[0051] like Figure 6As shown, the plasma processing chamber system 600 also includes a gas source / gas supply mechanism 630. The gas source 630 is fluidly connected to the plasma processing confinement chamber 604 via a gas inlet, such as a gas injector 640. The gas injector 640 can be located at any convenient location in the plasma processing confinement chamber 604 and can be of any type for injecting gas. However, the gas inlet is preferably configured to produce an "adjustable" gas injection profile. The adjustable gas injection profile allows the flow of corresponding gases to multiple regions in the plasma processing confinement chamber 604 to be independently adjusted. More preferably, the gas injector is mounted to the dielectric induction power window 612. The gas injector can be mounted on the power window 612, mounted in the power window 612, or form a part of the power window. Process gas and byproducts are removed from the plasma processing confinement chamber 604 via a pressure control valve 642 and a pump 644. The pressure control valve 642 and the pump 644 are also used to maintain a specific pressure in the plasma processing confinement chamber 604. Pressure control valve 642 can maintain a pressure of less than 1 Torr during processing. Edge ring 660 is placed around substrate 666. Gas source / gas supply mechanism 630 is controlled by controller 624. Kiyo manufactured by Lam Research Corp. (Fremont, CA) can be used to practice embodiments.

[0052] To illustrate an embodiment of an ion beam etching chamber, Figure 7 A simplified cross-sectional view of an ion beam etching chamber 700 for performing ion beam etching according to certain methods is presented. In this example, a substrate 701 is supported on a substrate support 703. The ion beam etching chamber 700 can be equipped with hardware (not shown) to provide electrical and fluid connections. The electrical connections can be used to supply power to the substrate support 703, or in some examples to an electrostatic chuck located on or inside the substrate support 703, and the fluid connections can be used to provide a fluid that is used to control the temperature of the substrate 701 and the substrate support 703. The substrate support 703 can be heated by a heater (not shown) and / or cooled by a cooling mechanism (not shown). Any suitable cooling mechanism can be used. In one example, the cooling mechanism can involve flowing a cooling fluid through a conduit within or adjacent to the substrate support 703. As Figure 7 As indicated by the double-headed arrow in FIG, the substrate support 703 can be rotated and tilted at variable speeds and angles. This rotation and tilting allows the ion beam to be incident at different angles continuously. Different IBE angles expose more of the residue layer 248 to IBE, resulting in faster removal of the residue layer 248.

[0053] The plasma generating gas is transported to the main plasma generating region 705. The plasma generating gas is excited by the plasma source 707. Figure 7 In the context of FIG, plasma source 707 is a coil that serves as the source of an inductively coupled plasma. Other sources, such as capacitively coupled sources, microwave sources, or discharge sources, may be used in a suitably designed reactor. Plasma is formed in the primary plasma generation region 705. Extraction electrode 709 includes a series of orifices 710 through which ions are extracted.

[0054] The orifices 710 may have a diameter between about 0.5-1 cm and a height defined by the thickness of the electrode. The orifices 710 may have an aspect ratio (AR) of height to width between about 0.01-100.0. In some cases, the orifices 710 are configured in a hexagonal, checkered, or spiral pattern, but other patterns may also be used. The center-to-center distance between adjacent orifices may be between about 1 mm and 10 cm. When only a single (top or bottom) face of the electrode is considered, the orifices may be configured to achieve a total open area (i.e., the sum of the areas of the orifices) between about 0.1% and 95% of the surface area of ​​the electrode. For example, an electrode having a diameter of 40 cm and 500 holes each having a diameter of 1 cm to form an electrode having an open area of ​​about 31% (393 cm 2 Opening area divided by 1257 cm 2 The orifices 710 may have different diameters in different electrodes. In some cases, the orifice diameter is smaller in the upper electrode and larger in the lower electrode. In one embodiment, the orifice in the lower electrode 713 is larger than the orifice in the focusing electrode 711 (e.g., between about 0-30% larger). In these or other cases, the orifice in the focusing electrode 711 is larger than the orifice in the extraction electrode 709 (e.g., between about 0-30% larger).

[0055] A bias voltage V1 applied to the extraction electrode 709 relative to the substrate 701 serves to impart kinetic energy to the ions relative to the substrate. This bias voltage is typically positive and can range from approximately 20 to 10,000 volts or more. In some cases, the bias voltage on the extraction electrode ranges from approximately 20 to 2,000 volts. Positive ions in the plasma above the extraction electrode 709 are attracted to the lower electrode 713 by the potential difference between electrodes 709 and 713. A focusing electrode 711 is added to focus the ions and, if necessary, repel electrons. The bias voltage V2 applied to this electrode can be positive or negative relative to the extraction electrode 709, but is typically biased negatively. The bias potential of the focusing electrode 711 is determined by the lens properties of the focusing electrode 711. Bias voltages on the focusing electrode 711 include positive voltages ranging from approximately 1.1 to 20 times the potential V1 on the extraction electrode, and negative voltages ranging from approximately 0.001 to 0.95 times the potential V1. Since different potentials are applied to different electrodes, a potential gradient exists. This potential gradient can be on the order of about 1000 V / cm. An exemplary separation distance between adjacent electrodes falls between about 0.1 and 10 cm, or, for example, about 1 cm.

[0056] If the voltage of the focusing electrode 711 is set to produce a collimated beam, then after the ions leave the bottom of the grounded lower electrode 713, they propagate in a collimated and focused beam. Alternatively, if the voltage of the focusing electrode is adjusted to under-focus or over-focus the ion beam, the beam will be divergent. In many (but not all) cases, the lower electrode 713 is grounded. Using a grounded lower electrode 713 in conjunction with a grounded substrate 701 results in a substantially field-free substrate processing region 715. Having the substrate in the field-free region prevents electrons or secondary ions generated by collisions between the ion beam and residual gases, or between the ion beam and surfaces in the reaction chamber, from being accelerated toward the substrate, thereby minimizing the risk of causing undesirable damage or secondary reactions.

[0057] In addition, it is important to prevent the substrate 701 from being charged by the ion beam itself or by ejected secondary electrons generated during the collision between the ion beam and the substrate. Neutralization is usually achieved by adding a low-energy electron source (not shown) in the vicinity of the substrate 701. Since the positive charge on both the ions and the ejected secondary electrons will positively charge the substrate, the low-energy electrons in the vicinity of the substrate can be attracted to the positively charged surface and can neutralize the charge. It is relatively easy to perform this neutralization in a field-free region.

[0058] In some applications, it may be desirable to have a potential difference between the lower electrode 713 and the substrate 701. For example, if very low energy ions are required, it can be difficult to maintain a well-collimated beam over long distances at low energy due to the mutual repulsion of positively charged ions (space-charge effect). One solution to this is to negatively bias the lower electrode 713 relative to the substrate 701 (or conversely, to positively bias the substrate 701 relative to the lower electrode 713). This allows the extraction of higher energy ions and slows them down as they reach the substrate.

[0059] Each of electrodes 709, 711, and 713 has a thickness. This thickness can be between about 0.5 mm and 10 cm, or between about 1 mm and 3 cm, for example, about 5 mm. Electrodes 709, 711, and 713 can each have the same thickness, or they can have different thicknesses. Furthermore, the separation distance between the extraction electrode 709 and the focusing electrode 711 can be the same as, greater than, or less than the separation distance between the focusing electrode 711 and the lower electrode 713.

[0060] The orifices 710 located in the extraction electrode 709, the focusing electrode 711, and the lower electrode 713 can be precisely aligned with each other. Otherwise, the ions will be incorrectly aimed and the etching results on the wafer will be degraded. For example, if a single orifice in the focusing electrode 711 is misaligned, this can cause one area of ​​the substrate 701 to be overetched (where too many ions are directed) while another area of ​​the substrate 701 is underetched (where no ions, or too few ions, are directed). Therefore, the orifices should be aligned with each other as closely as possible. In each case, the amount of misalignment between vertically adjacent electrodes is limited to about 1% or less of the hole diameter (measured by the linear displacement distance between the position of the orifice relative to the position of the adjacent orifice).

[0061] Ion beam etching processes are typically performed at low pressures. In some embodiments, the pressure can be about 100 mTorr or lower, for example, about 1 mTorr or lower, and in many cases about 0.1 mTorr or lower. Low pressure helps minimize undesirable collisions between ions and any gaseous species present in the substrate processing region. In some cases, relatively high pressure reactants are transported in other low-pressure ion processing environments.

[0062] In one embodiment, a processing tool may provide a platform that provides an ALE processing chamber, an IBE processing chamber, and a chamber for packaging the resulting device. Figure 8800 is a top view of a processing tool used in an embodiment. The wafer box 802 holds unprocessed wafers before they are processed and then holds processed wafers once all processing in the processing tool 800 is completed. The wafer box 802 can hold many wafers, often up to 25 wafers. The atmospheric transfer module (ATM) 814 is used to transfer wafers to and from the wafer box 802. The load lock station 805 represents at least one device that operates to transfer wafers back and forth between the atmosphere of the ATM 814 and the vacuum of the vacuum transfer module (VTM) 812. The VTM 812 is part of the processing tool and is connected to multiple chambers. There can be different types of chambers. In this embodiment, there are two ALE chambers 600 and two ion beam etching chambers 700 and an encapsulation chamber 828. In this embodiment, these ALE chambers 600 are manufactured by Lam Research (Fremont, CA). These ion beam etching chambers 700 were manufactured by Lam Research (Fremont, CA). The encapsulation chamber 828 may be a plasma enhanced chemical vapor deposition (PECVD) chamber or another dielectric deposition chamber, such as that manufactured by Lam Research (Fremont, CA). PECVD chamber. A robotic system within the vacuum transfer module 812 uses a robotic arm to move wafers with stacks between the load lock station 805 and the various chambers 600, 700, and 828. ATM 814 uses a robotic system to transfer wafers between the wafer cassette 802 and the load lock station 805 under vacuum. A controller 835 can be used to control the processing tool 800. The controller 835 can include one or more sub-controllers. The controller 835, which may include one or more sub-controllers, is controllably connected to the vacuum transfer module 812, the atomic layer etch chamber 600, the ion beam etch chamber 700, and the packaging chamber 828.

[0063] Figure 9900 is a high-level block diagram showing a computer system 900. The computer system 900 is suitable for implementing the controller 835 used in the embodiments. The computer system 900 can have a variety of physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to giant supercomputers. The computer system 900 includes one or more processors 902, and may further include an electronic display device 904 (for displaying graphics, text, and other data), a main memory 906 (e.g., random access memory (RAM)), a storage device 908 (e.g., a hard drive), a removable storage device 910 (e.g., an optical drive), a user interface device 912 (e.g., a keyboard, touch screen, keypad, mouse, or other pointing device, etc.), and a communication interface 914 (e.g., a wireless network interface). The communication interface 914 enables software and data to be transmitted between the computer system 900 and external devices via a link. The system may also include a communication infrastructure 916 (e.g., a communication bus, a cross-over bar, or a network), to which the aforementioned devices / modules are connected.

[0064] The information transmitted via the communication interface 914 can be in the form of a signal that can be received by the communication interface 914 through a communication link, such as an electronic, electromagnetic, optical, or other signal, which carries the signal and can be a communication link implemented using wire or cable, optical fiber, telephone line, cellular telephone link, radio frequency link, and / or other communication channel. Using such a communication interface 914, it is contemplated that one or more processors 902 can receive information from a network or can output information to a network in the course of implementing the above-described method steps. In addition, the method embodiments can be executed solely on the processor or can be executed in conjunction with a remote processor over a network such as the Internet, which shares a portion of the processing.

[0065] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices (such as hard disks, flash memory, hard drive memory, CD-ROMs, and other forms of permanent memory), and should not be interpreted as covering transient subject matter such as carrier waves or signals. Examples of computer-readable code include machine code, such as that produced by a compiler, and files including higher-level code executed by a computer using an interpreter. Computer-readable media can also be computer code transmitted by a computer data signal or processor.

[0066] In some embodiments, the computer-readable medium may include computer-readable code for transferring the stack to the ALE chamber 600, computer-readable code for performing the ALE process (step 104), computer-readable code for transferring the stack to the ion beam etching chamber 700, computer-readable code for performing the ion beam etching process (step 108), computer-readable code for transferring the stack 200 to the packaging chamber 828, computer-readable code for packaging the stack 200, and computer-readable code for removing the stack 200 from the processing tool 800 to the atmosphere. Packaging the stack 200 after etching and before exposing the stack 200 to the atmosphere prevents oxidation of the various layers of the stack. Oxidation of the various layers of the stack 200 may cause device malfunction. The integrated processing tool 800 having the ALE chamber 600, the ion beam etching chamber 700, and the packaging chamber 828 provides faster throughput for etching MRAM.

[0067] Although the present disclosure has been described with respect to several preferred embodiments, variations, modifications, permutations, and various alternative equivalents exist within the scope of the present disclosure. It should also be noted that there are many alternative embodiments of the methods and apparatuses of the present disclosure. Therefore, it is intended that the following claims be interpreted as including all such variations, modifications, permutations, and various alternative equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. A method of selectively etching a stack relative to a mask, comprising: providing atomic layer etching to at least partially etch the stack, wherein the atomic layer etching forms at least some redeposited residue; as well as Ion beam etching of the stack is provided, wherein the ion beam etching removes at least some of the redeposited residue from the atomic layer etching.

2. The method of claim 1 , wherein providing the atomic layer etch comprises a plurality of cycles, wherein each cycle comprises: The modification stage includes: providing a modifying gas comprising a halogen-containing gas including an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin; and converting the modifying gas into a plasma, wherein components from the plasma modify a portion of a surface of the stack to form a modified surface; and An activation stage, wherein the activation stage etches the modified surface of the stack.

3. The method according to claim 2, wherein the halogen-containing gas is selected from the group consisting of iodosilane, bromosilane, chlorosilane, hydrochlorosilane and fluorosilane.

4. The method according to claim 2, wherein the activation stage comprises: providing activation gas; as well as The activated gas is activated. The method of claim 4 , wherein the activation stage further comprises applying a bias voltage.

6. The method of claim 2, wherein the activation stage produces metal Group IV halogen molecules. The method of claim 6 , wherein the metal Group IV halogen molecule comprises metal, silicon, and halogen. The method of claim 1 , wherein the stack comprises at least one metal-containing layer.

9. The method of claim 1, wherein the stack comprises at least one transition metal-containing layer.

10. The method of claim 1 , wherein said providing said atomic layer etch comprises a plurality of cycles, wherein each cycle comprises: The modification stage includes: providing a reforming gas comprising a halogen-containing gas; and converting the modifying gas into a plasma, wherein components from the plasma modify a portion of a surface of the stack to form a modified surface; and An activation stage, wherein the activation stage etches the modified surface of the stack. The method of claim 1 , further comprising providing ion beam opening etching before providing the atomic layer etching.

12. A method of selectively etching a stack relative to a mask, comprising: providing an atomic layer etch to at least partially etch the stack, wherein the atomic layer etch forms at least some residue; as well as Ion beam etching of the stack is provided, wherein the ion beam etching removes at least some of the residue from the atomic layer etching, wherein providing the ion beam etching includes directing gas ions toward the stack at continuously varying angles. The method of claim 12 , wherein the ion beam etching reduces a slope of the stack.

14. The method of claim 12, wherein the ion beam etching removes halogens that have penetrated into the metal-containing layer of the stack. 15 . The method of claim 12 , wherein the ion beam etching removes chlorine that has penetrated into a metal-containing layer of the stack without etching the metal-containing layer of the stack.

16. An apparatus for selectively etching a stack relative to a mask, comprising: Vacuum transmission module; an atomic layer etching chamber connected to the vacuum transfer module; an ion beam etching chamber connected to the vacuum transfer module; an encapsulation chamber connected to the vacuum transfer module; a controller controllably connected to the vacuum transfer module, the atomic layer etching chamber, the ion beam etching chamber, and the packaging chamber, wherein the controller is configured to: controlling the vacuum transfer module to move the stack into the atomic layer etching chamber; controlling the atomic layer etch chamber to provide atomic layer etching of the stack, wherein the atomic layer etching forms at least some residue; controlling the vacuum transfer module to move the stack from the atomic layer etching chamber to the ion beam etching chamber; controlling the ion beam etching chamber to provide ion beam etching of the stack, wherein the ion beam etching removes at least some of the residue from the atomic layer etching; controlling the vacuum transfer module to move the stack from the ion beam etching chamber to the packaging chamber; as well as The encapsulation chamber is controlled to provide encapsulation of the stack.

17. The apparatus of claim 16, wherein the controller is further configured to: controlling the atomic layer etching chamber to provide a modifying gas; and The atomic layer etch chamber is controlled to convert the modifying gas into a plasma, wherein components from the plasma modify a portion of a surface of the stack to form a modified surface.

18. The apparatus of claim 17, wherein the controller is further configured to: controlling the atomic layer etching chamber to provide an activation gas; and The atomic layer etching chamber is controlled to activate the activation gas. 19 . The apparatus of claim 18 , wherein the controller is further configured to control the atomic layer etching chamber to apply a bias voltage.

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