Semiconductor device

Abstract

This application relates to the field of semiconductor technology, specifically to a semiconductor device, comprising: a semiconductor substrate on which a chip region and a dicing line region are formed; a first sealing ring disposed between the chip region and the dicing line region, the first sealing ring surrounding the chip region; wherein a vertical natural capacitor is formed within the first sealing ring, integrating the vertical natural capacitor within the sealing ring, thereby increasing the chip integration density, saving space, and achieving chip miniaturization.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device. Background Technology

[0002] In integrated circuits of semiconductor chips, the seal ring has a significant impact on chip reliability. A traditional semiconductor chip includes an integrated circuit region and a seal ring positioned around its periphery. The integrated circuit region can contain various electronic devices, such as passive and active components formed on a substrate. The seal ring lies between the wafer dicing lane (SL) and the integrated circuit region. During wafer dicing along the SL, the seal ring prevents unwanted stress propagation and breakage caused by the dicing process from the SL to the chip. Furthermore, the semiconductor chip also possesses resistance to gas and liquid corrosion, preventing the penetration and damage from moisture or other chemical contaminants.

[0003] Generally, in applications, the voltage input terminal Vdd of a traditional semiconductor chip must be connected to an external voltage source Vcc, and an additional voltage regulator capacitor C1 is required to stabilize the input voltage. Therefore, the need for an additional voltage regulator capacitor in traditional semiconductor chip applications results in extra cost and increases the complexity of the external circuitry, hindering the miniaturization of the semiconductor chip. Summary of the Invention

[0004] This application addresses, at least to some extent, the aforementioned technical problems in related technologies. To this end, this application proposes a semiconductor device to solve the problem of low device integration.

[0005] To achieve the above objectives, a first aspect of this application provides a semiconductor device, comprising:

[0006] A semiconductor substrate, wherein a chip region and a dicing line region are formed on the semiconductor substrate;

[0007] A first sealing ring is disposed between the chip area and the dicing line area.

[0008] The first sealing ring is provided around the chip area;

[0009] A vertical natural capacitor is formed inside the first sealing ring. Attached Figure Description

[0010] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0011] Figure 1 A cross-sectional view of the first and second sealing rings in one embodiment of this application is shown;

[0012] Figure 2 A top view of the first and second sealing rings in one embodiment of this application is shown. Detailed Implementation

[0013] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0015] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0016] Traditional semiconductor chips require an additional voltage regulator capacitor in applications, which incurs extra cost and increases the complexity of the external circuitry, hindering miniaturization. To address these issues, this embodiment proposes a first sealing ring positioned around the periphery of the chip area. This ring possesses the functions of a conventional sealing ring, such as preventing static electricity from affecting the integrated circuit area on the semiconductor chip, avoiding damage to the integrated circuit area from mechanical cutting tools, and preventing moisture or other pollutants and corrosive agents from entering the integrated circuit area. This first sealing ring not only provides the functions of a traditional sealing ring but also, through structural improvements, forms a capacitor, achieving voltage regulation without the need for an external capacitor. Furthermore, integrating the capacitor within the sealing ring increases the chip's integration density, saves space, and contributes to chip miniaturization.

[0017] Please refer to Figure 1-2 The first aspect of this application provides a semiconductor device 100, wherein the semiconductor device 100 has a chip region 101, a sealing ring region 102 surrounding the chip region 101, and a dicing line region 103 surrounding the sealing ring region 102, wherein the chip region 101 is provided for forming various components, such as transistors, resistors, and other familiar semiconductor components, the sealing ring region 102 is provided for forming a sealing ring structure thereon, and the dicing line region 103 is provided for performing a dicing process to form individual chips from a semiconductor wafer.

[0018] The semiconductor device 100 includes a semiconductor substrate 10, a first sealing ring 11, and a second sealing ring 12. The semiconductor substrate 10 has an isolation structure formed therein for isolating and surrounding a first source / drain region 103 and a second source / drain region 104. In this embodiment, the isolation structure may be a shallow trench isolation structure. Alternatively, the isolation structure may be a local silicon oxide feature.

[0019] It is worth mentioning that, in this embodiment, the example is to simultaneously form a first sealing ring 11 and a second sealing ring 12 on a semiconductor substrate 10. It should be noted that, in other embodiments of the present invention, the first sealing ring 11 may be provided alone, and this embodiment does not limit this.

[0020] An insulating layer is formed on the semiconductor substrate 10 and corresponds to the chip region 101, the sealing ring region 102, and the dicing line region 103. The insulating layer may be a single layer or a multilayer structure to serve as an interlayer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer, and the insulating layer may include oxides, nitrides, oxynitrides or combinations thereof, or may include low-k materials such as fluorinated silicate glass (FSG), carbon doped oxide, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), or fluorine tetra-ethyl-orthosilicate (FTEOS). The insulating layer can be formed using techniques such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), or other conventional deposition techniques.

[0021] Continue to refer to Figure 1 A first sealing ring 11 is formed on the first source / drain region 103 and surrounds the chip region 101, embedded in the insulating layer, and corresponds to the sealing ring region 102. The first sealing ring 11 may include a plurality of stacked and electrically connected metal wiring layers 111 (e.g., copper layers) (i.e., these metal wiring layers 111 are located at different layers within the insulating layer, thus separating the metal wiring layers 111 from each other) and a plurality of vertical via bars 112 disposed between the metal wiring layers 111 located at different layers within the insulating layer. The vertical via bars 112 may be made of copper (or may be implemented using other metals) and are electrically connected to each metal wiring layer 111.

[0022] Specifically, the first sealing ring 11 may include five metal wiring layers 111, which can be defined from bottom to top as M1, M2, M3, M4, and M5, with M5 also referred to as the top metal wiring layer. M1 is electrically connected to the first source / drain region 103 and adjacent metal wiring layers 111 via vertical via connectors 112. The first sealing ring 11 can be fabricated during the formation of the wiring layer and contact portion within the chip region 101, and can be fabricated using a dual damascene process. In this embodiment, the width of the first sealing ring 101 is approximately 3 micrometers.

[0023] It is worth mentioning that a number of vertical natural capacitors (VNCAPs) 200 connected in series are formed inside the first sealing ring 11. Specifically, a vertical natural capacitor (VNCAP) 200 is formed in each metal wiring layer of M1, M2, and M3 in the first sealing ring 11, and the vertical natural capacitors (VNCAPs) 200 formed in M1, M2, and M3 are connected in series.

[0024] Specifically, three metal wires are formed in M1, M2, and M3 of the first sealing ring 11, and an insulating dielectric layer is filled between adjacent metal wires. The two metal wires on both sides are electrically connected to M4 and M5 to serve as the cathode plate 20 of the vertical natural capacitor 200 for connecting the system low voltage Vss. The middle metal wire is insulated from M4 and M5 and serves as the anode plate 21 of the vertical natural capacitor 200 for connecting the external pad.

[0025] It should be noted that this embodiment only illustrates the formation of a vertical natural capacitor (VNCAP) 200 in a portion of the metal wiring layers in the first sealing ring 11. Of course, a vertical natural capacitor (VNCAP) 200 is formed in each of the metal wiring layers M1, M2, M3, and M4 in the first sealing ring 11, and the principle is the same as above.

[0026] Furthermore, this embodiment only illustrates the example of the first sealing ring 11 having five metal wiring layers. The metal wiring layers in the first sealing ring 11 can also be other layers such as 3, 4, 6, 7, etc., and this embodiment does not limit them here.

[0027] It is worth mentioning that one or more metal wiring layers 111 in the first sealing ring 11 can also form two, four or even more metal wiring layers, so that one or more vertical natural capacitors (VNCAP) 200 can be formed in each metal wiring layer 111. For example, when a metal wiring layer 111 in the first sealing ring 11 includes two metal wiring layers, one of the metal wiring layers is electrically connected to the other metal wiring layer to serve as the cathode plate 20 of the vertical natural capacitor 200, and the other metal wiring layer is insulated from the other metal wiring layer to serve as the anode plate 21 of the vertical natural capacitor 200. In this case, a vertical natural capacitor (VNCAP) 200 is formed in the metal wiring layer 111. When a certain metal wiring layer 111 in the first sealing ring 11 includes 4 metal wires, two of the metal wires are electrically connected to other metal wiring layers to serve as a pair of cathode plates 20 of the vertical natural capacitor 200, and the other two metal wires are insulated from other metal wiring layers to serve as another pair of anode plates 21 of the vertical natural capacitor 200. At this time, two vertical natural capacitors 200 are formed in the metal wiring layer 111.

[0028] It is understandable that if at least two metal wires are formed in each metal wiring layer 111, and at least one metal wire is electrically connected as the cathode plate of the vertical natural capacitor 200, and at least one metal wire is insulatedly connected as the anode plate 21 of the vertical natural capacitor 200, then at least one vertical natural capacitor 200 is formed in each metal wiring layer 111, and a set of vertical natural capacitors 200 connected in series is formed in the first sealing ring 11.

[0029] The second sealing ring structure 12 is formed on the second source / drain region 104, embedded in the insulating layer, corresponding to the sealing ring region 102, and surrounding the inner or outer side of the first sealing ring 11. Specifically, in this embodiment, the second sealing ring 12 surrounds the outer side of the first sealing ring 11. The second sealing ring 12 may include: a plurality of stacked metal wiring layers 111 and a plurality of through-hole connectors 112 disposed between the metal wiring layers 111. Like the first sealing ring 11, the second sealing ring 12 may include five stacked metal wiring layers 111, and the metal wiring layers 111 of the second sealing ring 12 are flush with the metal wiring layers 111 of the first sealing ring 11.

[0030] It is worth mentioning that we should continue to refer to Figure 2 The metal wiring layer 111 is comb-shaped.

[0031] The first sealing ring 11 and the second sealing ring 12 can be manufactured simultaneously using the same process. In an embodiment, the width of the first sealing ring 11 is equal to the width of the second sealing ring 12. For example, the width of the second sealing ring 12 is 3 micrometers. Furthermore, the first sealing ring 11 and the second sealing ring 12 are spaced approximately 2 micrometers apart and approximately 6 micrometers apart from the chip region 101.

[0032] It should be noted that this embodiment is described using electrical connection via vertical via connector 112, but this embodiment is not limited thereto. Electrical connections between adjacent metal wiring layers and between metal wiring layers and source / drain areas can also be made via vias, or even without vias. This embodiment does not limit the method of electrical connection, and those skilled in the art can choose flexibly as needed.

[0033] It is worth mentioning that the second sealing ring 12 can also have the same structure as the first sealing ring 11, that is, the internal structure of the second sealing ring 12 can be changed to form a vertical natural capacitor (VNCAP) 200 inside.

[0034] It is worth mentioning that this embodiment only illustrates that the first sealing ring 11 and the second sealing ring 12 include 5 metal layers. However, this application should not be limited to this, and those skilled in the art can flexibly choose the number of metal layers as needed.

[0035] Compared with the prior art, this embodiment integrates the vertical natural capacitor within the first sealing ring 11, resulting in higher chip integration, saving space, and achieving chip miniaturization.

[0036] The semiconductor device in this embodiment may be a volatile memory device such as a DRAM device or an SRAM device, or a non-volatile memory device such as a Flash device, a PRAM device, an MRAM device, or an RRAM device.

[0037] Furthermore, chips with the aforementioned semiconductor devices can be used in various electronic devices, specifically smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0038] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0039] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, wherein a chip region and a dicing line region are formed on the semiconductor substrate; A first sealing ring is disposed between the chip area and the dicing line area, and the first sealing ring surrounds the chip area; A vertical natural capacitor is formed inside the first sealing ring; The first sealing ring includes five stacked and electrically connected metal wiring layers, wherein the vertical natural capacitor is formed within three consecutive metal wiring layers; The number of vertical natural capacitors constitutes one, and the configuration is as follows: three metal wires are formed in each of the three consecutive metal wiring layers, and an insulating dielectric layer is filled between adjacent metal wires. The two metal wires on both sides are electrically connected to the other metal wiring layers and serve as one plate of the vertical natural capacitor, while the middle metal wire is insulated from the other metal wiring layers and serves as the other plate of the vertical natural capacitor.

2. The semiconductor device according to claim 1, characterized in that, The electrically connected metal wiring serves as the cathode plate of the vertical natural capacitor and is used to connect to the system's low voltage. The insulated metal wiring serves as the anode plate of the vertical natural capacitor and is used to connect to external pads.

3. The semiconductor device according to claim 1, characterized in that, An active / drain region is formed in the semiconductor substrate, the first sealing ring is disposed on the active / drain region, and the metal wiring layer is electrically connected to the active / drain region.

4. The semiconductor device according to claim 1, characterized in that, Also includes: A second sealing ring is provided around the first sealing ring. The second sealing ring includes a plurality of stacked and electrically connected metal wiring layers, wherein the second sealing ring is formed in the same manner after the first sealing ring is formed.

Images