MOS transistor and application for detecting the opening of a closed container

Abstract

Embodiments of the present disclosure relate to MOS transistors and applications for detecting the opening of a closed container. An integrated circuit includes a first substrate. The MOS transistor has a first polysilicon region that is electrically isolated from the first substrate and includes a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and the first substrate. The second polysilicon region includes a source region, a substrate region, and a drain region of the MOS transistor. The first polysilicon region is located between a region of the first substrate and the second polysilicon region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority of French patent application No. 2010681 filed on October 19, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments and implementations relate to microelectronics and in particular to MOS transistors isolated from a substrate of an integrated circuit, but also to detecting the opening of a closed container containing, for example, a valuable product, such as a perfume bottle or a bottle of wine. Background Art

[0004] Certain applications require integrated circuits that include MOS transistors that are electrically isolated from a substrate of the integrated circuit.

[0005] Therefore, there is a need to propose a MOS transistor which has a structure that is easy to produce and is particularly compatible with conventional CMOS manufacturing methods, which in particular use two polysilicon levels, but which is also compatible with non-volatile memory cell manufacturing methods having a selection transistor with a gate buried in the substrate. Summary of the invention

[0006] According to one aspect, a system includes an integrated circuit comprising a first substrate and at least one first MOS transistor.

[0007] The first MOS transistor comprises: a first polysilicon region, which is electrically isolated from the first substrate and includes a gate region; a second polysilicon region, which is electrically isolated from the first polysilicon region and the first substrate, and the second polysilicon region includes a source region, a substrate region and a drain region of the first transistor; the first polysilicon region is located between the region of the first substrate and the second polysilicon region.

[0008] Such a transistor thus comprises two polysilicon regions, making it compatible with conventional CMOS manufacturing methods using two polysilicon levels.

[0009] The gate region of the transistor is incorporated into a first polysilicon region (first polysilicon level) located between a substrate of the integrated circuit (referred to as "first substrate") and a second polysilicon region (second polysilicon level).

[0010] Furthermore, the source region and the drain region of the first transistor and the substrate region of the first transistor are located in the second polysilicon region which is electrically isolated from the first region and is located above the first polysilicon region.

[0011] Therefore, even if the first polysilicon region is heavily doped (for example, as a result of conventional manufacturing methods using in-situ doping of the first polysilicon level), this will not interfere with the operation of the first transistor because the active source and drain regions and the channel region (contained in the substrate region of the transistor) are located in the second polysilicon region, rather than in the first polysilicon region.

[0012] According to one embodiment, the substrate region of the first transistor is advantageously less heavily doped than the first polysilicon region.

[0013] This reduces or even eliminates leakage between the source and drain regions of the first transistor.

[0014] As a reference, and by way of example, the substrate region of the first transistor may include intrinsic polysilicon, ie, having a surface area of ​​less than 10 15 Atom / cm 3 Doping or less than 10 17 Atom / cm 3 (For example, approximately 5×10 16 Atom / cm 3 ) of the dopant concentration.

[0015] The first polysilicon region may have a thickness greater than 10 19 Atom / cm 3 This may correspond to the in-situ doping typically used in some double-polysilicon CMOS approaches.

[0016] The doping of the substrate region of the first transistor may also be used to advantageously adjust the threshold voltage of the first transistor.

[0017] The first transistor may be a PMOS transistor or an NMOS transistor.

[0018] According to a first alternative embodiment, the integrated circuit may include an isolation trench, for example an isolation trench of the shallow trench type (STI: Shallow Trench Isolation), which is located in the first substrate of the integrated circuit, and therefore, the first polysilicon region may be located above (and supported by) the isolation trench.

[0019] According to an embodiment compatible with this first alternative embodiment, the first polysilicon region may protrude from the second polysilicon region in the source-drain direction of the first transistor.

[0020] Furthermore, in the source-drain direction, the second polysilicon region is located on the first polysilicon region via a first dielectric region, and the first dielectric region may include, for example, a gate oxide layer, which is located on both sides of the silicon oxide-silicon nitride-silicon oxide stack.

[0021] According to this embodiment, the gate contact may thus advantageously be produced on a protruding portion of the first polysilicon region.

[0022] According to another embodiment, also compatible with this first alternative embodiment, the first polysilicon region protrudes from the second polysilicon region in a direction perpendicular to the source-drain direction of the first transistor.

[0023] In addition, in the source-drain direction of the first transistor, the size of the second polysilicon region is larger than that of the first polysilicon region, and the second polysilicon region is located on the first polysilicon region and the isolation trench via the second dielectric region. For example, the second dielectric region also has a silicon oxide-silicon nitride-silicon oxide type.

[0024] This embodiment thus achieves a more compact structure, wherein the gate contact can thus be produced on that portion of the first polysilicon region which protrudes from the second polysilicon region in a direction perpendicular to the source-drain direction.

[0025] According to a further embodiment, also compatible with this first alternative embodiment, the first polysilicon region protrudes from the second polysilicon region in a direction perpendicular to the source-drain direction of the first transistor.

[0026] In addition, in the source-drain direction of the first transistor, the size of the second polysilicon region is larger than that of the first polysilicon region, and the second polysilicon region is located on the first polysilicon region via a third dielectric region (eg, gate oxide layer) and also on the isolation trench.

[0027] In this structure, there is no need to use a silicon oxide-silicon nitride-silicon oxide stack while maintaining a compact structure.

[0028] According to a second alternative embodiment, the integrated circuit may include an isolation trench (eg also a shallow trench type trench) in the first substrate and a dielectric layer surrounding the first polysilicon region.

[0029] The first polysilicon region surrounded by its dielectric layer extends through the isolation trench into the first substrate of the integrated circuit.

[0030] A substrate region of the first transistor is at least partially located on one end of the first polysilicon region surrounded by the dielectric layer, and a source region and a drain region are located on the isolation trench.

[0031] In this second alternative embodiment, therefore, the first polysilicon region isolated from the first substrate of the integrated circuit is a buried region, which makes this alternative embodiment compatible with a method of manufacturing a non-volatile select transistor memory with a buried gate.

[0032] Thus, when the integrated circuit comprises at least one non-volatile memory cell of the select transistor type having a gate buried in the first substrate, the first polysilicon region may have a shape similar to that of the buried gate of said select transistor.

[0033] According to another embodiment, an integrated circuit includes: a dielectric layer, which is arranged between a first polysilicon region and a first substrate (of the integrated circuit); and a second MOS transistor, which includes a source region, a drain region, and a substrate region of the second transistor in the first substrate, which is located between the source region and the drain region and is covered by the dielectric layer.

[0034] Therefore, the first polysilicon region includes a gate region shared by the first transistor and the second transistor.

[0035] This embodiment provides a particularly compact two-transistor structure, wherein one of the transistors is isolated from a first substrate of the integrated circuit and the other transistor is produced in the first substrate.

[0036] The second transistor may be an NMOS transistor or a PMOS transistor.

[0037] As mentioned above, the first transistor may also be an NMOS transistor or a PMOS transistor.

[0038] Furthermore, when the first transistor is an NMOS transistor and the second transistor is a PMOS transistor, or when the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, two complementary transistors (CMOS transistors) are obtained which are particularly compact and compatible with conventional CMOS transistor manufacturing methods.

[0039] According to another aspect, a method for manufacturing a MOS transistor in an integrated circuit having a first substrate includes: forming a first polysilicon region, which is electrically isolated from the first substrate; forming a second polysilicon region, which is electrically isolated from the first polysilicon region and the first substrate, the first polysilicon region being located between a region of the first substrate and the second polysilicon region; forming a source region and a drain region in the second polysilicon region, the source region and the drain region being located on either side of a substrate region of the transistor; forming at least one source contact region on the source region and at least one drain contact region on the drain region; and forming at least one gate contact region on the first polysilicon region.

[0040] According to one embodiment, the method includes in-situ doping of the first polysilicon region.

[0041] According to one embodiment, the method includes doping the substrate region with an undoped substrate region or with a lower in-situ doping level than the first polysilicon region.

[0042] According to one embodiment, a method includes forming an isolation trench in a first substrate, and forming a first polysilicon region over the isolation trench.

[0043] According to one embodiment, the first polysilicon region may be formed simultaneously with the production of the non-volatile memory select transistor gate buried in the first substrate.

[0044] According to another possible implementation, the first polysilicon region is formed simultaneously with the formation of the floating gate of the dual-gate state transistor of the non-volatile memory cell.

[0045] According to one embodiment, the second polysilicon region may be formed simultaneously with the formation of the gate of the low voltage transistor.

[0046] The transistor may be a PMOS or NMOS transistor.

[0047] Such a double polysilicon MOS transistor with the gate in the first stage can advantageously be used to detect the opening of a container, as will be explained in more detail below.

[0048] Nowadays, in order to determine whether a product is suitable for use or sale, there is an increasing need to determine whether a container containing a product has not been opened, for example in view of the replacement of the original product with a counterfeit product or a low-quality product.

[0049] Visual inspection of the container is no longer sufficient.

[0050] It has therefore been proposed to use an electrically conductive wire connecting two output terminals of an integrated circuit in order to detect the non-opening or the opening of a container, which corresponds respectively to the non-severance or the severance of said wire.

[0051] More specifically, the integrated circuit will compare the voltages present at the two output terminals to deduce whether the wire has been cut.

[0052] However, it appears that if the (once severed) wire had been repaired, for example by welding or conductive glue, the comparison of the voltages at the two output terminals of the integrated circuit would again correspond to the non-opening of the container, when in fact the container may have actually been opened.

[0053] Therefore, there is also a need to be able to detect not only a current cut of a wire, but also a past cut of a wire which was subsequently repaired, for example using a conductive glue or a solder joint, which may therefore be synonymous, for example, with attempting to open or opening a container in which such a wire is located, wherein the wire was repaired after said opening.

[0054] This problem is solved using the first transistor defined above, which has a double polysilicon level with a gate in the first level and is isolated from the substrate of the integrated circuit.

[0055] More specifically, according to one embodiment, for example, the first transistor is a PMOS transistor whose source region is connected to ground and has a threshold voltage such that the first transistor is turned on when zero voltage is applied to its gate and is turned off when there is a bias (e.g., a negative bias) at its gate.

[0056] The first PMOS transistor is therefore a so-called "normally-on" transistor, which term is well known to those skilled in the art.

[0057] Therefore, a system may be proposed, comprising: a closed container; an integrated circuit as defined above and comprising the “normally on” PMOS transistor.

[0058] The integrated circuit has a first terminal and a second terminal connected by a conductive wire having a severable portion and arranged to be severed at the severable portion thereof in the event of opening or attempting to open the container.

[0059] The system also includes a detection device configured to detect the cutting of the cuttable portion, the detection device including the following items within the integrated circuit: a first capacitor electrically isolated from a first substrate of the integrated circuit and connected to a first terminal of the integrated circuit; the first PMOS transistor mentioned above, whose gate is connected to a second terminal of the integrated circuit and whose source is connected to ground; a second capacitor electrically isolated from the first substrate of the integrated circuit and having a first electrode, which is connected to a drain of the first PMOS transistor; and a measurement circuit configured to measure the voltage of the first electrode.

[0060] Furthermore, a voltage at the first electrode which is below a threshold value therefore indicates a present or past severance of the severable portion of the conductive line.

[0061] However, such a system allowing detection of current or past cutting of a cuttable portion of a conducting line is not limited to the use of such a particular first PMOS transistor.

[0062] In fact, in a more general manner, a first MOS transistor can be used, whose source and drain regions are electrically isolated from the first substrate (of the integrated circuit), whose gate region is connected to the second terminal of the integrated circuit, and the first MOS transistor is configured to be in an on-state when there is a zero voltage applied to its gate and to be in an off-state when there is a non-zero bias voltage at its gate region.

[0063] Thus, in a more general manner, a system comprises: a closed container; an integrated circuit having a first substrate and a first terminal and a second terminal, the first terminal and the second terminal being connected by a conductive wire having a cuttable portion and arranged to be cut at its cuttable portion in the event of opening or attempting to open the container; and a detection device configured to detect the cutting of the cuttable portion, the detection device comprising the following items within the integrated circuit: a first capacitor electrically isolated from the first substrate of the integrated circuit and connected to the first terminal; a first MOS transistor having a source region and a drain region electrically isolated from the first substrate, a gate region connected to the second terminal, and the first MOS transistor being configured to be in an on-state when there is a zero voltage applied to its gate and to be in an off-state when there is a non-zero bias voltage at its gate region; a second capacitor electrically isolated from the first substrate of the integrated circuit and having a first electrode connected to the drain of the first PMOS transistor; and a measurement circuit configured to measure a voltage of the first electrode, a voltage of the first electrode below a threshold value indicating a present or past cutting of the cuttable portion.

[0064] The first MOS transistor can be a MOS transistor defined above (whose gate is in the first polysilicon region and whose source region, substrate region and drain region are in the second polysilicon region) or the first MOS transistor can be another transistor having another structure isolating it from the first substrate of the integrated circuit.

[0065] According to one embodiment, the first capacitor and the second capacitor are capacitors including two polysilicon electrodes separated by a dielectric and located on an isolation region of the integrated circuit.

[0066] Contactless passive transponders, in particular NFC (“Near Field Communication”) transponders, such as tags, are well known to the person skilled in the art.

[0067] Of particular interest is their use to detect the opening or attempted opening (by a malicious third party) of closed containers containing, for example, valuable products (such as perfume bottles).

[0068] Near Field Communication (NFC) is a wireless connection technology that enables communication between an electronic device (such as a contactless integrated circuit card or tag) and a reader over a short distance (eg, 10 cm).

[0069] In a more general manner, NFC technology is standardized by the NFC Forum Consortium.

[0070] NFC technology is particularly suitable for connecting any type of user device and enabling fast and simple communication.

[0071] A contactless transponder is a transponder capable of exchanging information via an antenna with a contactless reader according to a contactless communication protocol.

[0072] An NFC transponder, which is a contactless transponder, is a transponder compatible with NFC technology.

[0073] NFC technology is an open technology platform standardized according to ISO / IEC 18092 and ISO / IEC 21481 standards, but it includes many existing standards, such as Type A and Type B protocols defined in standard ISO-14443, which may be communication protocols that may be used for NFC technology.

[0074] Contactless technology can also be used with RFID (Radio Frequency Identification) transponders that are compatible with the standards ISO 15693 and ISO 18000-3.

[0075] When information is transmitted between a reader and a passive transponder, the reader generates via its antenna a magnetic field which is typically a sine wave (carrier wave) of 13.56 MHz according to the commonly used standard.

[0076] To transmit information from the reader to the transponder, the reader uses amplitude modulation of the carrier wave.

[0077] The transponder demodulates the received carrier wave in order to derive therefrom the data transmitted from the reader.

[0078] In order to transmit information from the transponder to the reader, the reader generates an unmodulated magnetic field (carrier wave). The antenna of the transponder then modulates the field generated by the reader according to the information to be transmitted. The frequency of this modulation corresponds to a subcarrier of the carrier wave. The frequency of this subcarrier wave depends on the communication protocol used and can be equal to 848 kHz, for example.

[0079] This modulation is performed by varying the load of the terminals connected to the antenna of the transponder.

[0080] In other words, the transponder back-modulates the waves coming from the reader to transmit the information and, for the transmission of the information, does not integrate an actual transmission device or transmitter, such as a transmitter capable of generating its own magnetic field during transmission. Such a transponder without a transmitter is called a passive transponder, as opposed to an active transponder comprising a transmitter.

[0081] Typically, a passive transponder does not have any power source as it uses the waves from the reader to power its integrated circuit.

[0082] As mentioned above, information is transmitted from the passive transponder to the reader by load modulation.

[0083] More specifically, by varying the load on the terminals of the transponder's antenna, the output impedance of the reader's antenna changes due to the magnetic coupling between the two antennas.

[0084] This load variation performed during load modulation results in an amplitude and / or phase modulation of the signal (voltage or current) at the reader's antenna. A replica of the antenna current is generated and injected into the reader's receive chain where it is demodulated and processed to extract the transmitted information.

[0085] According to one embodiment, the system further comprises a contactless passive transponder configured to communicate with the reader via an antenna using a carrier signal, the transponder comprising an integrated circuit further having two antenna terminals connected to the antenna.

[0086] The integrated circuit also includes: a comparison circuit configured to compare the voltage of the first electrode of the second capacitor with the threshold; and a processing circuit configured to: in response to a first command from the reader, command the first capacitor to be charged; in response to a second command from the reader, command the second capacitor to be charged; in response to an activation command from the reader, activate the measurement circuit; and in response to a read command from the reader, transmit the result of the comparison to the reader.

[0087] According to another aspect, a method for detecting whether a cuttable portion of a conductive wire of the system defined above is cut or has been cut before comprises: charging a first capacitor; charging a second capacitor; measuring the voltage of a first electrode of the second capacitor at least once; and analyzing the result of the comparison between the measured voltage and the threshold value.

[0088] According to one embodiment, in order to monitor the non-cutting of the wire, and when only two containers are charged once, the method may include: measuring the voltage of the first electrode multiple times at interval measurement times; and generating multiple comparisons between these measured voltages and the threshold value; wherein a measured voltage below the threshold value at the measurement time indicates that the cuttable part is cut at or before the measurement time. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Other advantages and features will become apparent upon examination of the detailed description of non-limiting examples and embodiments of the invention and from the accompanying drawings, in which:

[0090] Figures 1 to 7 illustrates a cross-sectional view of a transistor embodiment;

[0091] Figure 8 is a flow chart of the production method;

[0092] Figures 9 to 14 The steps in the production method are shown;

[0093] Fig.15 illustrates a cross-sectional view of a transistor embodiment;

[0094] Figures 16 to 18 The use in a package opening detection embodiment is shown;

[0095] Fig.19 is a circuit diagram of a package opening detection circuit;

[0096] Fig. 20 Picture shows Fig.19 A cross-sectional view of a capacitor of a circuit;

[0097] Fig.21 The relationship between current and voltage is illustrated;

[0098] Fig. 22 illustrates a cross-sectional view of a transistor embodiment;

[0099] Figure 23 to Figure 24 is a flow chart of the detection method;

[0100] Fig.25 is a block diagram of a near field communication implementation; and

[0101] Fig.26 It is a flowchart of the operation. DETAILED DESCRIPTION

[0102] exist Figure 1 In the drawings, reference symbol IC is used to denote an integrated circuit including a substrate SB1 (hereinafter referred to as "first substrate" to distinguish it from a substrate region RSB of a first transistor TRP), and the structure of the integrated circuit will now be described.

[0103] The first transistor TRP (in this case a PMOS transistor) has a first polysilicon region P1 located on the insulating material of a shallow trench type isolation trench 1 made in a first substrate SB1.

[0104] Therefore, the first polysilicon region P1 is electrically isolated from the first substrate SB1.

[0105] The first polysilicon region P1 includes a gate region RG of the first transistor TRP.

[0106] The first transistor TRP further includes a second polysilicon region P2 which is electrically isolated from the first polysilicon region P1 via a first dielectric region 2 on which the second polysilicon region P2 is located.

[0107] In this example, the first dielectric region 2 comprises a gate oxide layer 21 which is positioned on either side of two dielectric stacks 20 , each dielectric stack comprising, for example, a silicon oxide-silicon nitride-silicon oxide (ONO) stack.

[0108] Since the second polysilicon region P2 is electrically isolated from the first polysilicon region P1, and since the first polysilicon region P1 is electrically isolated from the first substrate SB1, the second polysilicon region P2 is also electrically isolated from the first substrate SB1.

[0109] The second polysilicon region P2 includes a source region RS, a substrate region RSB, and a drain region RD of the first transistor TRP.

[0110] Therefore, if Figure 1 As shown, the first polysilicon region P1 is positioned between the region Z of the first substrate SB1 and the second polysilicon region P2.

[0111] In this example embodiment, the first polysilicon region P1 protrudes from (ie, exceeds) the second polysilicon region P2 in the source-drain direction of the first transistor, and the second polysilicon region is located on the first polysilicon region via the first dielectric region 2 as described above.

[0112] The protruding portion P1D of the first polysilicon region P1 allows the production of a silicided region SG of a gate contact on its surface, which silicided region SG is intended to receive a contact CG of conventional and known structure.

[0113] The first polysilicon region P1 may be doped quite heavily, for example, with a doping level greater than or equal to 10 19 Atom / cm 3 (atoms / cm 3 ) of the dopant concentration.

[0114] The substrate region of the first transistor is less heavily doped than the first polysilicon region P1.

[0115] Therefore, the substrate region RSB (vertical to the gate oxide layer 21) may include intrinsic polysilicon, that is, having a thickness less than or equal to 10 15 Atom / cm 3 The substrate region RSB may also be less than 10 17 Atom / cm 3 The dopant concentration of the first polysilicon region P1 is doped while of course remaining lower than the dopant concentration of the first polysilicon region P1.

[0116] Doping of the substrate region RSB allows adjusting the threshold voltage of the first transistor TRP.

[0117] In this example, since the first transistor TRP is a PMOS transistor, the source region RS and the drain region RD are P+ doped (and perpendicular to the gate oxide layer 20).

[0118] Furthermore, in a conventional and known manner, the source region RS comprises on its top surface a silicided source contact region SS intended to receive a source contact CS having a conventional structure.

[0119] The drain region RD comprises, on its top surface, a silicided drain contact region SD intended to receive a drain contact CD having a conventional structure.

[0120] Figure 2 The first transistor TRN shown in FIG. Figure 1 The first transistor TRP in FIG. 1 differs only in that the transistor TRN is an NMOS transistor which in this case has an N+ doped source region RS and a drain region RD.

[0121] Figure 3 and Figure 4 ( Figure 4 is along Figure 3 1 ) schematically shows another embodiment of the first transistor TRP, which is also a PMOS transistor, wherein it should be understood that, depending on the doping types of its source and drain regions, the first transistor TRP may also be an NMOS transistor.

[0122] exist Figure 3 In the embodiment shown in , the size of the second polysilicon region P2 is shown in this case to be larger than the size of the first polysilicon region P1 in the source-drain direction.

[0123] In this case, the second polysilicon region P2 is located on the first polysilicon region and the isolation trench 1 via the second dielectric region 3. Similar to the first dielectric region 2, the second dielectric region includes a silicon oxide-silicon nitride-silicon oxide stack 30 and a gate oxide layer 31.

[0124] The source region and the drain region are located on the isolation region via the stack 30 , and the substrate region RSB is partially located on the first polysilicon region 1 via the gate oxide layer 31 .

[0125] In addition, if Figure 4 As shown in , in this case, the first polysilicon region P1 protrudes (ie, extends) from the second polysilicon region P2 in a direction perpendicular to the source-drain direction of the first transistor.

[0126] Furthermore, a silicided gate contact region SG intended to receive a gate contact CG is again positioned on this protruding portion P1D.

[0127] The substrate region RSB further comprises on its top surface a silicided substrate contact region SSB which is intended to receive a substrate contact CRSB.

[0128] It should be noted that in Figure 1 and Figure 2 In the figure, for the sake of simplicity, the substrate contact portion is not shown.

[0129] Figure 5 The transistor TRP in Figure 3 The transistor TRP in FIG. 1 differs in that the silicon oxide-silicon nitride-silicon oxide stack 30 has been removed.

[0130] Furthermore, in this embodiment, the second polysilicon region P2 is located on the first polysilicon region P1 via the third dielectric region 40 , which in this case is a gate oxide layer, and is also located directly on the isolation trench 1 at the source region RS and the drain region RD.

[0131] In addition, the first polysilicon region P1 is Figure 4 The second polysilicon region P2 protrudes (ie, extends) from the second polysilicon region P2 in a direction perpendicular to the source-drain direction of the first transistor in a manner similar to that shown in .

[0132] Now more specifically refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 Another alternative embodiment of the first MOS transistor is shown, which is also a PMOS transistor, wherein it should be understood that the first MOS transistor may also be an NMOS transistor depending on the doping type of its source and drain regions.

[0133] Furthermore, the integrated circuit IC comprises an isolation trench 1 in the first substrate SB1 .

[0134] In this alternative embodiment, the first polysilicon region P1 is surrounded by a dielectric layer 5 (eg, silicon dioxide).

[0135] Furthermore, the first polysilicon region P1 surrounded by its dielectric layer 5 extends into the first substrate SB1 through the isolation trench 5 .

[0136] In addition, the second polysilicon region P2 still includes a source region RS, a drain region RD, and a substrate region RSB located between the source region RS and the drain region RD.

[0137] The substrate region RSB of the transistor TRP is at least partially located on the end 51 of the first polysilicon region surrounded by the dielectric layer 5 , while the source region RS and the drain region RD are located on the isolation trench 1 .

[0138] Therefore, also in this alternative embodiment, the first polysilicon region P1 is positioned between the zone Z of the first substrate and the second polysilicon region P2 .

[0139] The second polysilicon region is again electrically isolated from the first polysilicon region, and is also electrically isolated from the first substrate SB1.

[0140] like Figure 7 ( Figure 7 is along Figure 6 As shown in the cross section of line VII-VII in FIG. 1 , the first polysilicon region P1 surrounded by its dielectric layer 5 protrudes (ie, extends) from the second polysilicon region P2 in a direction perpendicular to the drain-source direction, as shown in FIG. Figure 4 As described, this allows the gate contact CG to make contact with the silicide region SG.

[0141] This alternative embodiment is therefore compatible with a method of manufacturing a non-volatile memory cell of the type having a selection transistor having a gate buried in the first substrate SB1.

[0142] More specifically, the buried first polysilicon region can be produced simultaneously with the production of the buried gates of the select transistors of the memories.

[0143] Furthermore, therefore, the first polysilicon region has, for example, a shape similar to that of a buried gate of such a selection transistor.

[0144] In practice, the first MOS transistor comprises, on the top surface of the second polysilicon region P2 , a protection layer intended to protect the underlying portion of the second polysilicon region P2 during a silicidation step in order to obtain a silicided area.

[0145] exist Figures 1 to 7 For simplicity, the protective layer is not shown in these figures, but will be Figure 8 The protective layer is mentioned in the description of Figures 13 to 15 The protective layer is shown in FIG.

[0146] Now more specifically refer to Figure 8 One embodiment of a method of manufacturing a first MOS transistor is described below.

[0147] In the substrate SB1, a first polysilicon region P1 isolated from the first substrate SB1 is formed (step ST80).

[0148] For example, after producing the shallow trench type isolation trench 1 in a conventional manner, the formation of the first polysilicon region P1 may include depositing polysilicon and then etching (e.g. Figures 1 to 5 ), or deposited in deep trenches followed by chemical mechanical polishing (e.g., in Figure 6 and Figure 7 In this respect, more specifically, after a shallow trench 1 has been produced, a deep engraving is performed through the trench 1 to produce a deep trench, which is then oxidized. A polysilicon layer is then deposited to fill the trench, and excess polysilicon is removed, for example by chemical mechanical polishing.

[0149] Alternatively, if steps similar to those of a conventional CMOS manufacturing method are used, in-situ doping ST81 of the first polysilicon region may be provided.

[0150] Then, in step ST82 , a second polysilicon region P2 isolated from the first polysilicon region P1 and the first substrate SB1 is formed.

[0151] For reference information, such formation may first include forming a dielectric region (e.g., silicon oxide layer growth) on the polysilicon region formed in step ST80, and then depositing a second polysilicon level followed by etching, or in the case of a buried first polysilicon region, depositing a polysilicon level on the isolation trench and then etching to form a second polysilicon region P2.

[0152] At this stage, a first polysilicon region P1 is obtained between the region of the first substrate SB1 and the second polysilicon region P2 .

[0153] Then, in a step ST83 , source and drain regions RS and RD are formed in a conventional manner known per se, wherein a substrate region RSB is located between the source and drain regions and is less heavily doped than the first polysilicon region P1 .

[0154] Optionally, in order to adjust the threshold voltage of the transistor, local doping of the substrate region RSB may be performed.

[0155] Then, in step ST84 , after the non-silicided regions have been protected with the protective layer mentioned above, the silicided regions SS, SB and SG are formed in a conventional and known manner.

[0156] Now more specifically refer to Figures 9 to 14 , Figures 9 to 14 A more detailed diagram for producing a transistor such as Figure 1 An embodiment of the method of the transistor described in .

[0157] exist Fig. 9 In the present invention, after producing the isolation trench 1 in the first substrate SB1 of the integrated circuit in a conventional and known manner, the first polysilicon region P1 is formed by polysilicon deposition and then etching.

[0158] For example, the formation of the first polysilicon region may be performed simultaneously with the formation of the floating gate of the dual gate state transistor of the non-volatile memory cell.

[0159] exist Figures 10 to 14 In the figure, for the sake of simplicity, the first substrate SB1 is no longer shown.

[0160] Then, if Fig.10 As shown in FIG, the first polysilicon region P1 is covered by the first dielectric region 2, which includes the growth of a silicon oxide layer and the deposition of a silicon oxide-silicon nitride-silicon oxide stack. In practice, the silicon oxide-silicon nitride-silicon oxide stack is first deposited, and then the area where the silicon oxide layer growth will occur is masked. The stack is removed in this area, and then the silicon oxide layer growth is performed in this area.

[0161] Then, if Fig.11 As shown in FIG. 1 , a second polysilicon region P2 located on a portion of the dielectric region 2 is formed by depositing a second crystalline silicon level and then etching.

[0162] For example, the formation of the second polysilicon region may be performed simultaneously with the formation of gates of low voltage transistors (ie, transistors capable of withstanding gate-source voltages of, for example, less than or equal to 3 volts) of the memory circuit arrangement.

[0163] exist Fig.12 In the embodiment of the present invention, lateral isolation regions or spacers ESP1 on either side of the first area P1 , and spacers ESP2 on either side of the second area P2 are produced in a conventional and known manner.

[0164] The second polysilicon region P2 is then locally implanted to form a source region RS and a drain region RD.

[0165] Then, a layer of ( Fig.13 ) The protective layer SPRT mentioned above is used in Fig.14 The underlying portion of the second polysilicon region P2 is protected during the silicidation step described in .

[0166] More specifically, during this silicidation step, silicided regions SS, SG and SD are produced in a conventional and known manner.

[0167] Now more specifically refer to Fig.15 , Fig.15 An example embodiment of two transistors TR1 and TR2 is shown.

[0168] The first transistor TR1 is connected to the reference Figure 1 and Figure 2 The described structure is similar to the structure of a transistor.

[0169] In this example, the first transistor TR1 is an NMOS transistor, but it goes without saying that the transistor TR1 may also be a P+ doped PMOS transistor having a source region RS1 and a drain region RD1 .

[0170] exist Fig.15 In FIG. 4 , a layer is also shown which protects from silicidation and covers the substrate region RSB of the transistor TR1 , and a part of the source region RS1 and the drain region RD1 .

[0171] The first polysilicon region P1 of the first transistor TR1 is located on the first substrate SB1 of the integrated circuit IC via a dielectric layer 6 (eg, a gate oxide layer).

[0172] Furthermore, therefore, the integrated circuit IC comprises a second transistor TR2 which in this case is an NMOS transistor.

[0173] The second transistor TR2 includes a source region RS2 , a drain region RD2 , and a substrate region RSB2 between the source region and the drain region in the first substrate SB1 , and the substrate region RSB2 is covered by a dielectric layer 2 .

[0174] In addition, the first polysilicon region P1 includes a gate region shared by the first transistor TR1 and the second transistor TR2 .

[0175] It goes without saying that if the source region RS2 and the drain region RD2 are P+ doped, the second transistor TR2 may be a PMOS transistor.

[0176] It can thus be seen that if one of the two transistors is an NMOS transistor and the other transistor is a PMOS transistor, two complementary transistors are obtained with a compact structure.

[0177] Now more specifically refer to Fig.16 and subsequent figures, which diagrammatically illustrate embodiments and implementations of a system SYS for detecting the opening or attempted opening of a closed container.

[0178] exist Fig.16 In the invention, the system SYS comprises a closed container RCP and an integrated circuit having a first terminal TDI and a second terminal TDO connected by a conductive wire FL1.

[0179] The wire has a cuttable portion FL10 and is arranged to be cut at the cuttable portion in the event of opening or attempting to open the container RCP.

[0180] The system SYS further comprises a detection device DSD, which in this case is incorporated in the integrated circuit IC and is configured to detect a present or past cutting of the cuttable portion FL10 of the conducting wire FL1 .

[0181] like Fig.17 As shown in , the container RCP may be a housing comprising a body CRP closed by a cover CV which together with the body CRP creates a groove FNT.

[0182] It goes without saying that this is only an example and that the container RCP may take any shape suitable for the contents of the container. For example, the container may be a bottle of wine or a bottle of alcohol closed by a cork.

[0183] exist Fig.17 In the example shown in , the conductive wire FL1 surrounded by the insulating cover is coiled so as to extend alternately on the cover CV and the body CRP.

[0184] This coil-shaped portion FL10 forms a cuttable portion of the conductive wire.

[0185] More specifically, when the cover CV is opened, the wire FL1 will be cut at the cuttable portion FL10.

[0186] It goes without saying that Fig.17 The illustrations in are not to scale, and a person skilled in the art will know how to select an appropriate diameter for the wire FL1 to ensure that the wire FL1 is severed when the cover CV is opened.

[0187] For example, the integrated circuit IC is attached to a wall of the body CRP.

[0188] Then, once the assembly has been produced, the unit is covered with a cap CH, e.g. Fig.18 is shown in a very schematic manner.

[0189] Now more specifically refer to Fig.19 , Fig.19 An exemplary embodiment of a detection device DSD is shown.

[0190] In this case, the device DSD comprises a first capacitor C1 electrically isolated from the first substrate SB1 of the integrated circuit and having a first electrode BC11 connected to a first terminal TDI of the integrated circuit.

[0191] In this example embodiment, the second electrode BC12 of the first capacitor C1 is connected to the power supply voltage VCC1 via the first auxiliary capacitor CTUN1 and the first controllable switch SW1 .

[0192] The device DSD further comprises a first MOS transistor TR, a source region and a drain region of the first MOS transistor TR being electrically isolated from the first substrate SB1 and a gate region of the first MOS transistor TR being connected to the second terminal TDO of the integrated circuit.

[0193] Generally speaking, the first transistor TR is configured to be in an on-state when a zero voltage is applied to a gate region thereof, and to be in an off-state when a non-zero bias voltage is applied to a gate region thereof.

[0194] For example, in a non-limiting manner, the first transistor TR may be a reference Figure 1 and Figures 3 to 7 A PMOS transistor is described.

[0195] In this case, for example, the first PMOS transistor TR has a source connected to the ground GND, and Fig.21 As shown, the first PMOS transistor TR is configured to be turned off when there is a negative bias voltage Vg (eg, -2 volts) applied to its gate, and to be turned on when there is a zero voltage Vg applied to its gate.

[0196] Therefore, the first transistor TR is “normally on”.

[0197] To obtain this configuration, the threshold voltage of the first PMOS transistor TR is negative and is, for example, in the order of -600 mV to -700 mV.

[0198] The device DSD further comprises a second capacitor C2 which is electrically isolated from the first substrate SB1 of the integrated circuit.

[0199] The second capacitor C2 has a first electrode BC21 connected to the drain of the first transistor TR.

[0200] The second capacitor C2 has a second electrode BC22 which is connected to the supply voltage VCC2 via a second auxiliary capacitor CTUN2 and a second controllable switch SW2.

[0201] The detection device DSD further comprises a measuring circuit MES configured to measure the voltage of the first electrode BC21 .

[0202] As will be seen in more detail below, a voltage at the first electrode being below the threshold value TH indicates a present or past cutting of the cuttable portion FL10 of the conducting wire FL1.

[0203] In this regard, in this embodiment, the integrated circuit IC includes a comparison circuit CMP configured to compare the voltage of the first electrode output by the measurement circuit MES with the threshold value TH and output a signal SRS indicating a comparison result.

[0204] The signal SRS may be a signal that has a high state when the measured voltage is lower than the threshold TH and has a low state when the measured voltage is higher than the threshold TH.

[0205] It goes without saying that the reverse is also possible.

[0206] exist Fig. 20 An exemplary embodiment is schematically shown in , which results in a capacitor C1 / C2 electrically isolated from the first substrate SB1 .

[0207] exist Fig. 20 As can be seen in FIG. 1 , the first capacitor C1 and the second capacitor C2 are capacitors comprising two polysilicon electrodes P10 and P20 separated by a dielectric 8 comprising a stack 80 of, for example, silicon oxide-silicon nitride-silicon oxide type.

[0208] These capacitors are located on an isolation trench 100 (for example, a shallow trench type isolation trench) which is made in the first substrate SB1.

[0209] Before starting with a detailed description of the operation of the system SYS, it should be noted that, as described above, the PMOS transistor TRP (such as the one described in reference to FIG. Figure 1 and Figures 3 to 7 The transistors described) are not the only possible transistors that can be used.

[0210] More specifically, any transistor whose source and drain regions are electrically isolated from the first substrate and which is configured to be in an on-state when there is a zero voltage applied to its gate and to be in an off-state when there is a non-zero bias applied to its gate region is suitable.

[0211] For example, this may be a transistor TRP100 (such as Fig. 22 The case of the transistor shown in FIG.

[0212] The transistor TRP100 is also a double polysilicon PMOS transistor, whose first polysilicon region P100 is located on the shallow trench type isolation trench 15, and whose second polysilicon region P200 is located on the first polysilicon region P100 via the gate oxide layer 9.

[0213] However, with Figure 1The transistor TRP in FIG. 100 is different. For example, the gate region of the transistor TRP100 is located in the second polysilicon region, and the source region and the drain region thereof are located in the first polysilicon region.

[0214] Compared with such transistor TRP100, transistor TRP (such as reference Figure 1 and Figures 3 to 7 The transistor described) is more advantageous because the transistor TRP has less leakage between the source region and the drain region because the source region and the drain region are arranged in the second polysilicon region, whose substrate region is made of intrinsic polysilicon or is lightly doped.

[0215] In this case, i.e. the substrate is a silicon-on-insulator (SOI) substrate comprising a carrier substrate positioned below a buried isolation layer referred to by those skilled in the art as BOX (buried oxide layer), which itself is positioned below a semiconductor film, in which and on which MOS transistors may also be arranged. This will therefore be electrically isolated from the carrier substrate of the integrated circuit via the BOX layer.

[0216] It goes without saying that, although it is usually easier to provide a PMOS transistor as the transistor TR, the use of an NMOS transistor is not excluded.

[0217] Now more specifically refer to Fig.23 To describe the operation of system SYS.

[0218] In step STP220 , the first capacitor C1 is charged.

[0219] The charging is performed by closing the switch SW1 to connect the first auxiliary capacitor CTUN1 to the power supply voltage VCC1.

[0220] One role of the first auxiliary capacitor CTUN1 is to allow charges to be injected into the first capacitor C1 through the Fowler-Nordheim effect or through a hot electron injection phenomenon.

[0221] The thickness of the dielectric layer of the first auxiliary capacitor CTUN1 (eg, 65 angstroms to 95 angstroms) is advantageously smaller than the thickness of the dielectric layer of the first capacitor C1 to allow programming of the capacitive structure without using too high a voltage.

[0222] The dielectric layer of the first capacitor C1 (which is thick because it uses a silicon oxide-silicon nitride-silicon oxide (ONO) stack) obtains a capacitor structure that is well isolated from the first substrate SB1. This thickness (e.g., 150 angstroms to 200 angstroms) obtains a very long charge retention capability, typically about 20 years, and prevents leakage risks on the first auxiliary capacitor CTUN1.

[0223] The first capacitor C1 , once charged, therefore has at its first electrode BC11 a voltage which is, for example, negative and equal to −2 Volts.

[0224] In step STP221 , the second capacitor C2 is charged by connecting the second auxiliary capacitor CTUN2 to the power supply voltage VCC2 via the closed first switch SW2 .

[0225] The function of the second auxiliary capacitor CTUN2 is similar to that of the first capacitor CTUN1 .

[0226] Once charged, the voltage VC2 of the first electrode BC21 of the second capacitor C2 will be a positive voltage equal to 2 Volts, for example.

[0227] In step STP222 , the voltage VC2 is measured by the measuring circuit MES.

[0228] In this respect, the measurement circuit MES may be, for example, a MOS transistor having its gate connected to the electrode BC21 , its source connected to ground and its drain connected to a current source to allow current-to-voltage conversion of the drain current of the transistor.

[0229] Therefore, the node BC21 is not connected to the first substrate SB1, and in order to prevent gate leakage as much as possible, a high-voltage MOS transistor having a gate oxide layer of, for example, about 200 angstroms is preferably used.

[0230] If the cuttable portion FL10 of the conducting wire FL1 is not cut, the transistor TR is turned off because its gate voltage is equal to -2 Volts.

[0231] Therefore, the second capacitor remains charged and, if for example a threshold TH equal to 1 Volt is chosen, the comparison performed in step STP223 indicates that the voltage VC2 is higher than the threshold TH, which means that the cut-off portion FL10 is not cut off.

[0232] However, if the portion FL10 of the conducting wire is cut, the gate voltage of the transistor TR is zero, which turns this transistor TR on, connecting the electrode BC21 to the ground GND.

[0233] This causes the second capacitor C2 to discharge, thereby causing the voltage VC2 to drop.

[0234] The voltage VC2 is then below the threshold TH, which indicates a switching-off of the switchable portion FL10 .

[0235] It should be noted that the voltage VC2 being below the threshold TH also indicates a past cut-out of the cut-out portion FL10 after which the cut-out portion was repaired, for example by a welding point.

[0236] More specifically, once the wire is cut, the gate voltage of the transistor becomes zero, and the transistor is turned on, thereby causing the second capacitor C2 to discharge and causing the voltage VC2 to be lower than the threshold TH.

[0237] Furthermore, even if the wire is repaired, capacitor C2 remains discharged.

[0238] like Fig.24 As schematically shown in FIG. 1 , the state of the cuttable portion of the conductor can also be monitored at regular or irregular time intervals.

[0239] More specifically, once capacitors C1 and C2 have been charged, a first measurement of voltage VC2 may be performed at time T0 in step STP230. Then, in step STP231, voltage VC2 is compared with a threshold value.

[0240] If the voltage is lower than the threshold value, this means that the cuttable portion is cut off or has been cut off before.

[0241] If the voltage VC2 is higher than the threshold value, this means that the cut-off portion FL10 is never cut off.

[0242] Furthermore, steps STP230 and STP231 may then be repeated at interval measurement times Ti (indicated by the increment of index i in step STP232 ).

[0243] Furthermore, a measured voltage below the threshold TH at the measuring time Ti therefore indicates that the cuttable portion of the conducting wire is cut at or before the measuring time.

[0244] like Fig.25 As shown, the use of a passive transponder in combination with a reader is particularly advantageous for detecting a current or past cut of the line FL1.

[0245] In this regard, Fig.25 In the embodiment, the system SYS further comprises a contactless passive transponder TG, such as a tag.

[0246] For example, the passive transponder TG is configured to communicate with a reader RD (eg, a cellular mobile phone having a contactless reader function) via an antenna ANT using a carrier signal having a frequency of 13.56 MHz.

[0247] In this case, the contactless passive transponder TG is a transponder capable of communicating according to a contactless communication protocol using, for example, near field communication (NFC) technology.

[0248] Such a transponder may also be an RFID transponder using the NFC technology.

[0249] The transponder TG comprises an integrated circuit IC which may be, for example, an integrated circuit of the ST25 series sold by STMicroelectronics.

[0250] In addition to the above-mentioned two terminals TDI and TDO, the integrated circuit also includes two antenna terminals AC0 and AC1 which are respectively connected to the two terminals of the antenna ANT.

[0251] The circuit IC further comprises a processing circuit MT, for example comprising an energy recovery circuit, a microprocessor and / or wired logic and a memory.

[0252] The processing circuit is configured to output a power supply voltage to the entire integrated circuit from the magnetic field received from the reader, and process the information received from the reader, and inversely modulate the carrier signal to transmit the information to the reader.

[0253] More specifically, if Fig.26 As shown in , the processing circuit MT is configured to: in response to a first command CMD1 from the reader (step STP260), command (step STP262) to charge the first capacitor C1; in response to a second command CMD2 from the reader (step STP261), command (step STP263) to charge the second capacitor C2; in response to an activation command CMDA from the reader (step STP264), activate (step STP265) the measurement circuit; and in response to a read command from the reader (step STP266), pass (step STP267) the comparison result SRS to the reader.

Claims

1. A detection system, comprising: Closed container; An integrated circuit having a first substrate, and a first terminal and a second terminal; an electrically conductive wire connecting the first terminal and the second terminal and having a severable portion arranged to be severed in the event of opening or attempting to open the closed container, and a detection device configured to detect severance of the severable portion; The detection device includes the following items within the integrated circuit: a first capacitor electrically isolated from the first substrate of the integrated circuit and connected to the first terminal; a first MOS transistor having a source region and a drain region electrically isolated from the first substrate, and a gate region connected to the second terminal, wherein the first MOS transistor is configured to be in an on-state in response to a zero voltage being applied to the gate region, and to be in an off-state in response to a non-zero voltage being applied to the gate region; a second capacitor electrically isolated from the first substrate of the integrated circuit and having a first electrode connected to the drain region of the first MOS transistor; as well as A measurement circuit is configured to measure a voltage at the first electrode, wherein the voltage at the first electrode indicates a present or past cutting of the cuttable portion if the voltage is below a threshold value.

2. The system of claim 1 , wherein the first MOS transistor comprises: a first polysilicon region electrically isolated from the first substrate and including the gate region; A second polysilicon region is electrically isolated from the first polysilicon region and the first substrate, wherein the second polysilicon region includes the source region, the substrate region and the drain region of the first MOS transistor, wherein the first polysilicon region is located between the region of the first substrate and the second polysilicon region.

3. The system of claim 2, wherein the substrate region for the second polysilicon region of the first MOS transistor is less heavily doped than the first polysilicon region.

4. The system of claim 2, wherein the substrate region for the second polysilicon region of the first MOS transistor comprises one of: intrinsic polysilicon, or a substrate having a thickness of less than 10 17 Atom / cm 3 The dopant concentration of the doped polysilicon.

5. The system of claim 2, wherein the first polysilicon region has a thickness greater than 10 19 Atom / cm 3 of dopant concentration.

6. The system of claim 2, wherein the first MOS transistor is a PMOS transistor.

7. The system of claim 6 , wherein the source region of the first MOS transistor is connected to ground, and wherein the first MOS transistor has a threshold voltage such that the first MOS transistor is in an on state in response to zero voltage being applied to the gate region, and is in an off state in response to a negative bias voltage being applied to the gate region.

8. The system of claim 1, wherein each of the first capacitor and the second capacitor comprises two polysilicon electrodes separated by a dielectric and located on an isolation region of the integrated circuit.

9. The system of claim 1, further comprising: a contactless passive transponder configured to communicate with a reader via an antenna using a carrier signal, said contactless passive transponder comprising said integrated circuit having two antenna terminals connected to said antenna; wherein the integrated circuit further comprises a comparison circuit configured to compare the voltage of the first electrode with the threshold value; as well as a processing circuit configured to: in response to a first command from the reader, command charging of a first capacitor; in response to a second command from the reader, command charging of a second capacitor; and in response to an activation command from the reader, activate the measurement circuit; and delivering a result of the comparison in response to a read command from the reader.

10. A method for detecting whether a severable portion of a conductive wire connecting a first terminal and a second terminal of an integrated circuit has been severed in the event of opening or attempting to open a closed container, comprising: charging a first capacitor electrically isolated from a first substrate of the integrated circuit and connected to the first terminal; charging a second capacitor, the second capacitor being electrically isolated from the first substrate of the integrated circuit and having a first electrode connected to a drain region of the first MOS transistor; as well as The voltage of the first electrode of the second capacitor is measured at least once using the first MOS transistor, and the measured voltage is compared with a threshold value.

11. The method of claim 10, wherein charging the first capacitor and the second capacitor comprises charging only once, wherein using comprises measuring the voltage of the first electrode multiple times at interval measurement times, comparing the multiple measurements with the threshold, wherein a measured voltage at one interval measurement time among the interval measurement times being lower than the threshold indicates that the cut-off portion has been cut off at the one interval measurement time among the interval measurement times, or has been cut off before the one interval measurement time among the interval measurement times.

12. A detection system comprising: Integrated circuits, including: a first substrate; and a first MOS transistor, the first MOS transistor having a first polysilicon region and a second polysilicon region, the first polysilicon region being electrically isolated from the first substrate and including a gate region, the second polysilicon region being electrically isolated from the first polysilicon region and the first substrate, the second polysilicon region including a source region, a substrate region, and a drain region of the first MOS transistor, wherein the first polysilicon region is located between a region of the first substrate and the second polysilicon region; wherein the first MOS transistor is a PMOS transistor; wherein the source region of the first MOS transistor is connected to ground, and wherein the first MOS transistor has a threshold voltage such that the first MOS transistor is in an on state in response to zero voltage being applied to the gate region, and is in an off state in response to a negative bias voltage being applied to the gate region.

13. The system of claim 12, wherein the substrate region of the second polysilicon region of the first MOS transistor is less heavily doped than the first polysilicon region.

14. The system of claim 12, wherein the substrate region of the second polysilicon region of the first MOS transistor comprises one of: intrinsic polysilicon, or a dopant concentration less than 10 17 Atom / cm 3 of doped polysilicon.

15. The system of claim 12, wherein the first polysilicon region has a thickness greater than 10 19 Atom / cm 3 of dopant concentration.

16. The system of claim 12, wherein the integrated circuit further comprises an isolation trench in the first substrate, and wherein the first polysilicon region is located over the isolation trench.

17. The system of claim 16, wherein the first polysilicon region extends beyond the second polysilicon region in a source-drain direction of the first MOS transistor, and wherein the second polysilicon region is located on the first polysilicon region via a first dielectric region.

18. The system of claim 16, wherein: The first polysilicon region extends beyond the second polysilicon region in a direction perpendicular to a source-drain direction of the first MOS transistor; as well as In the source-drain direction of the first MOS transistor, the size of the second polysilicon region is larger than that of the first polysilicon region, and the second polysilicon region is located on the first polysilicon region and the isolation trench via a second dielectric region.

19. The system of claim 16, wherein: The first polysilicon region extends beyond the second polysilicon region in a direction perpendicular to a source-drain direction of the first MOS transistor; as well as In the source-drain direction of the first MOS transistor, the size of the second polysilicon region is larger than that of the first polysilicon region, and the second polysilicon region is located on the first polysilicon region via a third dielectric region and also on the isolation trench.

20. A detection system comprising: Integrated circuits, including: a first substrate; and a first MOS transistor, the first MOS transistor having a first polysilicon region and a second polysilicon region, the first polysilicon region being electrically isolated from the first substrate and including a gate region, the second polysilicon region being electrically isolated from the first polysilicon region and the first substrate, the second polysilicon region including a source region, a substrate region, and a drain region of the first MOS transistor, wherein the first polysilicon region is located between a region of the first substrate and the second polysilicon region; The integrated circuit further comprises: an isolation trench located in the first substrate; and A dielectric layer surrounding the first polysilicon region, wherein the first polysilicon region is surrounded by the dielectric layer of the first polysilicon region, the dielectric layer extends through the isolation trench into the first substrate, and wherein the substrate region of the first MOS transistor is at least partially located on an end of the first polysilicon region surrounded by the dielectric layer, and the source region and the drain region are located on the isolation trench.

21. The system of claim 20, wherein the integrated circuit further comprises at least one nonvolatile memory cell of a type having a select transistor with a gate buried in the first substrate, and wherein the first polysilicon region has a shape similar to a shape of the gate of the select transistor.

22. A detection system comprising: Integrated circuits, including: a first substrate; and a first MOS transistor, the first MOS transistor having a first polysilicon region and a second polysilicon region, the first polysilicon region being electrically isolated from the first substrate and including a gate region, the second polysilicon region being electrically isolated from the first polysilicon region and the first substrate, the second polysilicon region including a source region, a substrate region, and a drain region of the first MOS transistor, wherein the first polysilicon region is located between a region of the first substrate and the second polysilicon region; The integrated circuit further comprises: a dielectric layer disposed between the first polysilicon region and the first substrate; and A second MOS transistor, wherein the second MOS transistor includes a source region, a drain region and a substrate region in the first substrate, the substrate region is between the source region and the drain region and is covered by the dielectric layer, and the first polysilicon region includes a gate region shared by the first MOS transistor and the second MOS transistor.

23. The system of claim 22, wherein the second MOS transistor is one of an NMOS transistor or a PMOS transistor.

24. A method for manufacturing a MOS transistor in an integrated circuit having a first substrate, comprising: forming a first polysilicon region, wherein the first polysilicon region is electrically isolated from the first substrate; forming a second polysilicon region, the second polysilicon region being electrically isolated from the first polysilicon region and the first substrate, wherein the first polysilicon region is located between a region of the first substrate and the second polysilicon region; forming a source region and a drain region in the second polysilicon region, wherein the source region and the drain region are located on either side of the substrate region of the MOS transistor; forming at least one source contact region on the source region, and forming at least one drain contact region on the drain region; forming at least one gate contact region on the first polysilicon region; as well as An isolation trench is formed in the first substrate, and the first polysilicon region is formed over the isolation trench.

25. The method of claim 24, further comprising in-situ doping of the first polysilicon region.

26. The method of claim 25, wherein the substrate region is undoped.

27. The method of claim 25, wherein the substrate region is doped to a lower degree than the in-situ doping of the first polysilicon region.

28. The method of claim 24, further comprising producing a non-volatile memory select transistor gate buried in the first substrate simultaneously with forming the first polysilicon region.

29. The method of claim 24, further comprising forming a floating gate of a dual gate state transistor of a nonvolatile memory cell simultaneously with forming the first polysilicon region.

30. The method of claim 24, further comprising forming a gate of a low voltage transistor of a memory circuit device simultaneously with forming the second polysilicon region.

31. The method of claim 24, wherein the MOS transistor is one of a PMOS transistor or an NMOS transistor.

Images