Random number generator, electronic device and operation method

Abstract

A random number generator, an electronic device and an operation method. The random number generator includes an entropy source circuit, an entropy extraction circuit and an output circuit. The entropy source circuit includes a charging circuit, which includes a first memristor unit and is configured to charge a first node through the first memristor unit and change the potential of the first node. The entropy extraction circuit is coupled to the entropy source circuit and configured to generate a periodically changing signal with multiple states, extract the time value when the first node is charged to the target potential, and obtain a random value based on the current state of the periodically changing signal corresponding to the time value. The output circuit is coupled to the entropy extraction circuit and configured to receive and output the random value. The random number generator is optimized in circuit design, avoiding the use of complex external circuits, and effectively reducing circuit area and power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a random number generator, an electronic device, and an operating method. Background Art

[0002] Physically Unclonable Function (PUF) and True Random Number Generator (TRNG) are important security modules in hardware security chips. The entropy source circuit is the core circuit in the security module. For the entropy source circuit used in PUF, its function is to generate static true random numbers, so that each time the PUF is used, the PUF can output a fixed true random number; for the entropy source circuit used in TRNG, its function is to generate dynamic true random numbers, so that each time the TRNG is used, the TRNG can output an unpredictable true random number. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a random number generator, comprising: an entropy source circuit, comprising a charging circuit, wherein the charging circuit comprises a first memristor unit and is configured to charge a first node through the first memristor unit and change the potential of the first node; an entropy extraction circuit, coupled to the entropy source circuit, configured to generate a periodic variation signal having multiple states, extract a time value when the first node is charged to a target potential, and obtain a random value based on a current state of the periodic variation signal corresponding to the time value; and an output circuit, coupled to the entropy extraction circuit, configured to receive and output the random value.

[0004] For example, in the random number generator provided in at least one embodiment of the present disclosure, the entropy extraction circuit includes a comparison unit and a time extraction unit, the comparison unit is coupled to the first node, and is configured to compare the potential of the first node with the target potential to obtain a voltage comparison result; the time extraction unit is configured to generate the periodic change signal, extract the time value of the first node being charged to the target potential according to the voltage comparison result, and extract the current state of the periodic change signal corresponding to the time value as the random value.

[0005] For example, in the random number generator provided by at least one embodiment of the present disclosure, the time extraction unit includes an oscillator unit, which is configured to oscillate to generate the periodic changing signal, is controlled to stop oscillating based on the voltage comparison result, and extracts the current state of the periodic changing signal when the oscillation stops as the random value.

[0006] For example, in the random number generator provided in at least one embodiment of the present disclosure, the time extraction unit also includes a logic control subunit, which is configured to receive a first control signal and perform a logic operation with the voltage comparison result to control whether the oscillation subunit stops oscillating.

[0007] For example, in the random number generator provided in at least one embodiment of the present disclosure, the oscillator unit is a ring oscillator, and the ring oscillator is configured to periodically output a first state having a first voltage and a second state having a second voltage, wherein the first voltage is higher than the second voltage.

[0008] For example, in the random number generator provided in at least one embodiment of the present disclosure, the output circuit includes a trigger unit, which is configured to receive the random value and an edge trigger signal, and output the random value in response to the edge trigger signal.

[0009] For example, in the random number generator provided by at least one embodiment of the present disclosure, the trigger unit is coupled to the comparison unit, configured to receive the voltage comparison result to obtain the edge trigger signal, and to output the random value in response to the edge trigger signal.

[0010] For example, in the random number generator provided in at least one embodiment of the present disclosure, the output circuit further includes a buffer subunit, and the buffer subunit is configured to receive the voltage comparison result and perform delay processing on the voltage comparison result to generate the edge trigger signal.

[0011] For example, in the random number generator provided in at least one embodiment of the present disclosure, the trigger unit is an edge D trigger, the input end of the edge D trigger is configured to receive the random value, the clock end of the edge D trigger is configured to receive the edge trigger signal, and the output end of the edge D trigger is configured to respond to the edge trigger signal to output the random value.

[0012] For example, in the random number generator provided in at least one embodiment of the present disclosure, the first memristor unit includes a first memristor and a first switching element, wherein the first switching element is controlled by a second control signal, the first memristor is electrically connected between a first voltage terminal and the first switching element, and the first switching element is coupled to the first node, or the first switching element is electrically connected between the first voltage terminal and the first memristor, and the first memristor is coupled to the first node.

[0013] For example, in the random number generator provided in at least one embodiment of the present disclosure, the charging circuit also includes a second memristor unit, which is coupled to the first node so that the first node can be charged through the second memristor unit and the potential of the first node can be changed.

[0014] For example, in the random number generator provided in at least one embodiment of the present disclosure, the second memristor unit includes a second memristor and a second switching element, the second switching element is controlled by a third control signal, the second memristor is electrically connected between a second voltage terminal and the second switching element, the second switching element is coupled to the first node, or the second switching element is electrically connected between the second voltage terminal and the second memristor, and the second memristor is coupled to the first node.

[0015] For example, in the random number generator provided by at least one embodiment of the present disclosure, the first memristor and the second memristor include resistive random access memories.

[0016] For example, in the random number generator provided in at least one embodiment of the present disclosure, the output circuit also includes a gating unit, wherein the control end of the gating unit is configured to receive a fourth control signal, the first input end of the gating unit is configured to receive the random value, and the second input end of the gating unit is configured to receive the voltage comparison result.

[0017] For example, in the random number generator provided in at least one embodiment of the present disclosure, the output end of the gating unit is configured such that the gating unit outputs the random value when the first voltage end and the second voltage end both receive the same voltage according to the control of the fourth control signal, or outputs the voltage comparison result when the first voltage end and the second voltage end respectively receive different voltages so that the target divided voltage of the first node is equal to the target potential.

[0018] For example, in the random number generator provided by at least one embodiment of the present disclosure, the charging circuit further includes a capacitor, and one electrode of the capacitor is coupled to the first node.

[0019] At least one embodiment of the present disclosure further provides an electronic device, which includes the random number generator provided by any embodiment of the present disclosure.

[0020] For example, the electronic device provided by at least one embodiment of the present disclosure also includes: a control module, configured to receive a main control signal and control the operation of the random number generator according to the main control signal; a voltage providing module, coupled to the entropy source circuit and configured to provide at least one voltage signal to the entropy source circuit.

[0021] At least one embodiment of the present disclosure also provides an operating method for the random number generator provided by at least one embodiment of the present disclosure, comprising: charging the first node through the entropy source circuit and causing the entropy extraction circuit to generate the periodic change signal having the multiple states to perform a timing operation; causing the entropy extraction circuit to extract the time value when the first node is charged to the target potential; causing the entropy extraction circuit to obtain the random value based on the current state of the periodic change signal corresponding to the time value; and receiving and outputting the random value through the output circuit.

[0022] At least one embodiment of the present disclosure also provides an operating method for the random number generator provided by at least one embodiment of the present disclosure, comprising: charging the first node through the first memristor unit and the second memristor unit to change the potential of the first node; causing the entropy extraction circuit to generate the periodic change signal having the multiple states to perform a timing operation; causing the entropy extraction circuit to extract the time value when the first node is charged to the target potential; causing the entropy extraction circuit to obtain the random value based on the current state of the periodic change signal corresponding to the time value; and receiving and outputting the random value through the output circuit.

[0023] At least one embodiment of the present disclosure further provides an operation method for the random number generator provided by at least one embodiment of the present disclosure, comprising: receiving the fourth control signal by the gating unit; in response to receiving the same voltage signal at the first voltage terminal and the second voltage terminal, charging the first node through the first memristor unit and the second memristor unit to change the potential of the first node, causing the entropy extraction circuit to generate the periodic change signal with the multiple states to perform a timing operation, causing the entropy extraction circuit to extract the time value when the first node is charged to the target potential, causing the entropy extraction circuit to obtain the random value based on the current state of the periodic change signal corresponding to the time value, receiving and outputting the random value through the output circuit, causing the gating unit to output the random value according to the control of the fourth control signal; or in response to receiving the different voltages at the first voltage terminal and at the second voltage terminal respectively, charging the first node through the first memristor unit and the second memristor unit to change the potential of the first node, causing the entropy extraction circuit to generate the voltage comparison result when the first node is charged to the target potential, causing the gating unit to output the voltage comparison result according to the control of the fourth control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0025] Figure 1 A schematic block diagram of a random number generator provided for at least one embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of a random number generator provided for at least one embodiment of the present disclosure;

[0027] Figure 3 A schematic diagram of a ring oscillator provided by at least one embodiment of the present disclosure;

[0028] Figure 4 A schematic diagram of another random number generator provided for at least one embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of another random number generator provided for at least one embodiment of the present disclosure;

[0030] Figure 6 A schematic diagram of another random number generator provided for at least one embodiment of the present disclosure;

[0031] Figure 7 A schematic diagram of another random number generator provided for at least one embodiment of the present disclosure;

[0032] Figure 8 for Figure 7 A schematic diagram of the random number generator of the embodiment shown working in TRNG mode;

[0033] Fig. 9 for Figure 7 A schematic diagram of the random number generator of the illustrated embodiment working in PUF mode;

[0034] Fig.10 A schematic diagram of an electronic device provided for some embodiments of the present disclosure;

[0035] Fig.11 A flowchart of a work flow of an electronic device when a TRNG mode and a PUF mode of a random number generator are reusable according to some embodiments of the present disclosure;

[0036] Fig.12 A flowchart of a method for operating a random number generator provided in some embodiments of the present disclosure;

[0037] Fig.13 A flowchart of another method for operating a random number generator provided for some embodiments of the present disclosure; and

[0038] Fig.14 A flowchart of another method for operating a random number generator is provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0041] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0042] TRNG can generate random numbers by extracting randomness from complementary metal oxide semiconductor (CMOS) circuits or new devices such as resistive random-access memory (RRAM). The random movement of ions in RRAM generates randomness, also known as "read noise". For example, a method for generating true random numbers based on TRNG of RRAM read noise includes: reading the resistance value of RRAM twice in a row, recorded as r1 and r2 respectively; comparing the size of r1 and r2, if r1 is greater than r2, then output 1; if r1 is less than r2, then output 0; if r1 is equal to r2, then the output remains unchanged. To realize this design, high-precision analog-to-digital converters and digital comparators are required in the circuit, but this design increases the circuit area of ​​TRNG and increases the design complexity.

[0043] In addition, the inventors have noticed that in the field of hardware security, compared with the entropy source circuit design dedicated to PUF or TRNG, the entropy source circuit design that can be reused by PUF and TRNG can generate dynamic and static true random numbers at the same time with a smaller circuit area. However, the entropy source circuit design that can be reused by PUF and TRNG usually uses external circuits with complex structures, so it costs a lot in terms of circuit area and power consumption.

[0044] At least one embodiment of the present disclosure provides a random number generator, including an entropy source circuit, an entropy extraction circuit and an output circuit. The entropy source circuit includes a charging circuit, which includes a first memristor unit and is configured to charge a first node through the first memristor unit and change the potential of the first node. The entropy extraction circuit is coupled to the entropy source circuit and configured to generate a periodically changing signal with multiple states, extract the time value when the first node is charged to the target potential, and obtain a random value based on the current state of the periodically changing signal corresponding to the time value. The output circuit is coupled to the entropy extraction circuit and configured to receive and output the random value.

[0045] At least one embodiment of the present disclosure also provides an electronic device corresponding to the above-mentioned random number generator.

[0046] At least one embodiment of the present disclosure also provides an operating method corresponding to the above-mentioned random number generator.

[0047] The random number generator, electronic device, and operating method provided in at least one embodiment of the present disclosure are optimized in circuit design, and can directly obtain random values ​​through the randomness of the extracted memristor and the periodic change signals of multiple states generated, thereby avoiding the use of complex external circuits and effectively reducing circuit area and power consumption overhead; and in at least one embodiment of implementing a PUF and TRNG reusable entropy source circuit, the design of the PUF and TRNG reusable entropy source circuit is simplified, reducing the circuit area and reducing power consumption.

[0048] Some embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Figure 1 A schematic block diagram of a random number generator provided for at least one embodiment of the present disclosure.

[0050] For example, Figure 1 As shown, the random number generator 100 includes an entropy source circuit 110, an entropy extraction circuit 120 and an output circuit 130. The entropy source circuit 110 includes a charging circuit 1101, which includes a first memristor unit (not shown in the figure) and is configured to charge the first node N1 through the first memristor unit and change the potential of the first node N1. The entropy extraction circuit 120 is coupled to the entropy source circuit 110, configured to generate a periodic change signal with multiple states, extract the time value when the first node N1 is charged to the target potential, and obtain a random value based on the current state of the periodic change signal corresponding to the time value. The output circuit 130 is coupled to the entropy extraction circuit 120, configured to receive and output a random value.

[0051] Figure 2 A schematic diagram of a random number generator provided for at least one embodiment of the present disclosure.

[0052] For example, Figure 2 Shown Figure 1 The circuit structure of a specific implementation example of the random number generator 100 is shown in FIG. Figure 2 As shown, the entropy source circuit 110 includes a charging circuit, and the charging circuit includes a first memristor unit 111. The entropy source circuit 110 charges the first node 112 through the first memristor unit 111, and thereby changes the potential of the first node 112, which is recorded as V c .

[0053] For example, Figure 2 As shown, in an embodiment of the present disclosure, the first memristor unit 111 includes a first memristor R1 and a first switch element T1. The first switch element T1 is controlled by a second control signal. The control terminal WLT of the first switch element T1 is configured to receive the second control signal. In some examples, for example, Figure 2 As shown, the first memristor R1 is electrically connected between the first voltage terminal BLT and the first switch element T1, and the first switch element T1 is coupled to the first node 112; in other examples, the first switch element T1 is electrically connected between the first voltage terminal BLT and the first memristor R1, and the first memristor R1 is coupled to the first node 112.

[0054] In at least one embodiment of the present disclosure, the first memristor R1 may be, for example, RRAM or the like. For example, in the case where the first memristor R1 is RRAM, the first memristor R1 is a stacked structure prepared by a semiconductor process, including two opposing electrode layers (for example, metal electrodes) and a storage material layer sandwiched between the two electrodes, and the storage material layer may further be a stacked structure, and the stacked structure includes a combination of multiple material layers. For example, the stacked structure obtained by the combination of the material layers may be TiN / HfAlO x / TaO x / TiN or TiN / HfO2 / TaO x / TiN or TiN / HfO2 / TiN or TiN / HfZrO x / TaO x / TiN or TiN / HfAlZrO x / TaO x / TiN or TiN / SiO2 / TiN, etc., and the embodiments of the present disclosure are not limited to this.

[0055] It should be noted that the first switch element T1 may be any appropriate switch element, such as a metal-oxide semiconductor field effect transistor (MOSFET), a thin film transistor or other three-terminal switch element, and the embodiments of the present disclosure are not limited thereto.

[0056] For example, Figure 2 As shown, in at least one embodiment, the charging circuit further includes at least one capacitor 113, one electrode of the capacitor 113 is coupled to the first node 112 (for example, the two are formed integrally), and the other electrode of the capacitor 113 is for example grounded. The entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 to change the potential V of the first node 112 c (For example, the potential relative to another electrode). It should be noted that the capacitor 113 may also be other electronic components that can charge the first node 112, and the embodiments of the present disclosure are not limited to this.

[0057] For example, Figure 2 As shown, the entropy extraction circuit 120 is coupled to the entropy source circuit 110, and includes a comparison unit 121 and a time extraction unit 122. The comparison unit 121 is coupled to the first node 112 and is configured to convert the potential V c and the target potential V f Compare to get the voltage comparison result, recorded as V t .

[0058] For example, the comparison unit 121 may be implemented as a comparator (eg, a dynamic low voltage comparator, etc.), or may be other electronic components capable of implementing a voltage comparison function, which is not limited in the embodiments of the present disclosure.

[0059] For example, in some examples, such as Figure 2 As shown, the negative (-) input terminal of the comparison unit 121 is electrically connected to the first node 112 and is configured to receive the potential V of the first node 112. c The positive (+) input terminal of the comparison unit 121 is configured to receive the target potential V f At this time, when V c <V f When the voltage comparison result V t is high level; when V c >V f When the voltage comparison result V t is low level.

[0060] For example, in some other examples, the positive (+) input terminal of the comparison unit 121 is electrically connected to the first node 112 and is configured to receive the potential V c The negative (-) input terminal of the comparison unit 121 is configured to receive the target potential V f At this time, when V c <V f When the voltage comparison result V t is low level; when V c >V f When the voltage comparison result V t is high level.

[0061] For example, the time extraction unit 122 is configured to generate a periodically changing signal having multiple states; the time extraction unit 122 generates a periodically changing signal according to the voltage comparison result V t Extract the potential V of the first node 112 c Charged to the target potential V f (i.e., V c =V f ), recorded as t0, and the current state of the periodically changing signal corresponding to the time value t0 is extracted as the random value.

[0062] For example, the time extraction unit 122 includes an oscillator unit 1221. The oscillator unit 1221 is configured to oscillate to generate a periodically changing signal based on the voltage comparison result V t The oscillation is controlled to stop, and the current state of the periodically changing signal when the oscillation stops is extracted as a random value.

[0063] For example, Figure 2As shown, in at least one embodiment, the oscillator unit 1221 can be implemented as a ring oscillator. The enable terminal EN of the oscillator unit 1221 is configured to receive the voltage comparison result V t The output terminal OUT of the oscillator unit 1221 is configured to periodically output a first state having a first voltage and a second state having a second voltage. For example, the first state may be a high level and the second state may be a low level; or the first state may be a low level and the second state may be a high level; the embodiments of the present disclosure are not limited to this.

[0064] For example, the oscillator unit 1221 can be a ring oscillator, or it can be other electronic components that can generate periodically changing signals and can achieve oscillation control (for example, a sinusoidal signal / triangular wave model / square wave model generator circuit, etc.), and the embodiments of the present disclosure are not limited to this.

[0065] Figure 3 A schematic diagram of a ring oscillator provided in accordance with at least one embodiment of the present disclosure.

[0066] For example, Figure 3 As shown, I1 and I2 are inverter circuits, and I3, I4, and I5 are inverter circuits with enable terminals. When the voltage comparison result V t When it is high, I3 and I4 are enabled, and I5 is disabled. At this time, I1, I3 and I4 form a three-order ring oscillator circuit. The output terminal OUT of the ring oscillator outputs a periodic changing signal that continuously flips between the first state and the second state. When the voltage comparison result V t When it is low level (i.e. at time t0), I5 is enabled, I3 and I4 are disabled, at this time I1 and I5 form a latch circuit, and the periodic change signal outputted by the output terminal OUT of the ring oscillator is randomly locked in the first state or the second state, that is, the output terminal OUT outputs a stable first state or second state signal. The specific design of the third-order ring oscillator circuit and the latch circuit can refer to the description in the art, and will not be repeated here.

[0067] For example, Figure 2 As shown, the output circuit 130 is coupled to the entropy extraction circuit 120 and includes a trigger unit 131. The trigger unit 131 is configured to receive a random value and an edge trigger signal, and output a random value in response to the edge trigger signal.

[0068] For example, in some examples, such as Figure 2 As shown, the trigger unit 131 is coupled to the comparison unit 121 and is configured to receive the voltage comparison result V tTo obtain an edge trigger signal, and to output a random value in response to the edge trigger signal; in other examples, the edge trigger signal received by the trigger unit may be a high-speed clock signal input by an external circuit.

[0069] In e.g. Figure 2 In the illustrated embodiment, an edge trigger signal generated internally by a random number generator is used instead of a high-speed clock signal input by an external circuit, thereby reducing the overall circuit area and power consumption overhead, and also broadening the application scope of the random number generator (for example, it can be applied to chips that cannot provide high-speed clock signals, etc.).

[0070] For example, in Figure 2 In at least one example of the embodiment of the present invention, the trigger unit 131 can be implemented as an edge D trigger. The input terminal D of the edge D trigger is configured to receive a random value, the clock terminal CLK of the edge D trigger is configured to receive an edge trigger signal, and the output terminal Q of the edge D trigger is configured to output a random value in response to the edge trigger signal.

[0071] For example, the trigger unit 131 may be an edge D trigger, or may be other electronic components that can output a random value in response to an edge trigger signal, and the embodiments of the present disclosure are not limited thereto.

[0072] Figure 4 A schematic diagram of another random number generator provided for at least one embodiment of the present disclosure.

[0073] For example, Figure 4 As shown, Figure 2 In contrast, the time extraction unit 122 of the random number generator 100 further includes a logic control subunit 1222. The logic control subunit 1222 is configured to receive the first control signal at its control terminal ROEN and compare it with the voltage comparison result V t A logical operation is performed to control whether the oscillator unit 1221 stops oscillating. Figure 4 In the example shown, the logical operation is an "AND" operation; in other examples, the logical operation may also be other logical operations that can achieve the above-mentioned control effect, and the embodiments of the present disclosure are not limited to this. Figure 4 The other structures and functions of the random number generator 100 shown are similar to those of Figure 2 The above are basically the same and will not be repeated here.

[0074] Figure 5 A schematic diagram of yet another random number generator provided for at least one embodiment of the present disclosure.

[0075] For example, Figure 5 As shown, Figure 4In contrast, the output circuit 130 of the random number generator 100 further includes a buffer subunit 132. The buffer subunit 132 is configured to receive the voltage comparison result V t , the voltage comparison result V t Delay processing is performed to generate an edge trigger signal. The buffer subunit 132 may be implemented as a buffer circuit, for example, and the embodiments of the present disclosure may not limit the specific implementation of the buffer subunit. Figure 5 The other structures and functions of the random number generator 100 shown are similar to those of Figure 4 The above are basically the same and will not be repeated here.

[0076] For example, Figure 5 As shown, the input end of the buffer subunit 132 is electrically connected to the output end of the comparison unit 121, and the output end of the buffer subunit 132 is electrically connected to the clock end CLK of the edge D flip-flop. Figure 5 In the embodiment shown, when the potential V of the first node 112 c Charged to the target potential V f (i.e., V c =V f ), the voltage comparison result V t From high level to low level, at this time, the voltage comparison result V output by the comparison unit 121 is t is an edge trigger signal (here a falling edge signal). The buffer subunit 132 receives the edge trigger signal and outputs the delayed edge trigger signal to the clock terminal CLK of the edge D flip-flop. The edge D flip-flop responds to the delayed edge trigger signal to output the random value received at the input terminal D from the output terminal Q.

[0077] It should be noted that when the clock terminal CLK of the edge D flip-flop receives the edge trigger signal, the signal input to the input terminal D must have remained stable for at least a period of time (i.e., the signal setup time, denoted as Tsetup) before this, to ensure that the edge D flip-flop can correctly sample the input signal. If the delay time of the buffer subunit 132 is denoted as Tpd, the design requirement of the buffer subunit 132 is to ensure that Tpd>Tsetup. Therefore, the buffer subunit 132 ensures that the edge trigger signal output by the comparison unit 121 first acts on the oscillator subunit 1221, so that the output of the oscillator subunit 1221 is first locked at a high or low level; at the same time, it also ensures that the edge trigger signal acts on the edge D flip-flop after a period of delay, ensuring that the edge D flip-flop samples the output signal of the stable oscillator subunit 1221, thereby ensuring that the edge D flip-flop can correctly sample the input signal.

[0078] Figure 6 A schematic diagram of yet another random number generator provided for at least one embodiment of the present disclosure.

[0079] For example, Figure 6 As shown, Figure 5 In contrast, the entropy source circuit 110 of the random number generator 100 further includes a second memristor unit 114. The second memristor unit 114 is coupled to the first node 112 so that the first node 112 can be charged by the second memristor unit 114 and the potential of the first node 112 can be changed. Figure 6 The other structures and functions of the random number generator 100 shown are similar to those of Figure 5 The above are basically the same and will not be repeated here.

[0080] For example, Figure 6 As shown, the second memristor unit 114 includes a second memristor R2 and a second switch element T2, and the second switch element T2 is controlled by a third control signal. The control terminal WLB of the second switch element T2 is configured to receive the third control signal. The second memristor R2 is electrically connected between the second voltage terminal BLB and the second switch element T2. In some examples, for example, Figure 6 As shown, the second switch element T2 is coupled to the first node 112 ; in some other examples, the second switch element T2 is electrically connected between the second voltage terminal BLB and the second memristor R2 , and the second memristor R2 is coupled to the first node 112 .

[0081] In at least one embodiment of the present disclosure, the second memristor R2 may be, for example, RRAM, etc. The case where the second memristor R2 is RRAM is the same as the case where the first memristor R1 is RRAM, and will not be described in detail herein.

[0082] It should be noted that the second switch element T2 may be any suitable switch element, such as a metal-oxide semiconductor field effect transistor (MOSFET), a thin film transistor or other three-terminal switch element, which is not limited in the embodiments of the present disclosure.

[0083] In e.g. Figure 6 In the illustrated embodiment, compared with the case where the entropy source circuit 110 includes only 1T1R, the use of 2T2R fully utilizes the randomness of the resistance change of the memristor (such as RRAM read noise), and has better and easier to extract physical randomness than CMOS circuits, thereby effectively improving the randomness of the circuit output.

[0084] Furthermore, it should be noted that it is not limited to Figure 5 Examples of embodiments, such as those based on Figure 2 , Figure 4 and Figure 5 The embodiment shown can also be similar to Figure 6 The second memristor unit is added to the case, thereby more effectively improving the randomness of the circuit output compared to the case of only including 1T1R.

[0085] Figure 7 A schematic diagram of yet another random number generator provided for at least one embodiment of the present disclosure.

[0086] For example, Figure 7 As shown, Figure 6 In contrast, the output circuit 130 of the random number generator 100 further includes a gating unit 133. The control terminal CTR of the gating unit 133 is configured to receive a fourth control signal, the first input terminal of the gating unit 133 is configured to receive a random value, and the second input terminal of the gating unit 133 is configured to receive a voltage comparison result V t The output terminal of the gating unit 133 is configured as follows: the gating unit 133 outputs a random value when the first voltage terminal BLT and the second voltage terminal BLB both receive the same voltage according to the control of the fourth control signal, and the random number generator 100 operates in the TRNG mode; or, when the first voltage terminal BLT and the second voltage terminal BLB receive different voltages respectively to make the target voltage at the first node 112 equal to the target potential V f When the output voltage comparison result V t , at this time, the random number generator 100 works in PUF mode. Figure 7 The other structures and functions of the random number generator 100 shown are similar to those of Figure 6 For example, the gating unit 133 may include a multi-way selection circuit, such as a two-choice selection circuit.

[0087] It should be noted that the selection unit 133 selects the first input terminal when the fourth control signal is at a low level, and selects the second input terminal when the fourth control signal is at a high level; or, selects the second input terminal when the fourth control signal is at a low level, and selects the first input terminal when the fourth control signal is at a high level.

[0088] For example, the random number generator 100 provided in the above embodiment realizes the reuse of the two working modes of TRNG and PUF. Compared with the random number generator dedicated to TRNG or PUF, in the embodiment of the present disclosure, the random number generator reusable by TRNG and PUF can realize the same function in a smaller circuit area, thereby saving the circuit area and power consumption.

[0089] Figure 8 for Figure 7 The illustrated embodiment is a schematic diagram of a random number generator operating in a TRNG mode.

[0090] For example, Figure 8 As shown, the first voltage terminal BLT and the second voltage terminal BLB both receive the same voltage (eg Figure 8As shown, BLT and BLB both receive 200mV); the control terminal WLT of the first switch element T1 and the control terminal WLB of the second switch element T2 receive the second control signal and the third control signal (for example Figure 8 As shown, the second control signal and the third control signal are both 1) to turn on the first switch element T1 and the second switch element T2; the control terminal CTR of the gating unit 133 receives the fourth control signal (for example Figure 8 As shown, the fourth control signal is 0) to select the first input terminal; the logic control subunit 1222 receives the first control signal (for example Figure 8 As shown, the first control signal is 1). At this time, the random number generator 100 operates in the TRNG mode.

[0091] For example, Figure 8 As shown, the entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 and the second memristor unit 114 to change the potential V of the first node 112. c The negative (-) input terminal of the comparison unit 121 receives the potential V of the first node 112. c The positive (+) input terminal of the comparison unit 121 is configured to receive the target potential V f (For example, V f =100mV).

[0092] For example, Figure 8 As shown, in the TRNG mode, in the first stage, the potential V of the first node 112 c Less than the target potential V f (i.e., V c <V f ), the voltage comparison result V output by the comparison unit 121 t is high level, the enable terminal EN of the oscillator unit 1221 receives the high level signal, the oscillator unit 1221 is enabled, and the output terminal OUT outputs a periodic change signal that continuously flips between the first state and the second state; at the end of the first stage (that is, when V c =V f When the voltage comparison result is V t From high level to low level, at this time, the voltage comparison result V output by the comparison unit 121 is t is an edge trigger signal (here, a falling edge signal), and the buffer subunit 132 receives the edge trigger signal; in the second stage, the potential V of the first node 112 c is charged to a potential greater than the target potential V f (i.e., V c >V f ), the voltage comparison result V output by the comparison unit 121 tis low level (i.e. at time t0), the enable terminal EN of the oscillator unit 1221 receives the low level signal, the oscillator unit 1221 is disabled, the oscillator unit 1221 stops oscillating, and the periodically changing signal output by the output terminal OUT is randomly locked in the first state or the second state, that is, the output terminal OUT outputs a stable first state or second state signal; after the delay time Tpd of the buffer subunit 132, the buffer subunit 132 outputs the delayed edge trigger signal to the clock terminal CLK of the trigger unit 131, the input terminal D of the trigger unit 131 samples the stable first state or second state signal as a random value, and responds to the edge trigger signal to output the random value at the output terminal Q to the first input terminal of the gating unit 133, and the output terminal of the gating unit 133 outputs the random value.

[0093] It should be noted that the potential V of the first node 112 c The relationship with the charging time t is shown in formula (1):

[0094] V c =V s (1-e (-t / RC) ) Formula (1)

[0095] Among them, V s is the equivalent power supply voltage (corresponding to the voltage received by BLT and BLB), R is the equivalent resistance (corresponding to the resistance of the first memristor R1 and the second memristor R2), and C is the capacitance of the capacitor 113. It can be seen from formula (1) that in the TRNG mode, the potential V c Charged to the target potential V f The time value t0 is affected by the randomness of the resistance change of the first memristor R1 and the second memristor R2 (such as RRAM read noise), thereby affecting the final stable state of the oscillator unit 1221. Therefore, the random value output by the random number generator 100 has strong randomness.

[0096] Fig. 9 for Figure 7 The illustrated embodiment is a schematic diagram of a random number generator operating in a PUF mode.

[0097] For example, Fig. 9 As shown, the first voltage terminal BLT and the second voltage terminal BLB receive different voltages (eg Fig. 9 As shown, BLT receives 200mV, and BLB receives 0V); the control terminal WLT of the first switch element T1 and the control terminal WLB of the second switch element T2 receive the second control signal and the third control signal respectively (for example Fig. 9As shown, both the second control signal and the third control signal are 1) to turn on the first switching element T1 and the second switching element T2; the control terminal CTR of the selection unit 133 receives a fourth control signal (for example Fig. 9 As shown, the fourth control signal is 1) to select the second input terminal; the logic control sub-unit 1222 receives a first control signal at its control terminal ROEN (for example Fig. 9 As shown, the first control signal is 0). At this time, the random number generator 100 operates in the PUF mode.

[0098] For example, as Fig. 9 shown, the entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 and the second memristor unit 114 to change the potential V of the first node 112 c . The negative (-) input terminal of the comparison unit 121 receives the potential V of the first node 112 c , and the positive (+) input terminal of the comparison unit 121 is configured to receive a target potential V f (for example, V f = 100 mV).

[0099] For example, as Fig. 9 shown, in the PUF mode, the resistance values of the first memristor R1 and the second memristor R2 are denoted as rr1 and rr2 respectively. At this time, the random number generator 100 outputs a random result by comparing the magnitudes of rr1 and rr2. Given that BLT receives 200 mV and BLB receives 0 V, due to the voltage division effect of the resistors, when rr1 < rr2, the potential V of the first node 112 c is greater than the target potential V f (that is, V c > 100 mV), then the voltage comparison result V output by the comparison unit 121 t is low level, and the selection unit 133 outputs low level; when rr1 > rr2, the potential V of the first node 112 c is less than the target potential V f (that is, V c < 100 mV), then the voltage comparison result V output by the comparison unit 121 t is high level, and the selection unit 133 outputs high level.

[0100] In the embodiment shown in, for example Fig. 9 , the entropy source circuit 110 generates a random result through the differential resistance values of two memristors, reducing the impact of data retention and read disturb of RRAM on storage reliability, having better data holding ability and robustness than 1T1R, and thus can significantly reduce the bit error rate of the circuit.

[0101] Fig.10 A schematic diagram of an electronic device provided for some embodiments of the present disclosure.

[0102] For example, Fig.10 As shown, the electronic device 1 includes a random number generator 100, a control module 200 and a voltage providing module 300 provided by at least one embodiment of the present disclosure. The control module 200 is configured to receive a main control signal WDCTR and control the operation of the random number generator 100 according to the main control signal WDCTR. The voltage providing module 300 is coupled to the entropy source circuit 110 in the random number generator 100, and is configured to provide at least one voltage signal to the entropy source circuit 110, for example, configured to receive the main control signal WDCTR and provide at least one voltage signal to the entropy source circuit 110 according to the main control signal WDCTR.

[0103] For example, Figure 7 For example, by setting the main control signal WDCTR to 0 or 1, the voltage providing module 300 provides different voltage signals to BLB; the control module 200 provides different first control signals to ROEN and different fourth control signals to CTR. Thus, by setting the main control signal WDCTR, the random number generator 100 can be controlled to work in TRNG mode or PUF mode.

[0104] For example, as shown in Table 1, when WDCTR=0, the voltage signal of the input BLB is 200mV, the first control signal of the input ROEN is 1, and the fourth control signal of the input CTR is 0. At this time, the random number generator 100 works in the TRNG mode; when WDCTR=1, the voltage signal of the input BLB is 0V, the first control signal of the input ROEN is 0, and the fourth control signal of the input CTR is 1. At this time, the random number generator 100 works in the PUF mode.

[0105] Table 1 Relationship between WDCTR and random number generator working mode

[0106]

[0107] For example, the voltage supply module 300 can be implemented by a digital circuit or an analog circuit; the control module 200 can be implemented by a digital circuit or an analog circuit, such as a CPU, a programmable logic controller (PLC), etc.; the embodiments of the present disclosure are not limited to this.

[0108] For example, in some embodiments, the electronic device 1 further includes an output module. The output module is configured to output the random value (or the voltage comparison result V c ) to obtain an intermediate number, and generate a random number based on the intermediate number. For example, the operation includes modulo 2 LOperation, the middle number is used as a random number, and the middle number is 2 L For example, in some examples, L is 1, that is, the operation includes a modulo 2 operation, and the intermediate number is a binary number. For example, the output module responds to the random value (or the voltage comparison result V c ) performs a modulo 2 operation to obtain an intermediate number 0 or 1, which is used as a random number in binary form. For example, in other examples, L is 2, that is, the operation includes a modulo 4 operation, and the intermediate number is a 4-base number. For example, the output module performs a modulo 2 operation on the random value (or the voltage comparison result V c ) performs a modulo 4 operation to obtain an intermediate number 0, 1, 2 or 3, which is used as a random number in 4-base form.

[0109] For example, in the above embodiment, in the TRNG mode, the random number generator 100 extracts the current state of the periodically changing signal corresponding to the time value t0 as the random value, so the random value has dynamic randomness, and the output module digitizes the random value to obtain a dynamic random number; in the PUF mode, the voltage comparison result V output by the random number generator 100 is c It is the random result output by comparing the size of rr1 and rr2, so the voltage comparison result V c With static randomness, the output module compares the voltage result V c Digitize to get static random numbers.

[0110] Fig.11 A flowchart of an electronic device when the TRNG mode and PUF mode of a random number generator are reusable is provided for some embodiments of the present disclosure, for example, corresponding to Figure 7 to Figure 9 The embodiment shown.

[0111] For example, Fig.11 As shown, when WDCTR=0, the random number generator 100 works in TRNG mode and outputs a random value with dynamic randomness, the electronic device 1 extracts the dynamic randomness, and digitizes the random variable corresponding to the random value to generate a dynamic random number; when WDCTR=1, the random number generator 100 works in PUF mode and outputs a voltage comparison result V with static randomness. c , the electronic device 1 extracts the static randomness and compares the voltage result V c The corresponding random variables are digitized to generate static random numbers.

[0112] Fig.12 A flowchart of a method for operating a random number generator provided in some embodiments of the present disclosure, for example, corresponding to Figure 2 The embodiment shown.

[0113] For example, Fig.12As shown, in at least one embodiment of the present disclosure, the operation method of the random number generator 100 includes the following steps S110 to S140.

[0114] Step S110: charging the first node 112 through the entropy source circuit 110 and causing the entropy extraction circuit 120 to generate a periodically changing signal with multiple states to perform a timing operation;

[0115] Step S120: enabling the entropy extraction circuit 120 to extract the time value of the first node 112 being charged to the target potential;

[0116] Step S130: enabling the entropy extraction circuit 120 to obtain a random value based on the current state of the periodically changing signal corresponding to the time value;

[0117] Step S140 : receiving and outputting the random value through the output circuit 130 .

[0118] For example, Figure 2 As shown, the entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 to change the potential V of the first node 112. c In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112 to c and the target potential V f Compare to get the voltage comparison result V t The time extraction unit 122 generates a periodic change signal having multiple states, and according to the voltage comparison result V t Extract the potential V of the first node 112 c Charged to the target potential V f (i.e., V c =V f ), extracts the current state of the periodically changing signal corresponding to the time value t0 as the random value. In the output circuit 130, the trigger unit 131 receives the random value and the edge trigger signal, and responds to the edge trigger signal to output the random value.

[0119] In e.g. Figure 2 In the embodiment, an edge trigger signal generated inside the random number generator is used instead of a high-speed clock signal input from an external circuit, thereby reducing the overall circuit area and power consumption overhead, and also broadening the application scope of the random number generator (for example, it can be applied to chips that cannot provide high-speed clock signals, etc.).

[0120] Fig.13 A flowchart of another method for operating a random number generator provided in some embodiments of the present disclosure, for example, corresponding to Figure 6 The embodiment shown.

[0121] For example, Fig.13 As shown, in some embodiments, when the entropy source circuit 110 of the random number generator 100 includes both the first memristor unit 111 and the second memristor unit 114, for example Figure 6 or Figure 7 In the illustrated embodiment, the operation method of the random number generator 100 includes the following steps S210 to S250.

[0122] Step S210: charging the first node 112 through the first memristor unit 111 and the second memristor unit 114 to change the potential of the first node 112;

[0123] Step S220: enabling the entropy extraction circuit 120 to generate a periodically changing signal having multiple states to perform a timing operation;

[0124] Step S230: enabling the entropy extraction circuit 120 to extract the time value of the first node 112 being charged to the target potential;

[0125] Step S240: enabling the entropy extraction circuit 120 to obtain a random value based on the current state of the periodically changing signal corresponding to the time value;

[0126] Step S250 : receiving and outputting the random value through the output circuit 130 .

[0127] For example, Figure 6 As shown, the entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 and the second memristor unit 114 to change the potential V of the first node 112. c In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112 to c and the target potential V f Compare to get the voltage comparison result V t The time extraction unit 122 generates a periodic change signal having multiple states, and according to the voltage comparison result V t Extract the potential V of the first node 112 c Charged to the target potential V f (i.e., V c =V f ), extracts the current state of the periodically changing signal corresponding to the time value t0 as the random value. In the output circuit 130, the trigger unit 131 receives the random value and the edge trigger signal, and responds to the edge trigger signal to output the random value.

[0128] In e.g. Figure 6In the illustrated embodiment, compared with the case where the entropy source circuit 110 includes only 1T1R, the use of 2T2R fully utilizes the randomness of the resistance change of the memristor (such as RRAM read noise), and has better and easier to extract physical randomness than CMOS circuits, thereby effectively improving the randomness of the circuit output.

[0129] Fig.14 A flowchart of another method for operating a random number generator provided in some embodiments of the present disclosure, for example, corresponding to Figure 7 The embodiment shown.

[0130] For example, Fig.14 As shown, in other embodiments, when the entropy source circuit 110 of the random number generator 100 includes both the first memristor unit 111 and the second memristor unit 114, and the output circuit 130 includes the gating unit 133 so as to realize the multiplexing of the TRNG and PUF working modes, for example Figure 7 In the illustrated embodiment, the operation method of the random number generator 100 includes the following steps S300, S311-S315 (TRNG working mode) and S321-S323 (PUF working mode).

[0131] Step S300: the gating unit 133 receives a fourth control signal;

[0132] In response to the first voltage terminal and the second voltage terminal receiving the same voltage signal:

[0133] Step S311: charging the first node 112 through the first memristor unit 111 and the second memristor unit 114 to change the potential of the first node 112;

[0134] Step S312: enabling the entropy extraction circuit 120 to generate a periodically changing signal having multiple states to perform a timing operation;

[0135] Step S313: enabling the entropy extraction circuit 120 to extract the time value of the first node 112 being charged to the target potential;

[0136] Step S314: enabling the entropy extraction circuit 120 to obtain a random value based on the current state of the periodically changing signal corresponding to the time value;

[0137] Step S315: receiving and outputting the random value through the output circuit 130;

[0138] Step S316: enabling the gating unit 133 to output a random value according to the control of the fourth control signal;

[0139] Alternatively, in response to receiving different voltages at the first voltage terminal and at the second voltage terminal respectively:

[0140] Step S321: charging the first node 112 through the first memristor unit 111 and the second memristor unit 114 to change the potential of the first node 112;

[0141] Step S322: enabling the entropy extraction circuit 120 to generate a voltage comparison result when the first node 112 is charged to a target potential;

[0142] Step S323: enabling the gating unit 133 to output the voltage comparison result according to the control of the fourth control signal.

[0143] For example, Figure 7 The random number generator 100 shown in FIG. Figure 8 As shown, the control terminal CTR of the gating unit 133 receives the fourth control signal to select the first input terminal, and the first voltage terminal BLT and the second voltage terminal BLB both receive the same voltage. At this time, the random number generator 100 operates in the TRNG mode. The entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 and the second memristor unit 114 to change the potential V of the first node 112. c In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112 to c and the target potential V f Compare to get the voltage comparison result V t The time extraction unit 122 generates a periodic change signal having multiple states, and according to the voltage comparison result V t Extract the potential V of the first node 112 c Charged to the target potential V f (i.e., V c =V f ), extract the current state of the periodically changing signal corresponding to the time value t0 as the random value. In the output circuit 130, the trigger unit 131 receives the random value and the edge trigger signal, and responds to the edge trigger signal to output the random value; the output end of the gating unit 133 outputs the random value.

[0144] For example, Fig. 9 As shown, the control terminal CTR of the gating unit 133 receives the fourth control signal to select the second input terminal, and the first voltage terminal BLT and the second voltage terminal BLB receive different voltages respectively. At this time, the random number generator 100 works in the PUF mode. The entropy source circuit 110 charges the capacitor 113 through the first memristor unit 111 and the second memristor unit 114 to change the potential V of the first node 112. c In the entropy extraction circuit 120, the comparison unit 121 compares the potential V of the first node 112 to c and the target potential V fCompare to get the voltage comparison result V t In the output circuit 130, the output terminal of the selection unit 133 outputs the voltage comparison result V t .

[0145] In e.g. Figure 7 to Figure 9 In the illustrated embodiment, the random number generator 100 realizes the reuse of the two working modes of TRNG and PUF. Compared with the random number generator dedicated to TRNG or PUF, the random number generator reusable by TRNG and PUF in these embodiments can realize the same function in a smaller circuit area, thereby saving circuit area and power consumption.

[0146] There are a few points to note about this disclosure:

[0147] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0148] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0149] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A random number generator, comprising: An entropy source circuit, comprising a charging circuit, wherein the charging circuit comprises a first memristor unit and is configured to charge a first node through the first memristor unit and change the potential of the first node; an entropy extraction circuit, coupled to the entropy source circuit, configured to generate a periodically changing signal having a plurality of states, extract a time value for charging the first node to a target potential, and obtain a random value based on a current state of the periodically changing signal corresponding to the time value; and An output circuit is coupled to the entropy extraction circuit and configured to receive and output the random value, wherein the output circuit includes a trigger unit, the trigger unit is configured to receive the random value and an edge trigger signal, and respond to the edge trigger signal to output the random value.

2. The random number generator according to claim 1, wherein: The entropy extraction circuit includes a comparison unit and a time extraction unit. The comparison unit is coupled to the first node and configured to compare the potential of the first node with the target potential to obtain a voltage comparison result; The time extraction unit is configured to generate the periodic change signal, extract the time value for the first node to be charged to the target potential according to the voltage comparison result, and extract the current state of the periodic change signal corresponding to the time value as the random value.

3. The random number generator according to claim 2, wherein: The time extraction unit includes an oscillator unit, The oscillator unit is configured to oscillate to generate the periodically changing signal, be controlled to stop oscillating based on the voltage comparison result, and extract the current state of the periodically changing signal when the oscillation is stopped as the random value.

4. The random number generator according to claim 3, wherein: The time extraction unit also includes a logic control subunit, The logic control subunit is configured to receive a first control signal and perform a logic operation with the voltage comparison result to control whether the oscillation subunit stops oscillating.

5. The random number generator according to claim 3, wherein: The oscillator unit is a ring oscillator. The ring oscillator is configured to periodically output a first state having a first voltage and a second state having a second voltage, the first voltage being higher than the second voltage.

6. The random number generator according to claim 2, wherein: The trigger unit is coupled to the comparison unit, and is configured to receive the voltage comparison result to obtain the edge trigger signal, and output the random value in response to the edge trigger signal.

7. The random number generator according to claim 6, wherein: The output circuit further includes a buffer subunit, which is configured to receive the voltage comparison result and perform delay processing on the voltage comparison result to generate the edge trigger signal.

8. The random number generator according to claim 2, wherein: The trigger unit is an edge D trigger, The input terminal of the edge D flip-flop is configured to receive the random value, the clock terminal of the edge D flip-flop is configured to receive the edge trigger signal, and the output terminal of the edge D flip-flop is configured to output the random value in response to the edge trigger signal.

9. The random number generator according to claim 1, wherein: The first memristor unit includes a first memristor and a first switch element, wherein the first switch element is controlled by a second control signal, The first memristor is electrically connected between a first voltage terminal and the first switch element, and the first switch element is coupled to the first node; or the first switch element is electrically connected between the first voltage terminal and the first memristor, and the first memristor is coupled to the first node.

10. The random number generator according to claim 9, wherein: The charging circuit further includes a second memristor unit, The second memristor unit is coupled to the first node so that the first node can be charged through the second memristor unit and the potential of the first node can be changed.

11. The random number generator according to claim 10, wherein: The second memristor unit includes a second memristor and a second switch element, and the second switch element is controlled by a third control signal. The second memristor is electrically connected between a second voltage terminal and the second switch element, and the second switch element is coupled to the first node; or the second switch element is electrically connected between the second voltage terminal and the second memristor, and the second memristor is coupled to the first node.

12. The random number generator according to claim 11, wherein: The first memristor and the second memristor include resistive memory.

13. The random number generator according to claim 12, wherein: The output circuit further includes a gating unit, wherein: The control end of the gating unit is configured to receive a fourth control signal, the first input end of the gating unit is configured to receive the random value, and the second input end of the gating unit is configured to receive the voltage comparison result.

14. The random number generator according to claim 13, wherein: The output terminal of the gating unit is configured such that the gating unit outputs the random value when the first voltage terminal and the second voltage terminal both receive the same voltage according to the control of the fourth control signal, or, The first voltage terminal and the second voltage terminal receive different voltages respectively to output the voltage comparison result when the target divided voltage of the first node is equal to the target potential.

15. The random number generator according to any one of claims 1 to 14, wherein: The charging circuit further includes a capacitor, one electrode of which is coupled to the first node.

16. An electronic device comprising the random number generator according to any one of claims 1 to 15.

17. The electronic device according to claim 16, further comprising: a control module configured to receive a main control signal and control the operation of the random number generator according to the main control signal; The voltage providing module is coupled to the entropy source circuit and is configured to provide at least one voltage signal to the entropy source circuit.

18. A method for operating a random number generator according to any one of claims 1 to 15, comprising: charging the first node through the entropy source circuit and causing the entropy extraction circuit to generate the periodically changing signal having the plurality of states to perform a timing operation; causing the entropy extraction circuit to extract the time value for which the first node is charged to the target potential; causing the entropy extraction circuit to obtain the random value based on the current state of the periodically varying signal corresponding to the time value; The random value is received and outputted through the output circuit.

19. A method for operating a random number generator according to claim 10, comprising: charging the first node through the first memristor unit and the second memristor unit to change the potential of the first node; causing the entropy extraction circuit to generate the periodically changing signal having the plurality of states to perform a timing operation; causing the entropy extraction circuit to extract the time value for which the first node is charged to the target potential; causing the entropy extraction circuit to obtain the random value based on the current state of the periodically varying signal corresponding to the time value; The random value is received and outputted through the output circuit.

20. A method for operating a random number generator according to claim 14, comprising: The gating unit receives the fourth control signal; In response to the first voltage terminal and the second voltage terminal receiving the same voltage signal, the first node is charged through the first memristor unit and the second memristor unit to change the potential of the first node, so that the entropy extraction circuit generates the periodic change signal having the multiple states to perform a timing operation, so that the entropy extraction circuit extracts the time value when the first node is charged to the target potential, so that the entropy extraction circuit obtains the random value based on the current state of the periodic change signal corresponding to the time value, receives and outputs the random value through the output circuit, and the gating unit outputs the random value according to the control of the fourth control signal; or, In response to receiving the different voltages at the first voltage terminal and at the second voltage terminal respectively, the first node is charged through the first memristor unit and the second memristor unit to change the potential of the first node, so that the entropy extraction circuit generates the voltage comparison result when the first node is charged to the target potential, and the gating unit outputs the voltage comparison result according to the control of the fourth control signal.

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