A digitally controlled envelope tracking power supply modulator

Abstract

The present application belongs to the technical field of integrated circuits, and particularly relates to a digital control envelope tracking power modulator. The envelope tracking power modulator comprises a digital control current source array, a switching amplifier, a digital-to-analog converter, and an off-chip power inductor. One end of the power inductor is connected to the output of the digital control current source array and the feedback input end of the switching amplifier, and the other end is connected to the output of the switching amplifier. The output of the digital-to-analog converter is connected to the reference voltage input end of the switching amplifier. The present application provides high-frequency current to the load through the digital control current source array, provides low-frequency current to the load through the switching amplifier, and controls the switching amplifier through the digital-to-analog converter. The present application removes the linear amplifier in the traditional hybrid architecture envelope tracking power modulator, and relies on the digital control current source array to generate the high-bandwidth envelope power at a very high speed to power the power amplifier, thereby improving the overall efficiency of the system.

Description

TECHNICAL FIELD

[0001] The present invention belongs to the field of integrated circuit technology, and particularly relates to a digitally controlled envelope tracking power supply modulator. BACKGROUND

[0002] The data transmission speed in modern wireless communication systems is getting higher and higher, and the signal modulation technology is getting more and more complex. A significant problem accompanying this is that the peak-to-average power ratio of the transmitted signal is getting larger and larger. The high peak-to-average power ratio of the signal puts a severe requirement on the efficiency of the power amplifier, whose role is to transmit the signal through the antenna. If a fixed voltage power supply is used to power the power amplifier, the efficiency of the power amplifier will decrease with the increase of the peak-to-average power ratio of the signal. The role of the envelope tracking power supply modulator is to dynamically adjust the power supply voltage of the power amplifier according to the change of the signal envelope, to reduce energy loss and improve efficiency.

[0003] The traditional envelope tracking power supply modulator includes a linear amplifier and a switching amplifier. The linear amplifier has a large bandwidth but low efficiency, and the switching amplifier has a low bandwidth but high efficiency. Therefore, it is necessary to take the advantages of each other, the switching amplifier provides the low frequency component of the envelope, and the linear amplifier is responsible for the high frequency component of the envelope, and the combination of the two makes the entire envelope tracking power supply modulator have high speed and high efficiency. The envelope tracking power supply modulator has been widely used in handheld mobile devices, especially in mobile phones.

[0004] When the bandwidth of the envelope is greater than 100MHz, it becomes very difficult to design a linear amplifier with large power and large bandwidth. First, from the power supply port of the power amplifier, the power amplifier can be regarded as a resistor in parallel with a capacitor, which forms the output load of the linear amplifier, a typical value is 4Ω and 600pF, which forms a pole of about 60MHz, and compensating for this in-band pole is a great challenge. Secondly, the high frequency envelope with large swing requires the linear amplifier to have a large swing rate, and the large power output requires the output power tube of the linear amplifier to have a large size, which makes the linear amplifier need to consume a large static current, which seriously reduces the efficiency of the linear amplifier and worsens the overall efficiency of the envelope tracking power supply modulator. Finally, each transistor that constitutes the linear amplifier is large in size, which causes the poles at each node inside the linear amplifier to introduce amplitude and phase deterioration in the band. In summary, the design of a linear amplifier with large bandwidth, large power and large swing rate is difficult, even impossible, and a circuit modification or replacement of the linear amplifier must be used. SUMMARY

[0005] The envelope tracking power supply modulator can quickly generate a high-bandwidth envelope power supply for power amplifier, and improve the overall efficiency of the system.

[0006] The envelope tracking power supply modulator is provided by the application, which is controlled by a digital control technology, and the input signal is a first digital signal, a second digital signal and a third digital signal.

[0007] The envelope tracking power supply modulator provided by the application comprises a digital control current source array, a switching amplifier, a digital-to-analog converter and an off-chip power inductor.

[0008] The first digital signal and the second digital signal control the digital control current source array.

[0009] The third digital signal controls the digital-to-analog converter.

[0010] The switching amplifier comprises a first input end and a second input end, and the first output end is the output of the digital control envelope tracking power supply modulator.

[0011] One end of the off-chip power inductor is connected to the output of the digital control current source array and the first input end, and the other end of the power inductor is connected to the output of the switching amplifier.

[0012] The output of the digital-to-analog converter is a first analog signal, and the first analog signal is a voltage signal and is sent to the second input end.

[0013] The digital control current source array comprises a gate, a first current source array and a second current source array.

[0014] The input of the gate is the first digital signal and the second digital signal, and the output is a fourth digital signal and a fifth digital signal; when the first digital signal is 1, the fourth digital signal is equal to the second digital signal, and the fifth digital signal is 0000000; when the first digital signal is 0, the fifth digital signal is equal to the second digital signal, and the fourth digital signal is 1111111.

[0015] Optionally, the first current source array comprises a 7-128 decoder and 127 first current units; the 7-128 decoder is a thermometer code, and the input signal is the fourth digital signal; each output controls one first current unit.

[0016] Optionally, the first current source array comprises: a 3-8 decoder, 127 first current units; the 3-8 decoder is thermometer coding, the input signal is the high 3 bits of the fourth digital signal, and each output controls 16 first current units; the low 4 bits of the fourth digital signal simultaneously controls 8, 4, 2, and 1 first current units from high to low, respectively.

[0017] The first current source array comprises: 127 first current units; 7 bits of the fourth digital signal simultaneously controls 64, 32, 16, 8, 4, 2, and 1 first current units from high to low, respectively.

[0018] Optionally, the second current source array comprises: a 7-128 decoder, 127 second current units; the 7-128 decoder is thermometer coding, the input signal is the fifth digital signal, and each output controls 1 second current unit.

[0019] Optionally, the second current source array comprises: a 3-8 decoder, 127 second current units; the 3-8 decoder is thermometer coding, the input signal is the high 3 bits of the fifth digital signal, and each output controls 16 second current units; the low 4 bits of the fifth digital signal simultaneously controls 8, 4, 2, and 1 second current units from high to low, respectively.

[0020] Optionally, the second current source array comprises: 127 second current units; 7 bits of the fifth digital signal simultaneously controls 64, 32, 16, 8, 4, 2, and 1 second current units from high to low, respectively.

[0021] Optionally, the first current unit comprises: a PMOS current mirror, a PMOS switch tube; the PMOS switch tube is connected in series with the output end of the PMOS current mirror; the gate of the PMOS switch tube is a first control end; the drain of the PMOS switch tube is connected to the first output end; when the first control end is high, the PMOS switch tube is turned off.

[0022] Optionally, the first current unit comprises: a PMOS power tube; the gate of the PMOS power tube is a first control end; the drain of the PMOS power tube is connected to the first output end; when the first control end is high, the PMOS power tube is turned off.

[0023] Optionally, the first current unit comprises: a PMOS current mirror, a PMOS switch tube; the PMOS switch tube is connected in series with the output end of the PMOS current mirror; the gate of the PMOS switch tube is a first control end; the drain of the PMOS switch tube is connected to the first output end; when the first control end is high, the PMOS switch tube is turned off.

[0024] Optionally, the second current unit comprises: an NMOS power tube; a gate of the NMOS power tube is the second control end; a drain of the NMOS power tube is connected to the first output end; when the second control end is low, the NMOS power tube is turned off.

[0025] In the application, the switch amplifier has three ports: a first input end, a second input end and a second output end; the switch amplifier is composed of six parts: a low-pass filter, a PID compensator, a sawtooth wave generator, a comparator, a two-phase non-overlapping and driving circuit and a power transistor; further, the first input end is connected to the input end of the low-pass filter, and the second input end is connected to the non-inverting input end of the PID compensator.

[0026] The low-pass filter is an RC filter, and the cutoff frequency is 5 MHz; the low-pass filter outputs a second analog signal to the inverting input end of the PID compensator.

[0027] The PID compensator outputs a third analog signal, and adjusts the loop bandwidth to 1 MHz.

[0028] The sawtooth wave generator outputs a fourth analog signal.

[0029] The fourth analog signal is a 10 MHz fixed frequency sawtooth wave.

[0030] The third analog signal is sent to the inverting input end of the comparator, and the fourth analog signal is sent to the non-inverting input end of the comparator.

[0031] The comparator compares the third analog signal and the fourth analog signal, and outputs a fifth analog signal.

[0032] The two-phase non-overlapping and driving circuit processes the fifth analog signal to generate a two-phase non-overlapping clock with driving capability to drive the power transistor.

[0033] The power transistor comprises a power tube made of PMOS and a power tube made of NMOS, and the drains of the two are connected together and connected to the second output end.

[0034] In the application, the digital-to-analog converter generates the first analog signal according to the third digital signal, and the first analog signal is sent to the second input end; the first analog signal should simulate the theoretical value of the second analog signal.

[0035] Optionally, the digital-to-analog converter is a current steering digital-to-analog converter.

[0036] In the present application, the user generates the first control signal, the second control signal and the third control signal according to the required current of the load; the first control signal and the second control signal control the digital control current source array after being processed by the gate, and provide the load with continuously changing high-frequency current; the third control signal controls the digital-to-analog converter to generate the first analog signal; the switching amplifier generates the low-frequency pulse signal at the second output end according to the first analog signal and the voltage of the first output end, and provides the load with low-frequency current after being filtered by the off-chip inductor; the high-frequency current is fast but low in efficiency, and the low-frequency current is slow but high in efficiency, and the combination of the two realizes high-speed and relatively high-efficiency power supply.

[0037] The envelope tracking power supply modulator provided by the present application removes the linear amplifier in the traditional hybrid architecture envelope tracking power supply modulator, and relies on the digital control current source array to generate the high-bandwidth envelope power supply at extremely high speed to power the power amplifier and improve the overall efficiency of the system. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 The figure is a system architecture block diagram provided by an embodiment of the present application.

[0039] Figure 2 The figure is a load current distribution schematic diagram provided by an embodiment of the present application.

[0040] Figure 3 The figure is a circuit schematic diagram provided by an embodiment of the present application.

[0041] Figure 4 The figure is a digital control current source array circuit schematic diagram provided by an embodiment of the present application.

[0042] Figure 5 The figure is a first current source array circuit schematic diagram provided by an embodiment of the present application.

[0043] Figure 6 The figure is another first current source array circuit schematic diagram provided by an embodiment of the present application.

[0044] Figure 7 The figure is another first current source array circuit schematic diagram provided by an embodiment of the present application.

[0045] Figure 8 The figure is a second current source array circuit schematic diagram provided by an embodiment of the present application.

[0046] Figure 9 The figure is another second current source array circuit schematic diagram provided by an embodiment of the present application.

[0047] Figure 10is another second current source array circuit schematic diagram provided by an embodiment of the present application.

[0048] Figure 11 is a first current unit circuit schematic diagram provided by an embodiment of the present application.

[0049] Figure 12 is another first current unit circuit schematic diagram provided by an embodiment of the present application.

[0050] Figure 13 is a second current unit circuit schematic diagram provided by an embodiment of the present application.

[0051] Figure 14 is another second current unit circuit schematic diagram provided by an embodiment of the present application.

[0052] Figure 15 is a switch amplifier circuit schematic diagram provided by an embodiment of the present application.

[0053] Figure 16 is a digital-to-analog converter circuit schematic diagram provided by an embodiment of the present application.

[0054] Figure 17 is a third current unit circuit schematic diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are a part of the embodiments of the present application, rather than all the embodiments of the present application. And the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments, all the other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0056] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. Unless otherwise expressly specified and limited, the terms "connected," "linked," etc., shall be interpreted broadly; for example, they can refer to electrical connection or mutual communication; they can refer to direct connection or indirect connection through an intermediate medium. It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are only intended to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0057] First, the design concept and related principles of this invention will be explained. (See [link to relevant documentation]). Figure 1 As shown, the overall envelope tracking power modulator mainly consists of two modules: a switching amplifier and a digitally controlled current source array, which supply current to the power amplifier. The output current of the switching amplifier is ISA, and the output current of the digitally controlled current source array is IPDAC. The current supplied to the power amplifier is IET, which is the sum of ISA and IPDAC. The current direction marked in the figure is the reference direction. After ISA flows into the power amplifier, it generates a changing envelope voltage waveform at the power amplifier's power supply terminal.

[0058] See the diagrams for ISA, IPDAC, and IET. Figure 2 The portion of the IPDAC signal greater than 0 can be considered as charging the power amplifier, causing the envelope voltage to rise; the portion less than 0 can be considered as discharging the power amplifier, causing the envelope voltage to fall. When designing a digitally controlled current source, the maximum swing of the IPDAC should be evaluated to ensure that the output current capability of the digitally controlled current source meets the swing requirements of the IPDAC. ISA is a periodic broken line and can be approximated as current I0. Figure 2 The expression for I0 is given, where R is the equivalent resistance of the power amplifier as seen from the power supply port, and V0 is the average value of the envelope voltage. IET can be considered as the IPDAC ripple current superimposed on the ISA current.

[0059] The overall circuit is divided into three modules, such as Figure 3The shown, respectively, are module 1 digital control current source array, module 2 switch amplifier, module 3 digital-to-analog converter. Module 1 is controlled by 1-bit first digital signal and 7-bit second digital signal, the second digital control signal can also be selected with other bits in order to ensure accuracy, it is recommended that the second digital signal is greater than or equal to 5 bits. The input end of the feedback voltage of module 2 is the first input end, the reference voltage input end is the second input end, the input signal is the first analog signal. The output end of the whole envelope tracking power supply modulator is the first output end, the first output end is connected to the first input end. Module 3 provides a reference voltage for module 2, and the output of module 3 is a first analog signal; Module 3 is controlled by 7-bit third digital signal, and the third digital control signal can also be selected with other bits in order to ensure accuracy, it is recommended that the third digital signal is greater than or equal to 7 bits.

[0060] In this embodiment, an optional embodiment of module 1 is shown in Figure 4 The whole module 1 is controlled by the first digital control signal and the second digital control signal. Module 11 is a gate composed of digital combinational logic circuit, which functions to output the fourth digital signal equal to the second digital signal and output the fifth digital signal as 0000000 when the first digital signal is 1; and output the fifth digital signal equal to the second digital signal and output the fourth digital signal as 1111111 when the first digital signal is 0. Module 12 is a first current source array, which functions to output current to the outside to make the output envelope voltage VET rise. Module 13 is a second current source array, which functions to absorb current to the inside to make the output envelope voltage VET fall.

[0061] In this embodiment, an optional embodiment of module 12 is shown in Figure 5 The whole module 12 is controlled by 7-bit fourth control signal. Module 14 is a 7-128 decoder, and the decoding mode is thermometer code. Module 15 is a first current unit, which outputs a set current to the outside when the input signal is 0. The fourth control signal is selected through module 14 to select a corresponding number of first current units to output current to the outside.

[0062] In this embodiment, an optional embodiment of module 12 is shown in Figure 6 The whole module 12 is controlled by 7-bit fourth control signal. Module 16 is a 3-8 decoder, and the decoding mode is thermometer code. Module 15 is a first current unit, which outputs a set current to the outside when the input signal is 0. The fourth control signal [6:4] is selected through module 16 to select a corresponding number of first current units to output current to the outside. The fourth control signal [3:0] directly selects a corresponding number of first current units to output current to the outside.

[0063] In this embodiment, an optional embodiment of module 12 is shown in Figure 7The whole module 12 is controlled by 7-bit fourth control signal. Module 15 is the first current unit, which outputs the set current when the input signal is 0. The fourth control signal [6:0] directly selects the corresponding number of first current units to output current.

[0064] In this embodiment, an alternative embodiment of module 13 is shown in Fig. 13. Figure 8 The whole module 13 is controlled by 7-bit fifth control signal. Module 14 is a 7-128 decoder, which decodes in thermometer code, and module 17 is the second current unit, which absorbs the set current when the input signal is 1. The fifth control signal [6:0] selects the corresponding number of second current units to absorb current after passing through module 14.

[0065] In this embodiment, an alternative embodiment of module 13 is shown in Fig. 13. Figure 9 The whole module 13 is controlled by 7-bit fifth control signal. Module 16 is a 3-8 decoder, which decodes in thermometer code, and module 17 is the second current unit, which absorbs the set current when the input signal is 1. The fifth control signal [6:4] selects the corresponding number of second current units to absorb current after passing through module 16. The fifth control signal [3:0] directly selects the corresponding number of second current units to absorb current.

[0066] In this embodiment, an alternative embodiment of module 13 is shown in Fig. 13. Figure 10 The whole module 13 is controlled by 7-bit fifth control signal. Module 17 is the second current unit, which absorbs the set current when the input signal is 1. The fifth control signal [6:0] directly selects the corresponding number of second current units to absorb current.

[0067] In this embodiment, an alternative embodiment of module 15 is shown in Fig. 15. Figure 11 Module 151 is a current mirror structure, and module 152 is a PMOS switch tube. The output current is determined by the ratio of M15A and M15B, and the first control end controls the conduction and turn-off of the switch tube. This structure outputs relatively accurate current, but when the output current is large, the output current becomes very inaccurate, and the current mirror fails. This circuit is only suitable for low-speed applications, and the stable speed of the output current limits the switching frequency.

[0068] In this embodiment, an alternative embodiment of module 15 is shown in Fig. 15. Figure 12The module 153 is a PMOS power transistor; the first control terminal controls the on and off of the output power transistor, and the output current is determined by the on resistance of the power transistor and the load. The final overall circuit obtained by this method needs to be calibrated before use to confirm the output current under different control words. In use, the control word is given according to the required output current.

[0069] In this embodiment, an alternative embodiment of the module 17 is shown in Figure 13 The module 171 is a current mirror structure, and the module 172 is an NMOS switch transistor; the output current is determined by the ratio of M17A and M17B, and the second control terminal controls the on and off of the switch transistor. This structure has a relatively accurate output current, but when the output current is large, the output current becomes very inaccurate, and the current mirror fails. This circuit is only suitable for low-speed applications, and the stable speed of the output current limits the switching frequency.

[0070] In this embodiment, an alternative embodiment of the module 17 is shown in Figure 14 The module 173 is an NMOS power transistor; the first control terminal controls the on and off of the output power transistor, and the output current is determined by the on resistance of the power transistor and the load. The final overall circuit obtained by this method needs to be calibrated before use to confirm the output current under different control words. In use, the control word is given according to the required output current.

[0071] In this embodiment, an alternative embodiment of the module 2 is shown in Figure 15 The signal at the first input terminal is first processed by the module 21, which is a low-pass filter. The filter can use a conventional RC filter with a cutoff frequency less than the switching frequency of the module 2, which is designed to be 5MHz. The processed signal is sent to the module 22, which is a PID compensator. The output signal of the compensator is the third analog signal, which is sent to the comparator together with the fourth analog signal generated by the module 23. The module 23 is a sawtooth wave generator, and the fourth analog signal is a sawtooth wave. The frequency of the fourth analog signal determines the switching frequency of the module 2, which is designed to be 10MHz. The output of the comparator is the fifth analog signal, which drives the module 25 after passing through the module 24. The module 24 is a two-phase non-overlapping logic and drive circuit, and the module 25 is a power transistor. The values of the capacitors and resistors in the module 22 can be calculated based on the inductance, the equivalent model of the power amplifier, and the required bandwidth. The calculation method uses the PID compensation method of the conventional voltage control mode Buck power supply. The designed bandwidth is 1MHz, and the phase margin is 60°.

[0072] In this embodiment, an alternative embodiment of the module 3 is shown in Figure 16The input signal is a 7-bit digital signal [6:0] and a 3-8 decoder is used in the figure. The 12 decoded digital signals control 12 third current cells in the current source array of module 31. The numbers in the third current cell array represent the ratio of the current that the current cell can provide to the current provided by the first current cell 1. Each third current cell has two outputs, one is the in-phase output and the other is the inverted output. The in-phase output is the final output of module 2. The output waveform of module 3 is the low-pass filtered pre-calculated output waveform.

[0073] In this embodiment, one of the optional implementations of the third current cell in module 31 is shown in Fig. 3B. Figure 17 The VG and NVG signals control the on and off of the switch, and they are complementary in logic, so they cannot be on or off at the same time. The output current is mirrored from a current source, and the mirror is M31A and M31B. By adjusting the size of M31B, different output currents can be obtained.

[0074] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, it is intended that the present application cover the modifications and changes as long as they come within the scope of the appended claims and their equivalents.

Claims

1. A digitally controlled envelope tracking power supply modulator characterized by, The digital control current source array, the switching amplifier, the digital-to-analog converter, and the off-chip power inductor are included. The switching amplifier comprises a first input end and a second input end. One end of the off-chip power inductor is connected to the output of the digital control current source array and the first input end, serving as a first output end, and the other end of the power inductor is connected to the output of the switching amplifier, serving as a second output end. The output of the digital-to-analog converter is a first analog signal, which is sent to the second input end. The first output end is the output of the digital control envelope tracking power supply modulator. The digital control current source array is controlled by the first digital signal and the second digital signal. The digital-to-analog converter is controlled by the third digital signal. The digital control current source array comprises a gate, a first current source array, and a second current source array. The gate is composed of a digital combination logic circuit, and the input of the gate is the first digital signal and the second digital signal, and the output of the gate is a fourth digital signal and a fifth digital signal. When the first digital signal is 1, the fourth digital signal is equal to the second digital signal, and the fifth digital signal is 0000000; when the first digital signal is 0, the fifth digital signal is equal to the second digital signal, and the fourth digital signal is 1111111. The first current source array is used to output current to the outside to make the output envelope voltage VET rise, and the second current source array is used to absorb current to the inside to make the output envelope voltage VET fall.

2. The digital control envelope tracking power supply modulator according to claim 1, wherein: The first current source array comprises a 7-128 decoder and 127 first current units; the 7-128 decoder is in thermometer code, and the input signal is the fourth digital signal; each output controls one first current unit; or The first current source array comprises a 3-8 decoder and 127 first current units; the 3-8 decoder is in thermometer code, and the input signal is the high 3 bits of the fourth digital signal; each output controls 16 first current units; the low 4 bits of the fourth digital signal simultaneously control 8, 4, 2, and 1 first current units from high to low, respectively; or The first current source array comprises 127 first current units; the 7 bits of the fourth digital signal simultaneously control 64, 32, 16, 8, 4, 2, and 1 first current units from high to low, respectively.

3. The digital control envelope tracking power supply modulator according to claim 1, wherein: The second current source array comprises a 7-128 decoder and 127 second current units; the 7-128 decoder is in thermometer code, and the input signal is the fifth digital signal; each output controls one second current unit; or The second current source array comprises: a 3-8 decoder, 127 second current units; the 3-8 decoder is in a thermometer code, a high 3-bit fifth digital signal is input, and each output controls 16 second current units; a low 4-bit fifth digital signal simultaneously controls 8, 4, 2 and 1 second current units from high to low respectively; or, The second current source array comprises: 127 second current units; and a 7-bit fifth digital signal simultaneously controls 64, 32, 16, 8, 4, 2 and 1 second current units from high to low respectively.

4. The digitally controlled envelope tracking power supply modulator of claim 2, wherein, The first current unit comprises: a PMOS current mirror, a PMOS switch tube; the PMOS switch tube is connected in series with the output end of the PMOS current mirror; the gate of the PMOS switch tube is a first control end; the drain of the PMOS switch tube is connected to the first output end; when the first control end is high, the PMOS switch tube is turned off; or, The first current unit comprises: a PMOS power tube; the gate of the PMOS power tube is a first control end; the drain of the PMOS power tube is connected to the first output end; when the first control end is high, the PMOS power tube is turned off.

5. The digitally controlled envelope tracking power supply modulator of claim 3, wherein, The second current unit comprises: an NMOS current mirror, an NMOS switch tube; the NMOS switch tube is connected in series with the output end of the NMOS current mirror; the gate of the NMOS switch tube is a second control end; the drain of the NMOS switch tube is connected to the first output end; when the second control end is low, the NMOS switch tube is turned off; or, The second current unit comprises: an NMOS power tube; the gate of the NMOS power tube is a second control end; the drain of the NMOS power tube is connected to the first output end; when the second control end is low, the NMOS power tube is turned off.

6. The digitally controlled envelope tracking power supply modulator of claim 1, wherein, The switching amplifier is composed of six parts: a low-pass filter, a PID compensator, a sawtooth wave generator, a comparator, a two-phase non-overlapping and driving circuit, and a power transistor.

7. The digitally controlled envelope tracking power supply modulator of claim 6, wherein: the first input is connected to the input of the low-pass filter, and the second input is connected to the in-phase input of the PID compensator; the low-pass filter is an RC filter with a cutoff frequency of 5 MHz, and the low-pass filter outputs a second analog signal to the inverting input of the PID compensator; the PID compensator outputs a third analog signal and adjusts the loop bandwidth to 1 MHz; the sawtooth wave generator outputs a fourth analog signal; the fourth analog signal is a 10 MHz fixed frequency sawtooth wave; the third analog signal is input to the inverting input of the comparator, and the fourth analog signal is input to the in-phase input of the comparator; the comparator compares the third analog signal and the fourth analog signal and outputs a fifth analog signal; The two-phase non-overlapping driving circuit processes the fifth analog signal to generate a two-phase non-overlapping clock with driving capability to drive the power transistor. The power transistor includes a power transistor made of PMOS and a power transistor made of NMOS, whose drains are connected together and connected to the second output terminal.

8. The digitally controlled envelope tracking power supply modulator of claim 7, wherein: The digital-to-analog converter generates the first analog signal according to the third digital signal; the first analog signal should analog the theoretical value of the second analog signal.

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