Pipeline analog-to-digital converter and timing adjustment method

Abstract

The present case relates to a pipeline analog-to-digital converter and a timing adjustment method. The pipeline analog-to-digital converter includes a multi-stage converter circuit system, a detection circuit system, and a frequency generator circuit. The multi-stage converter circuit system converts an input signal into a plurality of digital codes in sequence. One of the multi-stage converter circuit systems includes a sub-analog-to-digital converter circuit and a multiplication digital-to-analog converter circuit. The sub-analog-to-digital converter circuit performs a quantization operation according to a first signal to generate a corresponding one of the plurality of digital codes. The multiplication digital-to-analog converter circuit processes the corresponding one of the digital codes and the first signal in response to a frequency signal to generate a current-stage residual signal. The detection circuit system detects whether the quantization operation is completed to generate a control signal. The frequency generator circuit adjusts the timing of the frequency signal according to the control signal.

Description

Technical Field

[0001] The present invention relates to a pipeline analog-to-digital converter, and more particularly to a pipeline analog-to-digital converter with an adjustable amplification period and a timing adjustment method thereof. Background Art

[0002] The pipeline analog-to-digital converter can sequentially convert the input signal into the corresponding digital code through multiple stages of conversion. In the prior art, the operation period of each stage of conversion is fixed. As the frequency speed increases, the time of a cycle is getting shorter and shorter. In order for the pipeline analog-to-digital converter to correctly process the conversion result in a very short cycle, some circuits in the pipeline analog-to-digital converter (such as the residual amplifier) ​​need to have a higher current. As a result, the overall power consumption will increase and the overall circuit area will increase. Summary of the invention

[0003] In some embodiments, the pipeline analog-to-digital converter includes a multi-stage converter circuit system, a detection circuit system, and a frequency generator circuit. The multi-stage converter circuit system is used to convert an input signal into multiple digital codes in sequence. One of the multi-stage converter circuit systems includes a sub-analog-to-digital converter circuit and a multiplication digital-to-analog converter circuit. The sub-analog-to-digital converter circuit is used to perform a quantization operation according to a first signal to generate a corresponding one of the digital codes, wherein the first signal is the input signal or a previous stage residual signal. The multiplication digital-to-analog converter circuit is used to process the corresponding one of the digital codes and the first signal in response to a first frequency signal to generate a current stage residual signal. The detection circuit system is used to detect whether the quantization operation is completed to generate a control signal. The frequency generator circuit is used to adjust a timing of the first frequency signal according to the control signal.

[0004] In some embodiments, the timing adjustment method includes the following operations: providing a first frequency signal to one of the multi-stage converter circuit systems of a pipeline analog converter, wherein the one of the stage converter circuit systems performs a quantization operation based on the first signal to generate a digital code, and processes the digital code and the first signal based on the first frequency signal to generate a current stage residual signal; detecting whether the quantization operation is completed to generate a control signal; and adjusting the timing of the first frequency signal based on the control signal.

[0005] The features, practical operation and efficacy of the present invention are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present invention;

[0007] Figure 1BAccording to some embodiments of the present invention, Figure 1A Waveform diagrams of multiple frequency signals in ;

[0008] Figure 2 According to some embodiments of the present invention, Figure 1A A schematic diagram of a sub-analog-to-digital converter circuit;

[0009] Figure 3A According to some embodiments of the present invention, Figure 1A A schematic diagram of a detection circuit system;

[0010] Figure 3B According to some embodiments of the present invention, Figure 1A A schematic diagram of a detection circuit system;

[0011] Figure 4 A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present invention;

[0012] Figure 5 A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present invention;

[0013] Figure 6 A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present invention; and

[0014] Figure 7 The present invention is a flowchart of a timing adjustment method according to some embodiments of the present invention. DETAILED DESCRIPTION

[0015] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein in the context of this application are merely illustrative and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0016] As used herein, "coupling" or "connection" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuitry" may refer to a single system formed by at least one circuit, and the term "circuit" may refer to a device that is connected in a certain manner by at least one transistor and / or at least one active and passive component to process signals.

[0017] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this document, the terms first, second, third, etc. are used to describe and identify each component. Therefore, the first component in this document can also be referred to as the second component without departing from the original intention of the case. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

[0018] Figure 1A A schematic diagram of a pipeline analog-to-digital converter 100 is drawn according to some embodiments of the present invention, and Figure 1B According to some embodiments of the present invention, Figure 1A The pipelined analog-to-digital converter 100 includes a sample-and-hold circuit 110, a multi-stage converter circuit system 120[1] to 120[3], a detection circuit system 130, a frequency generator circuit 140, and a digital correction circuit 150.

[0019] The sample-and-hold circuit 110 samples the input signal VIN according to the clock signal CLK1, and outputs the sampled input signal VIN as a signal S1. In some embodiments, the sample-and-hold circuit 110 can be implemented by a switched capacitor circuit. The multi-stage converter circuit systems 120[1] to 120[3] sequentially convert the sampled input signal VIN (i.e., signal S1) into a plurality of digital codes D1. In some embodiments, the multi-stage converter circuit systems 120[1] to 120[2] have the same structure. In some embodiments, the converter circuit system 120[3] can be (but not limited to) a flash analog-to-digital converter circuit, which is used to generate the last of the plurality of digital codes D1 according to the residual signal S2[2] generated by the converter circuit system 120[2].

[0020] Taking the converter circuit system 120[1] as an example, the converter circuit system 120[1] includes a sub-analog-to-digital converter circuit 121 and a multiplication digital-to-analog converter circuit 122. During the sampling period Tsample of the clock signal CLK1, the sub-analog-to-digital converter circuit 121 is used to perform a quantization operation according to the signal S1 to generate a corresponding one of a plurality of digital codes D1. The multiplication digital-to-analog converter circuit 122 is used to process the corresponding one of the plurality of digital codes D1 and the signal S1 according to the clock signal CLK2 to generate a current-stage residual signal S2[1]. For example, in response to a rising edge RE of the clock signal CLK2, the multiplication digital-to-analog converter circuit 122 may start processing the corresponding digital code D1 and the signal S1, and generate the current-stage residual signal S2[1] during the amplification period Tamplify of the clock signal CLK2. The operation of the converter circuit system 120 [ 2 ] is performed according to the clock signal CLK1 ′ and the clock signal CLK2 ′, and the operation of the converter circuit system 120 [ 2 ] can be understood with reference to the converter circuit system 120 [ 1 ], so it will not be repeated.

[0021] In some embodiments, the multiplication digital-to-analog converter circuit 122 includes a sub-digital-to-analog converter circuit 122-1, a subtractor circuit 122-2, and a residual amplifier circuit 122-3. In response to the clock signal CLK2, the sub-digital-to-analog converter circuit 122-1 can convert the corresponding digital code D1 into a signal S2. The subtractor circuit 122-2 is used to subtract the signal S2 from the signal S1 to generate a signal S3. The residual amplifier circuit 122-3 can amplify the signal S3 to output a current-stage residual signal S2 [1]. In some embodiments, the sub-digital-to-analog converter circuit 122-1, the subtractor circuit 122-2, and the residual amplifier circuit 122-3 can be implemented by a switched capacitor circuit (not shown). Some switches of the switched capacitor circuit are turned on during the sampling period Tsample of the clock signal CLK1 to store the signal S1. Other switches of the switched capacitor circuit are turned on during the amplification period Tamplify of the clock signal CLK2 to perform related operations of the multiplication digital-to-analog converter circuit 122.

[0022] The detection circuit system 130 is used to detect whether the quantization operation of the signal S1 is completed to generate the control signal VC. The frequency generator circuit 140 can be used to generate the frequency signal CLK1, the frequency signal CLK2, the frequency signal CLK1′ and the frequency signal CLK2′. The frequency generator circuit 140 can adjust the timing of the frequency signal CLK2 (and / or the frequency signal CLK2′) according to the control signal VC. For example, if the detection circuit system 130 detects that the quantization operation of the signal S1 is completed, the detection circuit system 130 can output the control signal VC with a first logic value (for example, a logic value of 0). In response to the control signal VC, the frequency generator circuit 140 can switch the transition edge (for example, a rising edge RE) of the frequency signal CLK2 so that the multiplication digital-to-analog converter circuit 122 starts to process the corresponding digital code D1 and the signal S1.

[0023] Alternatively, if the detection circuit system 130 detects that the quantization operation of the signal S1 has not been completed, the detection circuit system 130 may output a control signal VC having a second logic value (e.g., a logic value of 1). In response to the control signal VC, the frequency generator circuit 140 may delay the transition edge of the frequency signal CLK2 (e.g., delay the rising edge RE to the rising edge RE′) so that the multiplication digital-to-analog converter circuit 122 delays processing the corresponding digital code D1 and the signal S1. In some embodiments, the frequency generator circuit 140 may include an oscillator circuit with delay control, which can adjust the frequency signal CLK2 according to the control signal VC. The detailed operation here will be referred to later. Figure 2 , Figure 3A and Figure 3B illustrate.

[0024] The digital correction circuit 150 is used to combine multiple digital codes D1 to generate a digital code DOUT. In some implementations, the digital correction circuit 150 can be used to correct the offset error of the sub-digital-to-analog converter circuit 122-1 and / or the gain error of the residual amplifier circuit 122-3. In some embodiments, the digital correction circuit 150 can be implemented by a plurality of digital logic circuits.

[0025] In some related technologies, the timing (e.g., transition edge) of the frequency signal CLK2 is fixed. In these technologies, if the quantization operation requires a longer processing time due to actual process variation and / or due to a voltage difference (e.g., the difference between the signal S1 and the reference voltage VREF1 described later) that is too small, the multiplication digital-to-analog converter circuit may receive an inaccurate (e.g., not yet stable) digital code, thereby generating an inaccurate residual signal. Compared to the above-mentioned technology, in some embodiments of the present case, by setting up a detection circuit system 130, it can be ensured that the multiplication digital-to-analog converter circuit 122 performs subsequent operations only after the quantization operation is completed. In this way, the multiplication digital-to-analog converter circuit 122 can receive the correct digital code to correctly generate the current-stage residual signal S2 [1]. In addition, by adjusting the amplification period Tamplify, the current of the residual amplifier circuit 122-3 can be reduced, thereby reducing the power and circuit area consumed by the residual amplifier circuit 122-3.

[0026] Figure 2 According to some embodiments of the present invention, Figure 1A Schematic diagram of a sub-ADC circuit 121. In some embodiments, the sub-ADC circuit 121 includes a comparator circuit 201, a comparator circuit 202, and an encoder circuit 203. The comparator circuit 201 and the comparator circuit 202 compare the signal S1 with the reference voltage VREF1 and the reference voltage VREF2 respectively (equivalent to the aforementioned quantization operation) to generate a plurality of output signals VO1 to VO4.

[0027] In detail, the comparator circuit 201 compares the signal S1 with the reference voltage VREF1 to generate an output signal VO1 and an output signal VO2. In some embodiments, the comparator circuit 201 is a differential comparator circuit. In an initial state, the two output terminals of the differential comparator circuit are reset to a preset level so that the output signal VO1 and the output signal VO2 have the default level. For example, the preset level is a high level, and the output signal VO1 and the output signal VO2 have a logic value of 1 in the initial state. Alternatively, in other examples, the preset level is a low level, and the output signal VO1 and the output signal VO2 have a logic value of 0 in the initial state. After the comparison between the signal S1 and the reference voltage VREF1 is completed, one output terminal of the comparator circuit 201 will have a high level, and the other output terminal of the comparator circuit 201 will have a low level. In other words, after the quantization operation is completed, one of the output signal VO1 and the output signal VO2 has a logic value of 1, and the other of the output signal VO1 and the output signal VO2 has a logic value of 0. Therefore, the detection circuit system 130 can determine whether the quantization operation is completed according to the logic values ​​of the output signal VO1 and the output signal VO2 .

[0028] Similarly, the comparator circuit 202 compares the signal S1 with the reference voltage VREF2 to generate an output signal VO3 and an output signal VO4. The relevant operations of the comparator circuit 202 can refer to the relevant operations of the comparator circuit 201, so they are not repeated. In some embodiments, the reference voltage VREF1 can be (but not limited to) 0.25 times the positive reference voltage, and the reference voltage VREF2 can be (but not limited to) 0.25 times the negative reference voltage, wherein the positive reference voltage and the negative reference voltage can be used to define the maximum input signal range.

[0029] The encoder circuit 203 is used to encode multiple output signals VO1 to VO4 according to the frequency signal CLK2 to output a corresponding one of the multiple digital codes D1. In some embodiments, the encoder circuit 203 may include multiple logic gate circuits, which output the corresponding digital code D1 when the frequency signal CLK2 is at a high level. For example, the encoder circuit 203 may include multiple AND gate circuits (not shown) to achieve it. Some of the AND gate circuits generate multiple first signals according to the output signal VO1 and the output signal VO3, the output signal VO2, and the output signal VO3, the output signal VO2 and the output signal VO4. The remaining AND gate circuits are used to output the first signals as multiple bits of the corresponding digital code D1 when the frequency signal CLK2 is at a high level. The above-mentioned implementation of the encoder circuit 203 is used for example, and the present case is not limited thereto. Various types of encoder circuits 203 are all within the scope of the present case.

[0030] Figure 3A According to some embodiments of the present invention, Figure 1A The detection circuit system 130 includes a plurality of logic gate circuits 301, a plurality of flip-flop circuits 302, and a logic gate circuit 303. As previously described, Figure 2In some examples, the output signal VO1 and the output signal VO2 have a logic value of 1 in the initial state. After the comparison operation is completed, one of the output signal VO1 and the output signal VO2 has a logic value of 1, and the other of the output signal VO1 and the output signal VO2 has a logic value of 0. Under this condition, each of the multiple logic gate circuits 301 can be implemented by a NAND gate circuit. The multiple logic gate circuits 301 generate multiple validation signals SV according to the multiple output signals VO1 to VO4. For example, the first logic gate circuit 301 generates a validation signal SV according to the multiple output signals VO1 to VO2. If the output signal VO1 and the output signal VO2 are both logic values ​​1, this logic gate circuit 301 can output a validation signal SV with a logic value of 0 to indicate that the quantization operation has not been completed. If one of the output signal VO1 and the output signal VO2 is a logic value 1, and the other of the output signal VO1 and the output signal VO2 is a logic value 0, this logic gate circuit 301 can output a validation signal SV with a logic value of 1 to indicate that the quantization operation has been completed. Similarly, the second logic gate circuit 301 can generate the validation signal SV according to the plurality of output signals VO3 to VO4.

[0031] The plurality of flip-flop circuits 302 receive the plurality of validation signals SV respectively according to the frequency signal CLK3 to generate the plurality of detection signals SD. In some embodiments, each of the plurality of flip-flop circuits 302 may be a D-type flip-flop circuit. In some embodiments, the frequency signal CLK3 may be the frequency signal CLK2. In some embodiments, the frequency signal CLK3 and the frequency signal CLK2 are set to have the same initial timing, or the phase of the frequency signal CLK3 leads the phase of the frequency signal CLK2. In response to the rising edge of the frequency signal CLK3, the plurality of flip-flop circuits 302 may output the plurality of validation signals SV as the plurality of detection signals SD. If each of the plurality of detection signals SD has a predetermined logic value (in this case, a logic value of 1), the quantization operation of the representative signal S1 has been completed. If at least two of the plurality of detection signals SD have different logic values ​​(for example, one detection signal SD has a logic value of 0, and the other detection signal SD has a logic value of 1), or if each of the plurality of detection signals SD does not have a predetermined logic value, the quantization operation of the representative signal S1 has not been completed.

[0032] The logic gate circuit 303 is used to determine whether the quantization operation of the signal S1 is completed according to the plurality of detection signals SD to generate the control signal VC. In this example, the logic gate circuit 303 may be an AND gate circuit, which generates the control signal VC according to the plurality of detection signals SD. When each of the plurality of detection signals SD has a logic value of 1, the logic gate circuit 303 determines that the quantization operation is completed and outputs the control signal VC having a logic value of 1. When at least two of the plurality of detection signals SD have different logic values, or when each of the detection signals SD does not have a logic value of 1, the logic gate circuit 303 determines that the quantization operation is not completed and outputs the control signal VC having a logic value of 0.

[0033] Figure 3B According to some embodiments of the present invention, Figure 1A As previously described, in Figure 2 In some other examples, the output signal VO1 and the output signal VO2 have a logic value of 0 in the initial state. After the comparison operation is completed, one of the output signal VO1 and the output signal VO2 has a logic value of 1, and the other of the output signal VO1 and the output signal VO2 has a logic value of 0. Under this condition, each of the multiple logic gate circuits 301 can be implemented by a NOR gate circuit. If the output signal VO1 and the output signal VO2 are both logic values ​​0, this logic gate circuit 301 can output a validation signal SV with a logic value of 1 to indicate that the quantization operation has not been completed. If one of the output signal VO1 and the output signal VO2 is a logic value 1, and the other of the output signal VO1 and the output signal VO2 is a logic value 0, this logic gate circuit 301 can output a validation signal SV with a logic value of 0 to indicate that the quantization operation has been completed. Similarly, the second logic gate circuit 301 can generate a validation signal SV according to the multiple output signals VO3 to VO4.

[0034] In this example, the logic gate circuit 303 may be a NOR gate circuit, which generates the control signal VC according to the plurality of detection signals SD. If each of the plurality of detection signals SD has a predetermined logic value (in this example, a logic value of 0), the logic gate circuit 303 determines that the quantization operation is completed, and outputs the control signal VC having a logic value of 1. If at least two of the plurality of detection signals SD have different logic values, or if each of the plurality of detection signals SD does not have the predetermined logic value, the logic gate circuit 303 determines that the quantization operation is not completed, and outputs the control signal VC having a logic value of 0.

[0035] Figure 4 A schematic diagram of a pipelined analog-to-digital converter 400 is drawn according to some embodiments of the present invention. The above embodiments are described by adjusting the amplification period of the converter circuit system 120 [1] as an example, but the present invention is not limited to this. For example, Figure 4 As shown, the amplification period of the converter circuit system 120[2] can also be adjusted (i.e., the frequency signal CLK2′ is adjusted). In this example, the sub-analog-to-digital converter circuit 121 is used to perform a quantization operation according to the previous stage residual signal S2[1] to generate a corresponding one of the multiple digital codes D1. The remaining operations are similar to the previous embodiments, so they will not be repeated.

[0036] Figure 5 A schematic diagram of a pipelined analog-to-digital converter 500 is drawn according to some embodiments of the present invention. In this example, the amplification periods of the converter circuit system 120[1] and the converter circuit system 120[2] are adjusted. For example, the detection circuit system 130 includes two sets of Figure 3A or Figure 3B In the circuits shown in , one group of circuits detects whether the quantization operation of the converter circuit system 120 [ 1 ] is completed to adjust the frequency signal CLK2 , and another group of circuits detects whether the quantization operation of the converter circuit system 120 [ 2 ] is completed to adjust the frequency signal CLK2 ′.

[0037] Figure 6 A schematic diagram of a pipelined analog-to-digital converter 600 is drawn according to some embodiments of the present invention. Compared with the aforementioned embodiments, in this example, the pipelined analog-to-digital converter 600 further includes a memory circuit 601. In some embodiments, in the pre-shipment test, the detection circuit system 130 can detect the maximum delay time that at least one of the frequency signal CLK2 and the frequency signal CLK2′ needs to be adjusted, and record the information F1 of the maximum delay time to the memory circuit 601. The frequency generator circuit 140 can read the memory circuit 601 to obtain the control signal VC according to the information F1. In some embodiments, the memory circuit 601 can be a register circuit. In some embodiments, the memory circuit 601 can be integrated in the frequency generator circuit 140. In some embodiments, the detection result of the detection circuit system 130 and the frequency signal generated by the frequency generator circuit 140 can be fed back to an external measurement machine to analyze the maximum delay time to generate the information F1.

[0038] In some embodiments, the operation concept of the detection circuit system 130 and the memory circuit 601 is similar to a foreground calibration mechanism, wherein the detection circuit system 130 and the memory circuit 601 can adjust at least one of the clock signal CLK2 and the clock signal CLK2′ before the pipelined analog-to-digital converter 600 converts the actual data. Figure 1A , Figure 4 or Figure 5In some of the illustrated embodiments, the operating concept of the detection circuit system 130 is similar to a background correction mechanism, which can dynamically adjust at least one of the frequency signal CLK2 and the frequency signal CLK2′ during the process of the pipelined analog-to-digital converter 100, 400 or 500 converting actual data.

[0039] The number of circuits and related configurations in the above embodiments are for illustrative purposes only, but are not intended to be limiting. It should be understood that the number of circuits and related configurations in the above embodiments may be adjusted accordingly based on actual application requirements (such as resolution, power, etc.).

[0040] Figure 7 A flowchart of a timing adjustment method 700 is drawn according to some embodiments of the present invention. In operation S710, a frequency signal is provided to one of the multi-stage converter circuit systems of the pipeline analog-to-digital converter, wherein the one of the multi-stage converter circuit systems performs a quantization operation according to a first signal to generate a digital code, and processes the digital code and the first signal according to the frequency signal to generate a current stage residual signal. In some embodiments, the first signal is an input signal VIN or a previous stage residual signal (e.g., a residual signal S2[1]). In operation S720, it is detected whether the quantization operation is completed to generate a control signal. In operation S730, the timing of the frequency signal is adjusted according to the control signal.

[0041] The description of the above operations S710, S720 and S730 can refer to the above embodiments, so they will not be repeated. The multiple operations of the above timing adjustment method 700 are only examples, and are not limited to be performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present case, the various operations under the timing adjustment method 700 can be appropriately increased, replaced, omitted or performed in a different order.

[0042] In summary, the pipelined analog-to-digital converter and timing adjustment method in some embodiments of the present invention can detect whether the quantization operation of each converter circuit system is completed and adjust the amplification period accordingly. In this way, the converter circuit system at each stage can be prevented from generating inaccurate digital codes and a certain amount of power and circuit area can be saved.

[0043] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. Ordinary technicians in this technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be based on the scope defined by the claims of this specification.

[0044]

Explanation of symbols

[0045] 100, 400, 500, 600: Pipeline analog-to-digital converter

[0046] 110: Sample and hold circuit

[0047] 120[1], 120[2], 120[3]: Converter circuit system

[0048] 121: Sub-Analog-to-Digital Converter Circuit

[0049] 122: Multiplication Digital Analog Converter Circuit

[0050] 122-1: Sub-digital analog converter circuit

[0051] 122-2: Subtractor circuit

[0052] 122-3: Residual value amplifier circuit

[0053] 130: Detection circuit system

[0054] 140: Frequency generator circuit

[0055] 150: Digital correction circuit

[0056] 201, 202: Comparator circuit

[0057] 203: Encoder circuit

[0058] 601: Memory Circuit

[0059] 700: Timing Adjustment Method

[0060] CLK1, CLK2, CLK1′, CLK2′, CLK3: frequency signal

[0061] D1, DOUT: digital code

[0062] F1: Information

[0063] S1, S2, S3: Signal

[0064] S2[1], S2[2]: residual signal

[0065] VC: control signal

[0066] VIN: Input signal

[0067] RE, RE′: rising edge

[0068] S710, S720, S730: Operation

[0069] Tsample: sampling period

[0070] Tamplify: During the amplification

[0071] VREF1, VREF2: reference voltage

[0072] VO1 to VO4: output signal.

Claims

1. A pipeline analog-to-digital converter, comprising: A multi-stage converter circuit system is used to convert an input signal into a plurality of digital codes in sequence, wherein one of the stage converter circuit systems comprises: a sub-analog-to-digital converter circuit, configured to perform a quantization operation according to a first signal to generate a corresponding one of the digital codes, wherein the first signal is the input signal or a previous stage residual signal; as well as a multiplication digital-to-analog converter circuit for processing the corresponding one of the digital codes and the first signal in response to a first frequency signal to generate a current-stage residual signal; a detection circuit system for detecting whether the quantization operation is completed to generate a control signal; as well as a frequency generator circuit, for adjusting a timing of the first frequency signal according to the control signal, When the detection circuit system detects that the quantization operation is completed, the frequency generator circuit is used to switch a transition edge of the first frequency signal according to the control signal, so that the multiplication digital-to-analog converter circuit starts to process the corresponding one of the digital codes and the first signal.

2. The pipelined analog-to-digital converter of claim 1 , wherein when the detection circuit system detects that the quantization operation is incomplete, the frequency generator circuit is used to delay a transition edge of the first frequency signal according to the control signal so that the multiplication digital-to-analog converter circuit postpones processing of the corresponding one of the digital codes and the first signal.

3. The pipelined analog-to-digital converter of claim 1 , wherein the detection circuit system comprises: A plurality of first logic gate circuits, used for generating a plurality of validation signals according to a plurality of output signals from the sub-analog-to-digital converter circuit; A plurality of flip-flop circuits, for respectively receiving the validation signals according to a second frequency signal to generate a plurality of detection signals; and A second logic gate circuit is used to determine whether the quantization operation is completed according to the detection signals to generate the control signal. 4 . The pipelined analog-to-digital converter of claim 3 , wherein when each of the detection signals has a predetermined logic value, the second logic gate circuit determines that the quantization operation is completed. 5 . The pipelined analog-to-digital converter of claim 3 , wherein when at least two of the detection signals have different logic values, or when each of the detection signals does not have a predetermined logic value, the second logic gate circuit determines that the quantization operation is incomplete.

6. The pipelined analog-to-digital converter of claim 3, wherein the sub-analog-to-digital converter circuit comprises: A plurality of comparator circuits, for comparing the first signal with a plurality of reference voltages respectively, to generate the output signals; and An encoder circuit is used to encode the output signals to output the corresponding one of the digital codes. 7 . The pipelined analog-to-digital converter as claimed in claim 3 , wherein the second frequency signal is the same as the first frequency signal, or a phase of the second frequency signal leads a phase of the first frequency signal.

8. The pipelined analog-to-digital converter of claim 1, further comprising: A memory circuit is used to store information indicating a maximum delay time of the first frequency signal, wherein the detection circuit system is also used to generate the information, and the frequency generator circuit is also used to obtain the control signal according to the information.

9. A timing adjustment method, comprising: Providing a first frequency signal to one of the multi-stage converter circuit systems of a pipeline analog converter, wherein the one of the stage converter circuit systems performs a quantization operation according to the first signal to generate a digital code, and processes the digital code and the first signal according to the first frequency signal to generate a current stage residual signal; detecting whether the quantization operation is completed to generate a control signal; and Adjust a timing of the first frequency signal according to the control signal, When the quantization operation is detected to be completed, a transition edge of the first frequency signal is switched according to the control signal so that one of the stage converter circuit systems starts to process a corresponding one of the digital codes and the first signal.

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