Method and apparatus for configuring a chip, device, and storage medium

Abstract

Embodiments of the present application disclose a method and apparatus, device, and storage medium for configuring a chip; wherein, the method includes: determining a wiring layer where a signal line is located; and adding a current path from a power supply point in a power network to a device in a wiring layer adjacent to the wiring layer where the signal line is located, so as to reduce the resistance voltage drop of the power network.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip design, including but not limited to methods and devices, equipment, and storage media for configuring chips. Background Art

[0002] The problem of resistance voltage drop (IR drop) has always existed in chips. If the global resistance voltage drop in a chip is too high, logic gates may malfunction, causing the chip to fail completely, even though logic simulation shows that the design is correct. If the local resistance voltage drop is too high (which usually occurs under some specific conditions, such as all bus data flipping synchronously), the chip will intermittently exhibit some functional failures. Even if the above extreme cases do not occur, the resistance voltage drop will still cause a reduction in the chip's computing speed. Experiments show that a 5% resistance voltage drop on a logic gate unit will reduce the normal gate speed by 15%. As semiconductor technology evolves towards deep sub-micron levels, the resistance problem has increasingly become a bottleneck in chip design. How to reduce the resistance voltage drop has become an issue that chip designers have to consider.

[0003] The power network in a common logic area can form a power plane, and the resistance voltage drop is relatively easy to meet. However, in some channel areas, since the power network is fragmented, it is very easy to generate a large resistance voltage drop. For example, Figure 1 As shown, in a chip, the power networks of functional modules such as the Central Processing Unit (CPU), Mobile Data Modem (MDM), Graphics Processing Unit (GPU), Neural Network Processing Unit (NPU), Double Data Rate (DDR), Peripheral Component Interconnect express (PCIe) interface, Universal Serial Bus (USB) interface, and PERIpheral equipment (PERI) can form a power plane, while the power network in the channel is easily divided into long and narrow areas, resulting in a large resistance voltage drop problem. Summary of the Invention

[0004] In view of this, the method, device, equipment, and storage medium for configuring a chip provided by the embodiments of the present application can reduce the resistance voltage drop of the power network by additionally increasing the current path from the power supply point to the device in the original power network. The method, device, equipment, and storage medium for configuring a chip provided by the embodiments of the present application are implemented as follows:

[0005] The method for configuring a chip provided by the embodiments of the present application includes: determining the wiring layer where the signal line is located; adding a current path from the power supply point to the device in the power network in the wiring layer adjacent to the wiring layer where the signal line is located to reduce the resistance voltage drop of the power network.

[0006] The device for configuring a chip provided by the embodiments of the present application includes: a determination module for determining the wiring layer where the signal line is located; an enhancement module for adding a current path from the power supply point to the device in the power network in the wiring layer adjacent to the wiring layer where the signal line is located to reduce the resistance voltage drop of the power network.

[0007] The electronic device provided by the embodiments of the present application includes a memory and a processor. The memory stores a computer program that can run on the processor, and the processor implements the method described in the embodiments of the present application when executing the program.

[0008] The computer-readable storage medium provided by the embodiments of the present application stores a computer program thereon, and is characterized in that the computer program implements the method described in the embodiments of the present application when executed by a processor.

[0009] In the embodiments of the present application, first, determine the wiring layer where the signal line is located; then, additionally add a current path from the power supply point to the device in the power network in the wiring layer adjacent to the wiring layer where the signal line is located; in this way, it is very likely to shorten the current path from the power supply point to the device, reduce the equivalent resistance between the two, and thus effectively reduce the resistance voltage drop between the two. Description of the Drawings

[0010] The drawings here are incorporated into the specification and constitute a part of this specification. These drawings show embodiments that conform to the present application and are used together with the specification to explain the technical solutions of the present application.

[0011] Figure 1 It is a schematic diagram of the chip structure of a typical multi-power domain;

[0012] Figure 2 It is a schematic diagram of the channel signal line direction;

[0013] Figure 3 It is a schematic diagram of the implementation process of the method for configuring a chip provided by the embodiments of the present application;

[0014] Figure 4 Schematic diagram of the implementation process of another method for configuring a chip provided by an embodiment of the present application;

[0015] Figure 5 Schematic diagram after adding a new power line provided by an embodiment of the present application;

[0016] Figure 6 Schematic diagram of the implementation process of yet another method for configuring a chip provided by an embodiment of the present application;

[0017] Figure 7 Schematic diagram for comparison before and after enhancing the power network in an embodiment of the present application;

[0018] Figure 8 Schematic diagram of the structure of a device for configuring a chip provided by an embodiment of the present application;

[0019] Figure 9 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will further describe the specific technical solutions of the present application in detail with reference to the accompanying drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application but are not intended to limit the scope of the present application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0022] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0023] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are used to distinguish similar or different objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0024] In a chip, the number of wiring metal layers ranges from 4 to 15, and of course, it is not limited to this. However, the wiring direction of each layer remains unchanged, and the wiring directions of adjacent layers are perpendicular. For example, if Metal6 is horizontally wired, then Metal5 and Metal7 must be vertically wired. As Figure 2As shown, the wiring direction of the Mn-th layer 202 is longitudinal, and the wiring directions of the adjacent upper and lower layers, namely the Mn-1-th layer 201 and the Mn+1-th layer 203, are transverse. This is the basic rule of wiring in chip configuration.

[0025] During the research process, the inventor found that: due to the single directionality (either transverse or longitudinal) of the channel traces, half of the layers will be wasted by the channel traces. For example Figure 2 As shown, assuming the data flow from A to B, it first passes through the longitudinal channel 211 and then through the transverse channel 212 to reach B. As Figure 2 shown, the signals are all in the transverse wiring layer 21 in the transverse channel 212. Then, due to the characteristics of the channel itself, the corresponding area of the transverse channel 212 in the upper layer (i.e., the longitudinal wiring layer) of this transverse wiring layer is the unrouted blank area, and the corresponding area of the transverse channel 212 in the lower layer (i.e., the longitudinal wiring layer) of this transverse wiring layer is also the blank area. It can be seen that for the wiring in the channel area, the utilization rate of the longitudinal wiring layer is very low. Similarly, for the longitudinal channel 211, the corresponding areas in the adjacent upper and lower layers are also blank areas, and the utilization rate of the transverse wiring layer is also relatively low.

[0026] In view of this, the embodiment of the present application provides a method for configuring a chip, aiming to make full use of the unrouted blank areas in the upper and lower wiring layers corresponding to the signal lines in the channel area, and without any cost, increase the current path from the power supply points to the devices in the power network deployed in the channel, so as to achieve the purpose of reducing the resistance voltage drop of the power network.

[0027] The method can be applied to an electronic device, and the electronic device can be any device with information processing capabilities such as a mobile phone, a tablet computer, a laptop computer, or a desktop computer. The functions implemented by the method for configuring a chip can be realized by the processor in the electronic device calling program code. Of course, the program code can be stored in a computer storage medium. It can be seen that the electronic device at least includes a processor and a storage medium.

[0028] Figure 3 For the implementation flow schematic diagram of the method for configuring a chip provided by the embodiment of the present application, as Figure 3 shown, the method may include the following steps 301 to step 302:

[0029] Step 301, determine the wiring layer where the signal line is located.

[0030] In some embodiments, the wiring layer where the signal line is located can be determined according to the configured chip layout. The configured chip layout may be a design layout in which part or all of the basic power network and signal network of the chip have been deployed. For example, the configured chip layout is a chip layout that meets the Tapeout standard. The so-called basic power network refers to a power network that meets the basic requirements of resistance voltage drop. For example, a power network with a resistance voltage drop not greater than 5%.

[0031] Step 302: Add a current path from the power supply point in the power network to the device in the wiring layer adjacent to the wiring layer where the signal line is located, so as to reduce the resistance voltage drop of the power network.

[0032] In some embodiments, according to the routing information of the signal line, the blank area corresponding to the signal line in the adjacent wiring layer can be determined; by using the blank area, a current path from the power supply point in the deployed power network to the device is added.

[0033] In some embodiments, the routing information of the signal line may include information such as the position, length, and width of the line segment. Based on this information, the blank area corresponding to the signal line in its adjacent wiring layer can be determined. The so-called adjacent wiring layer refers to the wiring layer adjacent to the wiring layer where the signal line is located. The adjacent wiring layer may include the upper neighbor wiring layer of the wiring layer where the signal line is located and / or the lower neighbor wiring layer of the wiring layer where the signal line is located.

[0034] In some embodiments, the electronic device can deploy at least one power line in the blank area to increase the current path from the power supply point to the device.

[0035] In the embodiments of the present application, the type of the power line is not limited. The power line can be a power line or a ground line.

[0036] In the embodiments of the present application, first, the wiring layer where the signal line is located is determined; then, a current path from the power supply point in the power network to the device is additionally added in the wiring layer adjacent to the wiring layer where the signal line is located; in this way, the current path from the power supply point to the device can be shortened with a high probability, so that the equivalent resistance between the two is reduced, and further the resistance voltage drop between the two is effectively reduced.

[0037] The embodiments of the present application further provide a method for configuring a chip. Figure 4 For the implementation process schematic diagram of another method for configuring a chip provided by the embodiments of the present application, as Figure 4 shown, this method may include the following steps 401 to step 403:

[0038] Step 401: Obtain the layout data of the chip layout that meets the manufacturing submission standard;

[0039] Step 402: Determine the wiring layer where the signal line is located from the layout data.

[0040] It can be understood that in the embodiments of the present application, power network enhancement is performed before the chip is submitted for manufacturing (Tapeout), that is, on the basis that the entire chip configuration is basically frozen and meets the manufacturing submission standard, power lines are added to the blank area of the wiring layer adjacent to the signal line; in this way, large-scale manual modification of the integrated circuit (Engineer Changing Order, ECO) will not occur, and without affecting the chip performance, by increasing the current path from the power supply point to the device in the deployed power network, the resistance voltage drop of the power network can be reduced, thereby improving the chip calculation speed.

[0041] Step 403: Add at least one power line in the wiring layer adjacent to the wiring layer where the signal line is located to increase the current path from the power supply point to the device, thereby reducing the resistance voltage drop of the deployed power network.

[0042] In some embodiments, the electronic device can implement Step 403 as follows: determine the target power line that meets the conditions among the power lines of the power network in the adjacent wiring layer; and deploy at least one other power line in parallel with the target power line.

[0043] The conditions can be various. For example, the condition can be that the resistance value is greater than the resistance threshold or the length is greater than the length threshold. That is, in some embodiments, the electronic device can determine the target power line as follows: determine the resistance value of each power line of the power network in the adjacent wiring layer; determine the power line with a resistance value greater than the resistance threshold as the target power line; and / or determine the length of each power line of the power network in the adjacent wiring layer; determine the power line with a length greater than the length threshold as the target power line.

[0044] It can be understood that the greater the resistance value of the power line, the greater the resistance voltage drop generated by it. The longer the power line, the greater its resistance value, and correspondingly, the greater the resistance voltage drop generated by it. In view of this, in some embodiments, only the parallel segments of the power lines with a resistance value greater than the resistance threshold and / or the parallel segments of the power lines with a length greater than the length threshold are deployed, rather than deploying the parallel segments of each power line; in this way, even if the parallel segments of each power line are not deployed, the resistance voltage drop of the deployed power network can be effectively reduced, thereby shortening the chip configuration cycle while reducing the resistance voltage drop of the power network.

[0045] In the embodiments of the present application, the current path is increased by paralleling power supply lines. In this way, without modifying the original power supply network, new power supply lines are paralleled on the basis of the original network to change the current path from the power supply point to the device. It can be seen that this optimization method is simple and easy to implement, and while shortening the chip configuration cycle, it can reduce the resistance voltage drop of the power supply network of the functional unit.

[0046] For the adjacent wiring layer (i.e., the neighboring wiring layer) of the signal line in the channel, paralleled power supply lines are added to shorten the current path from the power supply point to the device. Here, the technical effects obtained are illustrated by examples with reference to the accompanying drawings. As Figure 5 shown, taking the power supply point A0 in the deployed power supply network as an example, as Figure 5 shown, the current path from the power supply point A0 to the bottom device D0 includes the line segment A0B0 on the wiring layer 501, the line segment B0C0 on the wiring layer 502, and the line segment C0D0 on the wiring layer 503; if line segments B1C1 and B2C2 are added in the blank area of the wiring layer 502, then the current path from the power supply point A0 to the bottom device D0 not only includes the above-mentioned original deployed path, but also includes the paths (A0A1 + B1C1 + D1D0) and (A0A2 + B2C2 + D2D0); obviously, among these three paths, the path (A0A1 + B1C1 + D1D0) is the shortest, and correspondingly, the generated resistance voltage drop is the lowest.

[0047] It can be understood that the resistance voltage drop refers to the resistance voltage drop of the metal wire from the power supply point to the device. The larger this voltage drop, the smaller the voltage reaching the device from the power supply point (i.e., the voltage triggering the device to work); and the smaller the voltage triggering the device to work, the slower the working speed of the device. For example, the turn-on speed of a metal oxide semiconductor field effect (MOS) transistor is slower, and correspondingly, the computing speed of the chip is slower.

[0048] Ideally, we hope that the voltage at the power supply point remains unchanged after reaching the device. In fact, due to the resistance of the metal wire between the power supply point and the device, that is, the resistance voltage drop, the voltage at the power supply point becomes smaller after reaching the device, thereby slowing down the turn-on speed of the device. Therefore, in the embodiments of the present application, by increasing the current path from the power supply point of the deployed power supply network to the device, the possibility of shortening the current path between the two is increased, so that the equivalent resistance between the two becomes smaller, so as to achieve the purpose of reducing the resistance voltage drop between the two, and further improve the computing speed of the chip.

[0049] The embodiments of the present application further provide a method for configuring a chip. Figure 6 As shown in the schematic flowchart of the implementation process of another method for configuring a chip provided by the embodiments of the present application, as Figure 6 shown, the method may include the following steps 601 to step 606:

[0050] Step 601: Obtain the layout data of the chip layout that meets the manufacturing submission standards;

[0051] Step 602: Determine the wiring layer where the signal line is located from the layout data.

[0052] In some embodiments, a reasonable wiring sequence should be: first deploy the global power network (i.e., the power network before enhancement), then deploy the global signal network; finally, locally add some power lines according to the actual situation. In this way, without introducing ECO, the resistance voltage drop of the chip can be reduced and the chip performance can be improved. It can be seen that in the embodiments of the present application, enhancing the power network based on the chip layout can meet the requirements of the above wiring sequence.

[0053] Step 603: Determine the resistance value of each power line in the power network in the wiring layer adjacent to the wiring layer where the signal line is located.

[0054] In some embodiments, the electronic device can implement Step 603 as follows: determine the length and cross-sectional area of each power line; according to the length and cross-sectional area of each power line, determine the resistance value of the corresponding power line.

[0055] It can be understood that for different devices, the line width required to connect to the power supply point may be different. The larger the line width, the smaller its resistance value, and the smaller the corresponding resistance voltage drop. Even if the line connected to the power supply point is long, it may not need to be widened. Therefore, in this embodiment, based on the length and cross-sectional area of the power line, the resistance value of the power line is determined. In this way, the power lines that actually need to be processed can be selected, so that by configuring parallel segments of fewer power lines, the resistance voltage drop of the deployed power network can also be effectively reduced, and thus the chip configuration cycle can be shortened.

[0056] Step 604: Determine the power lines with resistance values greater than the resistance threshold as the target power lines.

[0057] In some embodiments, the electronic device can also determine the target power lines as follows: determine the length of each power line in the power network in the adjacent wiring layer; determine the power lines with lengths greater than the length threshold as the target power lines.

[0058] Step 605: Deploy at least one other power line parallel to the target power line in the wiring layer adjacent to the wiring layer where the signal line is located;

[0059] Step 606: Add vias at the endpoints of the other power lines to connect the other power lines to the power lines that are in the adjacent wiring layer to the wiring layer of the other power lines and perpendicular to the target power line, so that the other power lines are connected in parallel with the target power line; in this way, the current path from the power supply point to the device in the deployed power network can be increased, thereby reducing the resistance voltage drop of the deployed power network.

[0060] It can be understood that in a chip, the wiring direction of each layer is unchanged, and the wiring directions of adjacent two layers are perpendicular. For example, Figure 2 As shown, the wiring direction of the Mn-th layer 202 is longitudinal, and the wiring directions of the adjacent upper and lower two layers, namely the Mn-1-th layer 201 and the Mn+1-th layer 203, are transverse. Therefore, in the embodiment of the present application, adding vias at the endpoints of the other power lines can realize the connection of the power line to the power lines in its upper and lower adjacent two layers and perpendicular to the target power line, so that the other power lines are connected in parallel with the target power line.

[0061] For example, Figure 5 As shown, the target power line is the line segment B0C0, and the newly added other power lines are the line segments B1C1 and B2C2. By drilling holes at the endpoints of the line segments B1C1 and B2C2, these two line segments can be connected to the line segments A0B0 and C0D0 on the upper and lower adjacent wiring layers and perpendicular to the line segment B0C0, so as to realize the parallel connection of the line segments B1C1, B2C2 and the line segment B0C0.

[0062] Next, the exemplary application of the embodiment of the present application in a practical application scenario will be described.

[0063] The metal layer with low wiring resource utilization rate in the channel can be optimized, and sufficient power supply metal can be added in advance to enhance the power network, so as to achieve the purpose of reducing the resistance voltage drop. It can be understood that before the metal lines in the channel are deployed, if the signal lines have been laid out in the channel area, adding metal lines for the power network at this time may conflict with the metal lines in the channel. Therefore, in order to prevent the power lines from conflicting with the signal lines in the channel, the power lines can be deployed first, and then the signal lines in the channel can be deployed.

[0064] In some embodiments, the implementation steps may include the following steps 1) to 3):

[0065] Step 1): Design a normal power network;

[0066] It can be understood that a normal power network refers to a power network that can meet the basic resistance voltage drop requirements, such as a power network that meets a 5% voltage drop.

[0067] In some embodiments, a reasonable wiring sequence should be as follows: first, deploy the global power network (i.e., the power network before enhancement); then, deploy the signal lines; finally, add some additional power lines according to the actual situation. Generally speaking, the deployed global power network can basically meet the requirements of resistance voltage drop. For example, if the resistance voltage drop of the deployed global power network is 5%, it can meet the basic requirements of the chip. However, the channel characteristics are likely to cause a relatively large resistance voltage drop. Then, for the channel characteristics, enhancing the power network can reduce the resistance voltage drop to 3%, or even 2%, which greatly reduces the probability of the chip malfunctioning and thus effectively improves the chip performance.

[0068] For example, there is 100% of the wiring resources. According to the requirements, 10% of the wiring resources are reserved for the power network, and 90% of the wiring resources are reserved for the signal lines. However, due to the characteristics of the channel itself, even if 90% of the signal line resources are given to the channel area, they cannot be fully utilized. Maybe only 45% of the wiring resources are used for the deployment of the signal lines, so the remaining 45% of the wiring resources are empty and not utilized. Then, the remaining 45% of the wiring resources can be used for the deployment of the power lines, that is, 55% of the wiring resources are used to deploy the power network, thereby enhancing the power network and reducing the resistance voltage drop of the chip.

[0069] Step 2) Add additional power networks in a specific layer for channels with different characteristics to meet the requirements of the Design Rule Check (DRC) of the chip physical implementation design. For example Figure 7 As shown, assuming that the signal lines of the horizontal channel run on the Mn layer, sufficient power networks can be added in the Mn - 1 and Mn + 1 layers within the channel.

[0070] Step 3) Continue with placement and routing to complete other tasks of the physical design.

[0071] For the chip design itself, the power network design in the channel area is inherently difficult. In other words, the power network in the channel area is likely to cause a relatively large resistance voltage drop. In the embodiments of the present application, the blank areas in the channel that are not wired are fully utilized to enhance the power network; thus, without occupying the wiring resources and without increasing the chip area, by effectively enhancing the power network in the channel, the risk of resistance voltage drop is reduced, and the problem that the power network in the channel area is likely to cause a relatively large resistance voltage drop is overcome.

[0072] Based on the foregoing embodiments, an apparatus for configuring a chip provided by an embodiment of the present application includes each module included therein, as well as each unit included in each module, and can be implemented by a processor in an electronic device; of course, it can also be implemented by specific logic circuits; during implementation, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0073] Figure 8 It is a schematic structural diagram of the apparatus for configuring a chip according to an embodiment of the present application, as Figure 8 shown, the apparatus 80 includes a determination module 801 and an enhancement module 802; wherein,

[0074] The determination module 801 is configured to determine the wiring layer where the signal line is located;

[0075] The enhancement module 802 is configured to increase the current path from the power supply point in the power supply network to the device in the wiring layer adjacent to the wiring layer where the signal line is located, so as to reduce the resistance voltage drop of the power supply network.

[0076] In some embodiments, the enhancement module 802 is configured to: add at least one power line in the wiring layer adjacent to the wiring layer where the signal line is located, so as to increase the current path from the power supply point to the device.

[0077] In some embodiments, the enhancement module 802 is configured to: determine a target power line that meets the conditions among the power lines of the power supply network in the adjacent wiring layer; and deploy at least one other power line in parallel with the target power line.

[0078] In some embodiments, the enhancement module 802 is configured to: determine the resistance value of each power line of the power supply network in the adjacent wiring layer; determine the power line with a resistance value greater than the resistance threshold as the target power line; and / or, determine the length of each power line of the power supply network in the adjacent wiring layer; determine the power line with a length greater than the length threshold as the target power line.

[0079] In some embodiments, the enhancement module 802 is configured to: determine the length and cross-sectional area of each power line; determine the resistance value of the power line according to the length and cross-sectional area of each power line.

[0080] In some embodiments, the enhancement module 802 is configured to: add vias at the endpoints of the other power lines, so that the other power lines are connected to the power lines located in the wiring layer adjacent to the wiring layer of the other power lines and perpendicular to the target power line, so that the other power lines are in parallel with the target power line.

[0081] In some embodiments, a determining module 801 is configured to: obtain layout data of a chip layout that meets the manufacturing submission standard; and determine the wiring layer where a signal line is located from the layout data.

[0082] The description of the above device embodiments is similar to that of the above method embodiments and has similar beneficial effects to those of the method embodiments. For the technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0083] It should be noted that in the embodiments of the present application Figure 8 The division of modules of the device for configuring a chip shown is illustrative, merely a logical function division, and there may be other division methods in actual implementation. In addition, in each embodiment of the present application, each functional unit may be integrated in a processing unit, may exist separately physically, or two or more units may be integrated in one unit. The above integrated unit may be implemented in the form of hardware, or in the form of a software functional unit, or in the form of a combination of software and hardware.

[0084] Correspondingly, as Figure 9 shown, an electronic device 90 provided in an embodiment of the present application may include: a memory 901 and a processor 902. The memory 901 stores a computer program that can run on the processor 902, and when the processor 902 executes the program, it implements the steps in the method provided in the above embodiments.

[0085] The memory 901 is configured to store instructions and applications executable by the processor 902, and can also cache data to be processed or already processed by the processor 902 and each module in the electronic device 90 (for example, image data, audio data, voice communication data, and video communication data), and can be implemented by flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0086] It should be noted that in the embodiments of the present application, if the above method for configuring a chip is implemented in the form of software functional modules and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence or the part that contributes to the related art, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), magnetic disks, or optical discs that can store program codes. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0087] The embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the method for configuring a chip provided in the above embodiments are implemented.

[0088] The embodiments of the present application provide a computer program product containing instructions. When it runs on a computer, it causes the computer to execute the method for configuring a chip provided in the above method embodiments.

[0089] It should be pointed out here that: the descriptions of the above storage medium and device embodiments are similar to the descriptions of the above method embodiments and have beneficial effects similar to those of the method embodiments. For the technical details not disclosed in the embodiments of the storage medium, chip, and terminal device of the present application, please refer to the descriptions of the method embodiments of the present application for understanding.

[0090] It should be understood that the "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that the specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" or "in some embodiments" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the sequence numbers of the above processes do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The sequence numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0091] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0092] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments of the touch screen system described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or modules can be electrical, mechanical or other forms.

[0093] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules; they may be located in one place or distributed across multiple network units; some or all of the modules may be selected according to actual needs to achieve the purpose of this embodiment.

[0094] In addition, all functional modules in the embodiments of the present application can be integrated into one processing unit, or each module can be a separate unit, or two or more modules can be integrated into one unit; the above-mentioned integrated modules can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0095] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0096] Alternatively, if the above integrated units of the present application are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence or the part that contributes to the related art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media such as removable storage devices, ROMs, magnetic disks, or optical discs that can store program codes.

[0097] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0098] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0099] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0100] As described above, the above are only the implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for configuring a chip, characterized in that, The method includes: Determining the wiring layer where the signal line is located; and Determining a target power line that meets the conditions among the power lines of the power network in the wiring layer adjacent to the wiring layer where the signal line is located; and deploying at least one other power line in parallel with the target power line to increase the current path from the power supply point to the device in the power network and reduce the resistance voltage drop of the power network; wherein the at least one other power line and the target power line are in the same wiring layer; Wherein, determining a target power line that meets the conditions among the power lines of the power network in the wiring layer adjacent to the wiring layer where the signal line is located includes: Determining the resistance value of each power line of the power network in the adjacent wiring layer; determining the power lines with resistance values greater than the resistance threshold as the target power lines; and / or Determining the length of each power line of the power network in the adjacent wiring layer; determining the power lines with lengths greater than the length threshold as the target power lines.

2. The method according to claim 1, wherein The determining the resistance value of each power line of the power network in the adjacent wiring layer includes: Determining the length and cross-sectional area of each power line; Determining the resistance value of the power line according to the length and cross-sectional area of each power line.

3. The method according to claim 1, characterized in that, The deploying at least one other power line in parallel with the target power line includes: Adding vias at the endpoints of the other power line to connect the other power line to the power line in the wiring layer adjacent to the wiring layer of the other power line and perpendicular to the target power line, so that the other power line is in parallel with the target power line.

4. The method according to any one of claims 1 to 3, characterized in that, The determining the wiring layer where the signal line is located includes: Obtaining the layout data of the chip layout that meets the manufacturing submission standards; Determining the wiring layer where the signal line is located from the layout data.

5. A device for configuring a chip, characterized in that, Includes: A determining module for determining the wiring layer where the signal line is located; An enhancing module for determining a target power line that meets the conditions among the power lines of the power network in the wiring layer adjacent to the wiring layer where the signal line is located; and deploying at least one other power line in parallel with the target power line to increase the current path from the power supply point to the device in the power network and reduce the resistance voltage drop of the power network; wherein the at least one other power line and the target power line are in the same wiring layer; Wherein, determining a target power line that meets the conditions among the power lines of the power network in the wiring layer adjacent to the wiring layer where the signal line is located includes: Determining the resistance value of each power line of the power network in the adjacent wiring layer; determining the power lines with resistance values greater than the resistance threshold as the target power lines; and / or Determining the length of each power line of the power network in the adjacent wiring layer; determining the power lines with lengths greater than the length threshold as the target power lines.

6. An electronic device, comprising a memory and a processor, the memory storing a computer program that can run on the processor, characterized in that, When the processor executes the program, the method according to any one of claims 1 to 4 is implemented.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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