Integrated circuit, design method and design device thereof, electronic device and storage medium

Abstract

An integrated circuit, a design method and a design device thereof, an electronic device and a storage medium, the design method comprising: obtaining an initial design scheme of the integrated circuit; and obtaining an application design scheme of the integrated circuit based on the initial design scheme; in the initial design scheme, the integrated circuit comprises a first conductive part and a second conductive part, the first conductive part comprises a plurality of first sub-parts located in different conductive layers, and the second conductive part comprises a plurality of second sub-parts located in different conductive layers; the first conductive part and the second conductive part are both at least through a first adjacent conductive layer and a second adjacent conductive layer; in a stacking direction of the conductive layers, the first sub-parts in the first adjacent conductive layer and the first sub-parts and the second sub-parts in the second adjacent conductive layer are all overlapped, and the second sub-parts in the first adjacent conductive layer and the first sub-parts and the second sub-parts in the second adjacent conductive layer are all overlapped. The design method helps to save the research and development cost of obtaining the application design scheme based on the initial design scheme.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a design method of an integrated circuit, an integrated circuit design apparatus, an integrated circuit, an electronic device, and a storage medium. BACKGROUND

[0002] At present, with the continuous development and progress of chip process technology, high speed, high integration, low power consumption and low cost have become the main development direction of the integrated circuit industry, and the performance requirements of the market for chip products have also been improved accordingly, so the design scale and complexity of the chip have also been greatly increased. SUMMARY

[0003] At least one embodiment of the present disclosure provides a design method of an integrated circuit, the design method comprising: obtaining an initial design scheme of an integrated circuit; and obtaining an application design scheme of the integrated circuit based on the initial design scheme; the integrated circuit comprises a plurality of conductive layers, the plurality of conductive layers are arranged in a stacked manner, at least one insulating layer is arranged between each two adjacent conductive layers to separate and insulate the two adjacent conductive layers from each other; in the initial design scheme, the integrated circuit comprises a first conductive part and a second conductive part which are insulated from each other, the first conductive part comprises a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between the different conductive layers to connect the plurality of first sub-parts, the second conductive part comprises a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between the different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part in the first adjacent conductive layer and the first sub-part and the second sub-part in the second adjacent conductive layer at least partially overlap, and the second sub-part in the first adjacent conductive layer and the first sub-part and the second sub-part in the second adjacent conductive layer at least partially overlap.

[0004] The at least one embodiment of the present disclosure also provides an integrated circuit, which comprises a plurality of conductive layers; the plurality of conductive layers are arranged in a stack, and at least one insulating layer is arranged between each two adjacent conductive layers to separate and insulate the two adjacent conductive layers; the integrated circuit comprises a first conductive part and a second conductive part which are insulated from each other, the first conductive part comprises a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between the different conductive layers to connect the plurality of first sub-parts, and the second conductive part comprises a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between the different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part in the first adjacent conductive layer at least partially overlaps the first sub-part and the second sub-part in the second adjacent conductive layer, and the second sub-part in the first adjacent conductive layer at least partially overlaps the first sub-part and the second sub-part in the second adjacent conductive layer.

[0005] The at least one embodiment of the present disclosure further provides an integrated circuit design apparatus, which comprises an initial design scheme acquisition unit and an application design scheme acquisition unit; the initial design scheme acquisition unit is configured to acquire an initial design scheme of an integrated circuit; the application design scheme acquisition unit is configured to obtain an application design scheme of the integrated circuit based on the initial design scheme; the integrated circuit comprises a plurality of conductive layers, the plurality of conductive layers are arranged in a stacked manner, at least one insulating layer is arranged between each two adjacent conductive layers, so that the two adjacent conductive layers are spaced apart and insulated from each other; in the initial design scheme, the integrated circuit comprises a first conductive part and a second conductive part which are insulated from each other, the first conductive part comprises a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between the different conductive layers to connect the plurality of first sub-parts, the second conductive part comprises a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between the different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part in the first adjacent conductive layer and the first sub-part and the second sub-part in the second adjacent conductive layer at least partially overlap, and the second sub-part in the first adjacent conductive layer and the first sub-part and the second sub-part in the second adjacent conductive layer at least partially overlap.

[0006] The at least one embodiment of the present disclosure further provides an electronic device, which comprises a memory and a processor; the memory non-transitorily stores computer executable instructions; the processor is configured to run the computer executable instructions, and the computer executable instructions, when run by the processor, implement the design method of the integrated circuit according to any embodiment of the present disclosure.

[0007] The at least one embodiment of the present disclosure further provides a non-transitory computer readable storage medium, which stores computer executable instructions, and the computer executable instructions, when executed by a processor, implement the design method of the integrated circuit according to any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0009] Figure 1A schematic flow chart of a design method of an integrated circuit provided for some embodiments of the present disclosure;

[0010] Figure 2 A schematic diagram of an initial design scheme of an integrated circuit provided for some embodiments of the present disclosure;

[0011] Figure 3 A schematic diagram of an initial design scheme of an integrated circuit and application of the design scheme provided for some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram of an initial design scheme of an integrated circuit and application of the design scheme provided for some embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram of a specific implementation example of an initial design scheme of an integrated circuit provided for some embodiments of the present disclosure;

[0014] Figure 6A A schematic diagram of a specific implementation example of an initial design scheme of an integrated circuit provided for some embodiments of the present disclosure; Figure 5 A planar schematic diagram of a first adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0015] A planar schematic diagram of a second adjacent conductive layer in Figure 6B A planar schematic diagram of a second adjacent conductive layer in Figure 5 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0016] A planar schematic diagram of a second adjacent conductive layer in Figure 6C A planar schematic diagram of a second adjacent conductive layer in Figure 5 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0017] A planar schematic diagram of a second adjacent conductive layer in Figure 7 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0018] A planar schematic diagram of a second adjacent conductive layer in Figure 8 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0019] A planar schematic diagram of a second adjacent conductive layer in Figure 9 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0020] A planar schematic diagram of a second adjacent conductive layer in Figure 10 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0021] A planar schematic diagram of a second adjacent conductive layer in Figure 11 A planar schematic diagram of a second adjacent conductive layer in A planar schematic diagram of a second adjacent conductive layer in

[0022] A planar schematic diagram of a second adjacent conductive layer in Figure 12A A planar schematic diagram of a second adjacent conductive layer in Figure 11a plan view of the first adjacent conductive layer in the integrated circuit;

[0023] Figure 12B is Figure 11 a plan view of the second adjacent conductive layer in the integrated circuit;

[0024] Figure 12C is Figure 11 a plan view of the third adjacent conductive layer in the integrated circuit;

[0025] Figure 12D is Figure 11 a plan view of the fourth adjacent conductive layer in the integrated circuit;

[0026] Figure 11 is Figure 12A to Figure 12D a schematic view of a layout of vias in the same insulating layer in the design scheme of the integrated circuit shown in FIG. 1;

[0027] Figure 11 is a schematic view of the setting positions of input interfaces and output interfaces of a first signal and a second signal in an initial design scheme of an integrated circuit provided by some embodiments of the present disclosure;

[0028] Figure 12A to Figure 12D is a schematic view of another specific example of an initial design scheme of an integrated circuit provided by some embodiments of the present disclosure;

[0029] Figure 12A is a schematic block diagram of an integrated circuit design apparatus provided by some embodiments of the present disclosure;

[0030] Figure 11 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;

[0031] Figure 12A to Figure 12D is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure; and

[0032] Figure 12A to Figure 12D is a schematic view of a storage medium provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0034] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms are used herein merely to distinguish one element from another, and are not intended to imply any order or sequence. Also, the terms "a", "an", or "the" are not limited to refer to only one of an element but are intended to cover both single and plural instances. The terms "including", "comprising", or "having" and the like are inclusive and are intended to cover any and all members, whether specific or similar, without excluding other elements or methods. The terms "connected" or "coupled" are not limited to direct or physical connections, but can include indirect or wireless connections, whether or not between different parts of the same element or between different elements. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and can change accordingly when the absolute positions of the described objects are changed.

[0035] With the rapid development of the integrated circuit industry, the scale and complexity of circuit design are increasing. In the development process of integrated circuits, it is often necessary to modify the original circuit layout designed to meet different practical application requirements or solve possible problems in circuit design. However, in the case of large-scale integrated circuit design and complex layout design, the above modification process may often require changes to the layout design of multiple film layers in the integrated circuit, which is a large amount of change and often takes a lot of time, and may also require new mask plates for preparing the multiple film layers, thereby greatly increasing the development cost.

[0036] At least one embodiment of this disclosure provides a design method for an integrated circuit, comprising: obtaining an initial design scheme for the integrated circuit; and obtaining an application design scheme for the integrated circuit based on the initial design scheme; the integrated circuit includes multiple conductive layers, which are stacked on top of each other, and at least one insulating layer is disposed between every two adjacent conductive layers to make the two adjacent conductive layers spaced apart and insulated from each other; in the initial design scheme, the integrated circuit includes a first conductive portion and a second conductive portion that are insulated from each other, the first conductive portion including multiple first sub-parts respectively located in different conductive layers and a first connecting portion located between different conductive layers to connect the multiple first sub-parts, the second conductive portion including... The first conductive layer comprises a plurality of second sub-parts located in different conductive layers and a second connecting portion located between different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers include an adjacent first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part in the first adjacent conductive layer and the first sub-part and the second sub-part in the second adjacent conductive layer at least partially overlap, and the second sub-part in the first adjacent conductive layer and the first sub-part and the second sub-part in the second adjacent conductive layer at least partially overlap.

[0037] The integrated circuit design method provided in the above embodiments of this disclosure can be applied to the design and development of integrated circuits with different circuit structures or different layout designs, such as chip design and chip development.

[0038] In the integrated circuit design method provided in the above embodiments of this disclosure, by designing the first sub-part of the first adjacent conductive layer to at least partially overlap with both the first and second sub-parts of the second adjacent conductive layer in the initial design scheme of the provided integrated circuit, and by designing the second sub-part of the first adjacent conductive layer to at least partially overlap with both the first and second sub-parts of the second adjacent conductive layer, the number of conductive and insulating layers that need to be modified in the integrated circuit can be reduced when adjustments or modifications are required to the connection method between the first sub-part and the first connecting part in the first conductive part and the connection method between the second sub-part and the second connecting part in the second conductive part. Furthermore, the amount of modification and time required in adjusting or modifying the layout structure based on the initial design scheme of the integrated circuit to obtain the application design scheme can be reduced, thereby reducing the R&D cost of the integrated circuit and improving R&D efficiency.

[0039] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0040] Figure 12A A schematic flowchart of a design method of an integrated circuit provided for some embodiments of the present disclosure, Figure 12C A schematic diagram of an initial design scheme of an integrated circuit provided for some embodiments of the present disclosure.

[0041] In combination Figure 12B and Figure 12D , the design method of the integrated circuit provided by the embodiments of the present disclosure includes steps S11 and S12.

[0042] Step S11: obtaining an initial design scheme of an integrated circuit.

[0043] Step S12: obtaining an application design scheme of the integrated circuit based on the initial design scheme.

[0044] Taking the initial design scheme of the integrated circuit shown in Figure 12A as an example, the integrated circuit includes a plurality of conductive layers and a plurality of insulating layers, the plurality of conductive layers for example including Figure 12C the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the third adjacent conductive layer 103 shown in Figure 12B , and the plurality of insulating layers for example including the first insulating layer 111 located between the first adjacent conductive layer 101 and the second adjacent conductive layer 102 and the second insulating layer 112 located between the second adjacent conductive layer 102 and the third adjacent conductive layer 103 shown in

[0045] . Figure 12D As shown in , the plurality of conductive layers are arranged in a stacked manner, and an insulating layer is arranged between every two adjacent conductive layers to separate and insulate the two adjacent conductive layers. For example, the first adjacent conductive layer 101 and the second adjacent conductive layer 102 can be two adjacent conductive layers, or the second adjacent conductive layer 102 and the third adjacent conductive layer 103 can also be two adjacent conductive layers. Taking the first adjacent conductive layer 101 and the second adjacent conductive layer 102 as an example, the first adjacent conductive layer 101 and the second adjacent conductive layer 102 are arranged in a stacked manner in the direction R1, that is, the direction R1 is the stacking direction of the first adjacent conductive layer 101 and the second adjacent conductive layer 102; the first insulating layer 111 is located between the first adjacent conductive layer 101 and the second adjacent conductive layer 102 to separate and insulate the first adjacent conductive layer 101 and the second adjacent conductive layer 102.

[0046] It should be noted that the embodiments of the present disclosure take the initial design scheme of the integrated circuit shown in Figure 12C as an example to describe the design method of the integrated circuit provided by the embodiments of the present disclosure, but the embodiments of the present disclosure include but are not limited to this. For example, in Figure 12AThe initial design of the integrated circuit shown in the figure shows three conductive layers and two insulating layers respectively located between two adjacent conductive layers, that is, the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the third adjacent conductive layer 103, and the first insulating layer 111 and the second insulating layer 112; while in some other embodiments of the present disclosure, the number of conductive layers in the initial design of the integrated circuit can also be 2, 4, 5 or more, and accordingly, the number of insulating layers can also be 1, 3, 4 or more, and the number of insulating layers between two adjacent conductive layers can also be 2, 3, 4 or more, etc., and the embodiments of the present disclosure do not make specific limitations on this.

[0047] As shown in the figure, Figure 12D In this initial design, the integrated circuit includes a first conductive part 130 and a second conductive part 140 which are insulated from each other. The first conductive part 130 includes a plurality of first sub-parts 131 respectively located in different conductive layers and a first connecting part 132 located between different conductive layers to connect the plurality of first sub-parts 131, for example, the first connecting part 132 at least penetrates the insulating layer located between the different conductive layers. The second conductive part 140 includes a plurality of second sub-parts 141 respectively located in different conductive layers and a second connecting part 142 located between different conductive layers to connect the plurality of second sub-parts 141, for example, the second connecting part 142 at least penetrates the insulating layer located between the different conductive layers.

[0048] For example, for the above step S11, the first conductive part 130 and the second conductive part 140 are connected by the first connecting part 132 and the second connecting part 142, and the first conductive part 130 and the second conductive part 140 are connected by the first connecting part 132 and the second connecting part 142. Figure 12BIn the initial design scheme of the integrated circuit 10, the first conductive part 130 at least passes through the first adjacent conductive layer 101 and the second adjacent conductive layer 102, for example, the first conductive part 130 at least includes a first sub-part 131 in the first adjacent conductive layer 101 and a first sub-part 131 in the second adjacent conductive layer 102; the second conductive part 140 at least passes through the first adjacent conductive layer 101 and the second adjacent conductive layer 102, for example, the second conductive part 140 at least includes a second sub-part 141 in the first adjacent conductive layer 101 and a second sub-part 141 in the second adjacent conductive layer 102; in the stacking direction R1 of the first adjacent conductive layer 101 and the second adjacent conductive layer 102, the first sub-part 131 in the first adjacent conductive layer 101 overlaps with the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102, and the second sub-part 141 in the first adjacent conductive layer 101 overlaps with the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102; that is, in the stacking direction R1, the first sub-part 131 in the second adjacent conductive layer 102 overlaps with the first sub-part 131 and the second sub-part 141 in the first adjacent conductive layer 101, and the second sub-part 141 in the second adjacent conductive layer 102 overlaps with the first sub-part 131 and the second sub-part 141 in the first adjacent conductive layer 101.

[0049] Therefore, in the case of meeting the initial design scheme that the first sub-part 131 in the first adjacent conductive layer 101 is designed to overlap with the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 in the stacking direction R1, and the second sub-part 141 in the first adjacent conductive layer 101 is also designed to overlap with the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 in the stacking direction R1, the number of conductive layers and insulating layers that need to be changed in the integrated circuit can be reduced to obtain the required application design scheme based on Figure 12E According to the initial design scheme, the number of conductive layers and insulating layers that need to be changed in the integrated circuit can be reduced to obtain the required application design scheme according to actual different design or application requirements, for example, when the connection mode of the first conductive part 130 and the second conductive part 140 needs to be adjusted or modified. Further, the amount of change and the time required in the process of obtaining the application design scheme based on the initial design scheme can be reduced, and the number of new mask plates that need to be redesigned or prepared can also be reduced, thereby reducing the research and development cost of the integrated circuit and improving the research and development efficiency.

[0050] For example, the obtained new application design scheme can also continue to meet the corresponding setting conditions for the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the first insulating layer 111 in the initial design scheme, that is, the application design scheme can be the same as the initial design scheme. For example, the application design scheme can include that in the stacking direction R1, the first sub-part 131 in the first adjacent conductive layer 101 and the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 all overlap, and the second sub-part 141 in the first adjacent conductive layer 101 and the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 all overlap.

[0051] Therefore, in subsequent design, the obtained application design scheme can continue to be adjusted as a new initial design scheme according to different actual needs in the case of needing to continue to make changes based on the obtained application design scheme to obtain a new design scheme. Further, the amount of changes and the time required in the process of making multiple changes based on the initial design scheme can be reduced, and the number of corresponding new mask plates that need to be redesigned or prepared is reduced, thereby further reducing the research and development cost of integrated circuits and improving the research and development efficiency.

[0052] For example, the application design scheme can also include the same or similar conditions as other settings for the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the first insulating layer 111 in the initial design scheme. For specific content, please refer to the corresponding description of the initial design scheme, and the repeated parts will not be described again.

[0053] For example, the first sub-part 131 and the second sub-part 141 in the first adjacent conductive layer 101 are spaced apart and insulated from each other and are centrally symmetrically arranged with respect to the first reference point N1. The first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 are spaced apart and insulated from each other and are centrally symmetrically arranged with respect to the second reference point N2.

[0054] It should be noted that, in order to clearly show the relative positions and overlapping relationships of the first sub-part 131 and the second sub-part 141 in different conductive layers in the stacking direction R1, Figure 11 The first sub-part 131 and the second sub-part 141 located in the same layer in the initial design scheme shown are only divided by the "S" type curve, but it should be understood that Figure 12E The first sub-part 131 and the second sub-part 141 located in the same layer in the initial design scheme shown are spaced apart and insulated from each other, and the specific layout implementation manner can also be referred to the subsequent description of the first sub-part 131 and the second sub-part 141 in the same layer in the application design scheme. Figure 11 and Figure 12EThe corresponding description in the specific example shown.

[0055] It should be noted that the first reference point N1 and the second reference point N2 mentioned above and other reference points mentioned hereinafter, etc. (for example, the third reference point N3, the fourth reference point N4, and the fifth reference point N5) are only for clearly illustrating the corresponding positional relationship, and are not actually present in the actual structure of the integrated circuit.

[0056] As shown in Figure 12A to Figure 12D For the first insulating layer 111 located between the first adjacent conductive layer 101 and the second adjacent conductive layer 102, the first insulating layer 111 includes a first via H1 and a second via H2, the first via H1 and the second via H2 penetrate through the first insulating layer 111 and are respectively used to set the first connection part 132 and the second connection part 142. For example, in Figure 11 In the initial design scheme shown in

[0057] For example, the number of the first vias H1 is the same as the number of the second vias H2. It should be noted that in Figure 12A to Figure 12E In the embodiment shown in

[0058] The first reference point N1, the second reference point N2, and the third reference point N3 overlap with each other in the layer stacking direction R1 of the first adjacent conductive layer 101 and the second adjacent conductive layer 102, that is, the first reference point N1, the second reference point N2, and the third reference point N3 are located on the same straight line extending along the layer stacking direction R1. Therefore, it can not only help to reduce the amount of changes required to be made in each conductive layer and insulating layer in the process of obtaining a new application design scheme based on the initial design scheme, but also reduce the layout space required to be occupied by the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111 as a whole in the integrated circuit, thereby facilitating the optimization of the structural design of the integrated circuit.

[0059] For example, in Figure 12EIn the illustrated embodiment, the third adjacent conductive layer 103 is located on the side of the second adjacent conductive layer 102 away from the first adjacent conductive layer 101. The first conductive portion 130 and the second conductive portion 140 also pass through the third adjacent conductive layer 103, i.e., the first conductive portion 130 further includes a first sub-portion 131 located in the third adjacent conductive layer 103, and the second conductive portion 140 further includes a second sub-portion 141 located in the third adjacent conductive layer 103. In the stacking direction R1 of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103, the first sub-portion 131 in the second adjacent conductive layer 102 overlaps the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103, and the second sub-portion 141 in the second adjacent conductive layer 102 overlaps the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103, i.e., the first sub-portion 131 in the third adjacent conductive layer 103 overlaps the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102, and the second sub-portion 141 in the third adjacent conductive layer 103 overlaps the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102.

[0060] For example, the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103 are spaced apart and insulated from each other and are centrally symmetric with respect to the fourth reference point N4. For the second insulating layer 112 located between the second adjacent conductive layer 102 and the third adjacent conductive layer 103, the second insulating layer 112 includes a third via hole H3 and a fourth via hole H4, which pass through the second insulating layer 112 and are used to arrange the first connecting portion 132 and the second connecting portion 142. For example, in the illustrated embodiment, the third via hole H3 is used to arrange the first connecting portion 132, and the fourth via hole H4 is used to arrange the second connecting portion 142. Figure 12E In the illustrated initial design scheme, the third via hole H3 is used to arrange the first connecting portion 132, and the fourth via hole H4 is used to arrange the second connecting portion 142. The third via hole H3 and the fourth via hole H4 are centrally symmetric with respect to the fifth reference point N5, i.e., the third via hole H3 and the fourth via hole H4 are located on the same straight line passing through the fifth reference point N5. The first reference point N1, the second reference point N2, the third reference point N3, the fourth reference point N4, and the fifth reference point N5 overlap each other in the stacking direction R1, i.e., the first reference point N1, the second reference point N2, the third reference point N3, the fourth reference point N4, and the fifth reference point N5 are located on the same straight line extending along the stacking direction R1.

[0061] The above specific arrangements and connection modes of the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 and the third adjacent conductive layer 103 can refer to the corresponding descriptions of the first adjacent conductive layer 101 and the second adjacent conductive layer 102 in the foregoing description, and repeated descriptions are omitted herein.

[0062] For example, the number of third vias H3 and the number of fourth vias H4 are the same. It should be noted that... Figure 12E In the illustrated embodiment, the number of third vias H3 and the number of fourth vias H4 are both one; however, in other embodiments of this disclosure, the number of third vias H3 and the number of fourth vias H4 may also be two, three, four or more, etc., and the number of third vias H3 and fourth vias H4 may be the same as the number of first vias H1 and second vias H2, or may be different from the number of first vias H1 and second vias H2. The embodiments of this disclosure do not impose specific limitations on this.

[0063] For example, such as Figure 12E As shown, in the stacking direction R1, the first via H1 in the first insulating layer 111 does not overlap with the third via H3 and the fourth via H4 in the second insulating layer 112, and the second via H2 in the first insulating layer 111 does not overlap with the third via H3 and the fourth via H4 in the second insulating layer 112. That is, in this stacking direction R1, the first via H1, the second via H2, the third via H3, and the fourth via H4 do not overlap with each other.

[0064] For example, in some embodiments, step S12 above includes step S121.

[0065] Step S121: Select any one of the first adjacent conductive layer, the second adjacent conductive layer, and the first insulating layer for layout adjustment to obtain the application design scheme.

[0066] For step S12 above, Figure 12E Taking the initial design scheme of the integrated circuit shown as an example, if the initial design scheme satisfies the condition that the first sub-part 131 in the first adjacent conductive layer 101 overlaps with both the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 in the stacking direction R1, and the second sub-part 141 in the first adjacent conductive layer 101 also overlaps with both the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 in the stacking direction R1, then based on this initial design scheme, the corresponding application design scheme can be obtained by modifying only any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111. This reduces the amount of modification and time required in obtaining the application design scheme from the initial design scheme, and also reduces the number of new photomasks that need to be redesigned or fabricated, thereby reducing the R&D cost of integrated circuits and improving R&D efficiency.

[0067] It should be noted that in some other embodiments of this disclosure, it is also possible to only target...Figure 12E The third conductive layer 103 or the second insulating layer 112 shown in the initial design scheme is modified to obtain a corresponding application design scheme, that is, by modifying any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third conductive layer 103, the first insulating layer 111, and the second insulating layer 112, the required application design scheme is obtained.

[0068] Next, the implementation process of obtaining an application design scheme based on the initial design scheme shown in Figure 12E But it should be noted that the embodiments of the present disclosure include but are not limited to this.

[0069] Figure 12E An initial design scheme and an application design scheme of an integrated circuit provided by some embodiments of the present disclosure are shown in the following schematic diagram, Figure 11 Another initial design scheme and an application design scheme of an integrated circuit provided by some embodiments of the present disclosure are shown in the following schematic diagram. For example, Figure 13 The initial design scheme of the integrated circuit is shown on the left side, and the application design scheme obtained based on the initial design scheme is shown on the right side; Figure 12E The initial design scheme of the integrated circuit is shown on the left side, and the application design scheme obtained based on the initial design scheme is shown on the right side. It should be noted that, in addition to including the first input interface INPT1, the first output interface OUTPT1, the second input interface INPT2, and the second output interface OUTPT2, Figure 13 And Figure 13 The initial design scheme shown in Figure 13 The initial design scheme shown in

[0070] For example, as shown in Figure 13 And Figure 13 The first conductive part 130 can be used to transmit a first signal, and the second conductive part 140 can be used to transmit a second signal different from the first signal. For example, the first signal can be transmitted from the input interface INPT1 to the corresponding output interface OUTPT1 through the first conductive part 130, and the second signal can be transmitted from the input interface INPT2 to the corresponding output interface OUTPT2 through the second conductive part 140.

[0071] For example, the input interface INPT1 of the first signal and the input interface INPT2 of the second signal are disposed in the same conductive layer, for example, in the third adjacent conductive layer 103, and the input interfaces INPT1 and INPT2 of the first signal are centrally symmetrical about each other with respect to the fourth reference point N4. The output interface OUTPT1 of the first signal and the output interface OUTPT2 of the second signal are disposed in the same conductive layer, for example, in the first adjacent conductive layer 101, and the output interfaces OUTPT1 and OUTPT2 of the first signal are centrally symmetrical about each other with respect to the first reference point N1.

[0072] It should be noted that in some other examples or embodiments of this disclosure, the input interface INPT1 of the first signal and the input interface INPT2 of the second signal may also be located in different conductive layers; the output interface OUTPT1 of the first signal and the output interface OUTPT2 of the second signal may also be located in different conductive layers; the input interface INPT1 and the output interface OUTPT1 of the first signal, as well as the input interface INPT2 and the output interface OUTPT2 of the second signal, may also be located in other conductive layers, for example, they may also be located in the integrated circuit except for Figure 13 and Figure 14 The embodiments of this disclosure do not impose specific limitations on the other conductive layers besides the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103 shown.

[0073] For example, consider adjusting the positions of the input interface INPT1 for the first signal and the input interface INPT2 for the second signal in the initial design scheme, such as swapping their positions to obtain a new application design scheme. Figure 14 As shown, based on the provided initial design scheme, the layout of the first insulating layer 111 can be adjusted to obtain the corresponding application design scheme. For example, in Figure 11 In the example shown, step S121 may include: obtaining an application layout structure after rotation relative to the original layout structure plane of the first insulating layer 111, based on the original layout structure in the first insulating layer 111.

[0074] For example, such as Figure 14 As shown, by rotating the original layout of the first insulating layer 111 in a plane, the positions of the first via H1 and the second via H2 in the first insulating layer 111 are adjusted, thereby changing the connection method of the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111. For example, as... Figure 15As shown, due to the change of the positions of the first via H1 and the second via H2 in the first insulating layer 111, the first sub portion 131 and the second sub portion 141 in the second adjacent conductive layer 102 are exchanged in the initial design scheme, i.e., the first sub portion 131 originally used for transmitting the first signal in the second adjacent conductive layer 102 becomes the second sub portion 141 used for transmitting the second signal, and the second sub portion 141 originally used for transmitting the second signal becomes the first sub portion 131 used for transmitting the first signal. Further, in the case where the positions of the third via H3 and the second via H4 in the second insulating layer 112 do not change, the first sub portion 131 and the second sub portion 141 in the third adjacent conductive layer 103 are also exchanged accordingly, i.e., the first sub portion 131 originally used for transmitting the first signal in the third adjacent conductive layer 103 becomes the second sub portion 141, and the second sub portion 141 originally used for transmitting the second signal becomes the first sub portion 131, thereby meeting the change requirement of reversing the setting positions of the input interface INPT1 of the first signal and the input interface INPT2 of the second signal.

[0075] Therefore, based on the initial design scheme Figure 15 As shown in the initial design scheme, when it is required to adjust or modify the setting positions of the input interface INPT1 of the first signal and the input interface INPT2 of the second signal, the layout structure of the via in the first insulating layer 111 can be adjusted to obtain a corresponding application design scheme. Further, the number of conductive layers and insulating layers that need to be changed in the integrated circuit can be reduced, the amount of change and the time required in the process of obtaining the corresponding application design scheme based on the initial design scheme can be reduced, and the number of new mask plates that need to be redesigned or prepared can also be reduced, thereby reducing the research and development cost of the integrated circuit and improving the research and development efficiency.

[0076] For example, as shown in the initial design scheme Figure 1 As shown in the initial design scheme, the second adjacent conductive layer 102 can be selected to be adjusted to obtain a corresponding application design scheme. For example, as shown in the example Figure 1

[0077] For example, as shown in the initial design scheme Figure 1 ​As shown, by performing a planar flip or mirror and planar rotation on the original layout structure of the second adjacent conductive layer 102, the connection mode of the first conductive part 130 and the second conductive part 140 in the second adjacent conductive layer 102, the third adjacent conductive layer 103 and the second insulating layer 112 can be changed. For example, as shown in the initial design scheme, Figure 1 As shown, due to the change of the positions of the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102, the connection functions of the third via hole H3 and the fourth via hole H4 in the second insulating layer 112 in the initial design scheme are changed, i.e., the third via hole H3 in the second insulating layer 112 originally used for transmitting the first signal is changed to be used for transmitting the second signal, and the fourth via hole H4 originally used for transmitting the second signal is changed to be used for transmitting the first signal. Further, in the case where the layout structure of the third adjacent conductive layer 103 is not changed, the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103 are also exchanged accordingly, i.e., the first sub-part 131 in the third adjacent conductive layer 103 originally used for transmitting the first signal is changed to be the second sub-part 141, and the second sub-part 141 originally used for transmitting the second signal is changed to be the first sub-part 131, thereby meeting the change requirement of adjusting the setting positions of the input interface INPT1 of the first signal and the input interface INPT2 of the second signal.

[0078] Therefore, based on the initial design scheme as shown, Figure 1 As shown, in the initial design scheme, when it is required to adjust or modify the setting positions of the input interface INPT1 of the first signal and the input interface INPT2 of the second signal according to actual design or application requirements, only the layout structure of the second adjacent conductive layer 102 needs to be adjusted, and the corresponding application design scheme can be obtained. Further, the number of conductive layers and insulating layers that need to be changed in the integrated circuit can be reduced, the amount of change and the time required in the process of obtaining the corresponding application design scheme based on the initial design scheme can be reduced, and the number of new mask plates that need to be redesigned or prepared can also be reduced, thereby reducing the research and development cost of the integrated circuit and improving the research and development efficiency.

[0079] For example, in the initial design scheme as shown, Figure 1 and Figure 16The example shown is an example, and the new application design scheme obtained can continue to satisfy the corresponding setting conditions of the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, the first insulating layer 111, and the second insulating layer 112 in the initial design scheme, that is, the application design scheme can include: in the stacking direction R1, the first sub-part 131 in the first adjacent conductive layer 101 and the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 all overlap, and the second sub-part 141 in the first adjacent conductive layer 101 and the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 all overlap.

[0080] For example, the application design scheme can also include: in the stacking direction R1, the first sub-part 131 in the second adjacent conductive layer 102 and the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103 all overlap, and the second sub-part 141 in the second adjacent conductive layer 102 and the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103 all overlap.

[0081] Therefore, in subsequent design, according to different actual needs, if it is necessary to continue to make changes based on the obtained application design scheme to obtain a new design scheme, the above-mentioned obtained application design scheme can be used as a new initial design scheme to continue to adjust. Further, the amount of changes and the time required in the process of making multiple changes based on the initial design scheme can be reduced, and the number of corresponding new mask plates that need to be redesigned or prepared is reduced, thereby further reducing the research and development cost of integrated circuits and improving the research and development efficiency.

[0082] For example, the application design scheme can also include the same or similar conditions as other settings in the initial design scheme for the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, the first insulating layer 111, and the second insulating layer 112. The specific content can be referred to the corresponding description of the initial design scheme, and the repeated parts will not be described again.

[0083] In some embodiments of the present disclosure, the orthographic projection of the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101 in a reference plane and the orthographic projection of the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 in the reference plane are different from each other, the reference plane being perpendicular to the stacking direction R1 of the first adjacent conductive layer 101 and the second adjacent conductive layer 102. That is, in the stacking direction R1, the pattern formed by the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101 and the pattern formed by the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 cannot completely overlap. Thus, it can be helpful to obtain a corresponding application design scheme by only modifying any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111.

[0084] For example, further, the orthographic projection of the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 in a reference plane and the orthographic projection of the first sub-section 131 and the second sub-section 141 in the third adjacent conductive layer 103 in the reference plane are different from each other, the reference plane being perpendicular to the stacking direction R1. That is, in the stacking direction R1, the pattern formed by the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 and the pattern formed by the first sub-section 131 and the second sub-section 141 in the third adjacent conductive layer 103 cannot completely overlap.

[0085] The initial design scheme of the integrated circuit shown in Figure 16 and Figure 17 will be described in detail below. For example, Figure 17 and Figure 17 shown in the examples can be Figure 17 the specific implementation of the initial design scheme of the integrated circuit shown in Figure 18 , reference can be made to the corresponding contents in the above-described embodiments of

[0086] Figure 18 a schematic diagram of a specific implementation example of an initial design scheme of an integrated circuit provided by some embodiments of the present disclosure, ​ a plan view of the first adjacent conductive layer in ​ , ​ a plan view of the second adjacent conductive layer in ​ , ​ a plan view of the third adjacent conductive layer in ​ .

[0087] For example, in combination with ​ and ​As shown, the first sub portion 131 and the second sub portion 141 in the first adjacent conductive layer 101 are provided with a first interval region RG1, and the first reference point N1 is the center of the first interval region RG1. The first sub portion 131 and the second sub portion 141 in the second adjacent conductive layer 102 are provided with a second interval region RG2, and the second reference point N2 is the center of the second interval region RG2. The first sub portion 131 and the second sub portion 141 in the third adjacent conductive layer 103 are provided with a third interval region RG3, and the third reference point N3 is the center of the third interval region RG3.

[0088] For example, the area surrounded by the orthographic projection of the first sub portion 131 and the second sub portion 141 in the first adjacent conductive layer 101 in a reference plane has the same size and shape as the area surrounded by the orthographic projection of the first sub portion 131 and the second sub portion 141 in the second adjacent conductive layer 101 in the reference plane. For example, the reference plane can be parallel to the plane where the first adjacent conductive layer 101 or the second adjacent conductive layer 102 is located. For example, the first sub portion 131 and the second sub portion 141 in the first adjacent conductive layer 101 constitute a square profile as a whole in the reference plane, the first sub portion 131 and the second sub portion 141 in the second adjacent conductive layer 102 constitute a square profile as a whole in the reference plane, and the two square profiles have the same size and shape.

[0089] For example, the area surrounded by the orthographic projection of the first sub portion 131 and the second sub portion 141 in the second adjacent conductive layer 102 in a reference plane has the same size and shape as the area surrounded by the orthographic projection of the first sub portion 131 and the second sub portion 141 in the third adjacent conductive layer 103 in the reference plane. For example, the first sub portion 131 and the second sub portion 141 in the second adjacent conductive layer 102 constitute a square profile as a whole in the reference plane, the first sub portion 131 and the second sub portion 141 in the third adjacent conductive layer 103 constitute a square profile as a whole in the reference plane, and the two square profiles have the same size and shape.

[0090] Therefore, in the case where the first reference point N1, the second reference point N2, and the third reference point N3 overlap with each other in the stacking direction R1, the layout space required by the first sub portion 131 and the second sub portion 141 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103 in the integrated circuit as a whole can be reduced, thereby facilitating the optimization of the structural design of the integrated circuit.

[0091] For example, the size and shape of the region enclosed by the orthogonal projection of the first sub-portion 131 in the first adjacent conductive layer 101 on the reference plane are the same as the size and shape of the region enclosed by the orthogonal projection of the first sub-portion 131 in the second adjacent conductive layer 102 on the reference plane, for example, both are "L" shaped patterns of the same size. The size and shape of the region enclosed by the orthogonal projection of the second sub-portion 141 in the first adjacent conductive layer 101 on the reference plane are the same as the size and shape of the region enclosed by the orthogonal projection of the second sub-portion 141 in the second adjacent conductive layer 102 on the reference plane, for example, both are "L" shaped patterns of the same size. In this way, it is beneficial to simplify the manufacturing process of the integrated circuit, thereby reducing the research and development cost of the integrated circuit.

[0092] For example, the size and shape of the region enclosed by the orthogonal projection of the first sub-portion 131 in the third adjacent conductive layer 103 on the reference plane are the same as the size and shape of the region enclosed by the orthogonal projection of the first sub-portion 131 in the second adjacent conductive layer 102 on the reference plane, for example, both are "L" shaped patterns of the same size. The size and shape of the region enclosed by the orthogonal projection of the second sub-portion 141 in the third adjacent conductive layer 103 on the reference plane are the same as the size and shape of the region enclosed by the orthogonal projection of the second sub-portion 141 in the second adjacent conductive layer 102 on the reference plane, for example, both are "L" shaped patterns of the same size.

[0093] For example, the overall pattern formed by the first sub-portion 131 and the second sub-portion 141 in the first adjacent conductive layer 101 is a double L shaped pattern that is centrally symmetric, the overall pattern formed by the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 is a double L shaped pattern that is centrally symmetric, and the overall pattern formed by the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103 is a double L shaped pattern that is centrally symmetric.

[0094] It should be noted that, in the initial design scheme shown in ​ For example, in the initial design scheme shown in

[0095] For example, in the case where the overall pattern formed by the first sub-portion 131 and the second sub-portion 141 in each conductive layer is a double L shaped pattern that is centrally symmetric, ​ For example, in the initial design scheme shown in ​ For example, in the initial design scheme shown in ​ For example, in the first adjacent conductive layer 101 shown in ​The layout design shown is (B); however, in some other examples, the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101 may also adopt... ​ Other layout designs, such as (A), (C), or (D). For example, in ​ In the second adjacent conductive layer 102 shown, the first sub-part 131 and the second sub-part 141 employ... ​ The layout design shown is (D); however, in some other examples, the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 may also adopt... ​ Other layout designs, such as (A), (B), or (C). For example, in ​ In the third adjacent conductive layer 103 shown, the first sub-part 131 and the second sub-part 141 employ... ​ The layout design shown is (B); however, in some other examples, the first sub-section 131 and the second sub-section 141 in the third adjacent conductive layer 103 may also adopt... ​ Other layout designs, such as (A), (C), or (D), are also possible. It should be noted that embodiments of this disclosure include, but are not limited to, these.

[0096] It should be noted that, with ​ Taking the initial design shown as an example, the first via H1 and the second via H2 in the first insulating layer 111, as well as the third via H3 and the fourth via H4 in the second insulating layer 112, can also adopt other suitable layout designs. The embodiments of this disclosure do not impose specific limitations on this.

[0097] For example, taking the first via H1 and the second via H2 as examples, when the overall pattern formed by the first sub-parts 131 and the second sub-parts 141 in the first adjacent conductive layer 101 and the second adjacent conductive layer 102 is a centrally symmetrical double L-shaped pattern, ​ It shows ​ The initial design shown includes various layout design examples for the first via H1 and the second via H2. For example, refer to... ​ As shown, the first via H1 and the second via H2 can be respectively located at positions P1 to P8. For example, in ​ In the first insulating layer 111 shown, the first via H1 and the second via H2 employ... ​ The layout design shown (B) is that the vias are located at positions P1 and P5 respectively; however, in some other examples, the first via H1 and the second via H2 can also be used. ​ Other layout designs, such as (A), (C), or (D), are also possible. It should be noted that embodiments of this disclosure include, but are not limited to, these.

[0098] For example, the layout of the third via H3 and the fourth via H4 is basically the same as that of the first via H1 and the second via H2 described above, and the repetitions will not be repeated. For example, in ​ In the second insulating layer 112 shown, the third via H3 and the fourth via H4 employ... ​ The layout design shown (D) is that the vias are located at positions P2 and P6 respectively; however, in some other examples, the third via H3 and the fourth via H4 can also be used. ​ Other layout designs in the example, such as (A), (B), or (C).

[0099] For example, with ​ Taking the initial design scheme shown as an example, ​ This diagram illustrates the placement of the input interfaces for the first and second signals in an initial design scheme of an integrated circuit provided by some embodiments of this disclosure. For example, as... ​ As shown, the input interface INPT1 for the first signal and the input interface INPT2 for the second signal can be set at positions P1 to P8 respectively. For example, they can be respectively used... ​ The layout designs shown are (A), (B), (C), or (D). It should be noted that, except for... ​ Besides the layout shown, the input interface INPT1 for the first signal and the input interface INPT2 for the second signal can also adopt other suitable layout designs. The embodiments of this disclosure do not impose specific limitations on this.

[0100] For example, the layout of the output interface OUTPT1 of the first signal and the output interface OUTPT2 of the second signal is basically the same as the layout of the input interface INPT1 of the first signal and the input interface INPT2 of the second signal, and the repeated parts will not be described again.

[0101] ​ This is a schematic diagram illustrating a specific example of an initial design scheme for another integrated circuit provided in some embodiments of this disclosure. It should be noted that, except that there are multiple first vias H1, second vias H2, third vias H3, and fourth vias H4, ​ The initial design scheme of the integrated circuit shown is... ​ The initial design schemes of the integrated circuits shown are basically the same or similar, and the repeated parts will not be described again.

[0102] For example, such as ​ As shown, there are two first vias H1 and two second vias H2, and two third vias H3 and two fourth vias H4. This helps to improve the electrical connection between the first sub-parts 131 in adjacent conductive layers and the electrical connection between the second sub-parts 141 in adjacent conductive layers.

[0103] It should be noted that in some other embodiments of the present disclosure, the number of the first via hole H1, the second via hole H2, the third via hole H3 and the fourth via hole H4 can also be 3, 4 or more, and the embodiments of the present disclosure do not make specific limitations thereto.

[0104] ​ a specific implementation example of the initial design scheme of the integrated circuit provided by some embodiments of the present disclosure, ​ for ​ a plan view of the first adjacent conductive layer in ​ for ​ a plan view of the second adjacent conductive layer in ​ for ​ a plan view of the third adjacent conductive layer in ​ for ​ a plan view of the fourth adjacent conductive layer in

[0105] For example, as shown in ​ and ​ , in addition to the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the third adjacent conductive layer 103, the initial design scheme of the integrated circuit also includes a fourth adjacent conductive layer 104. For example, the fourth adjacent conductive layer 104 is adjacent to the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the third adjacent conductive layer 103, and is located on the side of the third adjacent conductive layer 103 away from the second adjacent conductive layer 102. The first conductive part 130 and the second conductive part 140 are also located in the fourth adjacent conductive layer 104, that is, the first conductive part 130 also includes a first sub-part 131 located in the fourth adjacent conductive layer 104, and the second conductive part 140 also includes a second sub-part 141 located in the fourth adjacent conductive layer 104. In the stacking direction R1, the first sub-part 131 in the fourth adjacent conductive layer 104 overlaps with the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103, and the second sub-part 141 in the fourth adjacent conductive layer 104 overlaps with the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103, that is, the first sub-part 131 in the third adjacent conductive layer 103 overlaps with the first sub-part 131 and the second sub-part 141 in the fourth adjacent conductive layer 104, and the second sub-part 141 in the third adjacent conductive layer 103 overlaps with the first sub-part 131 and the second sub-part 141 in the fourth adjacent conductive layer 104.

[0106] The specific arrangement of the first sub-section 131 and the second sub-section 141 in the fourth adjacent conductive layer 104 and the connection manner between the fourth adjacent conductive layer 104 and the third adjacent conductive layer 103 (for example, the layout manner of the fifth via hole H5 and the sixth via hole H6 for arranging the first connection section 132 and the second connection section 142) can refer to the corresponding description of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103 above, and the repeated parts will not be described here.

[0107] For example, in combination with the description of FIG. 1, the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the second adjacent conductive layer 102, and the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the second adjacent conductive layer 102. ​ ​ For example, in combination with the description of FIG. 1, the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the second adjacent conductive layer 102, and the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the second adjacent conductive layer 102.

[0108] For example, in combination with the description of FIG. 1, the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the second adjacent conductive layer 102, and the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the second adjacent conductive layer 102.

[0109] For example, in combination with the description of FIG. 1, the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the first sub-section 131 in the reference plane in the second adjacent conductive layer 102, and the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the first adjacent conductive layer 101 are different from the size and shape of the region surrounded by the orthographic projection of the second sub-section 141 in the reference plane in the second adjacent conductive layer 102.

[0110] ​For example, the size and shape of the region enclosed by the orthographic projection of the first sub-part 131 in the first adjacent conductive layer 101 onto the reference plane are the same as the size and shape of the region enclosed by the orthographic projection of the first sub-part 131 in the fourth adjacent conductive layer 104 onto the reference plane, and the size and shape of the region enclosed by the orthographic projection of the second sub-part 141 in the first adjacent conductive layer 101 onto the reference plane are the same as the size and shape of the region enclosed by the orthographic projection of the second sub-part 141 in the fourth adjacent conductive layer 104 onto the reference plane.

[0111] For example, such as ​ As shown, the overall pattern formed by the first sub-part 131 and the second sub-part 141 in the first adjacent conductive layer 101 is a centrally symmetrical double-Z pattern composed of two approximately Z-shaped structures facing each other. The overall pattern formed by the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 is a centrally symmetrical double-U pattern composed of two U-shaped structures intersecting each other. The overall pattern formed by the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103 is a centrally symmetrical double-U pattern composed of two U-shaped structures intersecting each other. The overall pattern formed by the first sub-part 131 and the second sub-part 141 in the fourth adjacent conductive layer 104 is a centrally symmetrical double-Z pattern composed of two approximately Z-shaped structures facing each other.

[0112] For example, in ​ as well as ​ In the illustrated embodiment, the first sub-part 131 and the second sub-part 141 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, and the fourth adjacent conductive layer 104 respectively employ... ​ The four layout options are shown.

[0113] For example, these four layout methods can be divided into two groups. ​ and ​ The layout shown belongs to the first group of layouts. ​ and ​The layout shown belongs to the second group of layout methods. For example, the first sub-part 131 and the second sub-part 141 in two adjacent conductive layers adopt layout methods belonging to different groups, thereby avoiding the situation where the layout methods of the first sub-part 131 and the second sub-part 141 in two adjacent conductive layers are exactly the same during multiple modifications to the initial design of the integrated circuit. In this way, based on different actual needs, the obtained application design scheme can be further modified to obtain a new design scheme, thereby reducing the amount of changes and time required during multiple modifications based on the initial design scheme, and reducing the number of corresponding new photomasks that need to be redesigned or fabricated, thus further reducing the R&D cost of integrated circuits and improving R&D efficiency.

[0114] For example, the first sub-part 131 and the second sub-part 141 in two non-adjacent conductive layers can adopt a layout belonging to the same group, which helps to simplify the integrated circuit fabrication process and reduce the integrated circuit R&D cost.

[0115] For example, in a new application design scheme where the positions of two input interfaces (or two output interfaces) are swapped by modifying any one of the first adjacent conductive layers 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, and the fourth adjacent conductive layer 104, the layout of the first sub-part 131 and the second sub-part 141 in the selected conductive layer can be changed to another layout belonging to the same group of layouts.

[0116] For example, when choosing the right ​ When the first adjacent conductive layer 101 shown is modified, the layout of the first sub-part 131 and the second sub-part 141 in the first adjacent conductive layer 101 can be modified to belong to the same first group of layouts. ​ The layout shown; when selecting the correct layout... ​ When modifying the second adjacent conductive layer 102 shown, the layout of the first sub-part 131 and the second sub-part 141 in the second adjacent conductive layer 102 can be modified to belong to the same second group of layouts. ​ The layout shown; when selecting the correct layout... ​ When modifying the third adjacent conductive layer 103 shown, the layout of the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103 can be modified to belong to the same first group of layouts. ​ The layout shown; when selecting the correct layout... ​ When modifying the fourth adjacent conductive layer 104 shown, the layout of the first sub-part 131 and the second sub-part 141 in the fourth adjacent conductive layer 104 can be modified to belong to the same second group of layouts. ​The layout shown.

[0117] For example, ​ For example, ​ The layout of the vias in the same insulating layer in the design of the integrated circuit shown. For example, ​ The layout of the vias in the same insulating layer in the design of the integrated circuit shown. For example, ​ The layout of the vias in the same insulating layer in the design of the integrated circuit shown. For example, ​ The via H shown in can correspond to ​ The first via H1, the second via H2, the third via H3, the fourth via H4, the fifth via H5 or the sixth via H6 shown in.

[0118] For example, in combination with ​ For example, in combination with ​ As shown in, in the first insulating layer between the first adjacent conductive layer 101 and the second adjacent conductive layer 102, the first via H1 and the second via H2 adopt the layout design (A) shown in; in the second insulating layer between the second adjacent conductive layer 102 and the third adjacent conductive layer 103, the third via H3 and the fourth via H4 adopt the layout design (C) shown in; in the third insulating layer between the third adjacent conductive layer 103 and the fourth adjacent conductive layer 104, the fifth via H5 and the sixth via H6 adopt the layout design (B) shown in. ​ ​ ​

[0119] For example, ​ The four via layout modes shown in can be divided into two groups:The layout modes shown in (A) and (B) in belong to the first group of layout modes, and the layout modes shown in (C) and (D) belong to the second group of layout modes. For example, the vias in two adjacent insulating layers adopt layout modes belonging to different groups, so as to avoid the situation that the layout modes of the vias in two adjacent insulating layers are completely the same in the process of modifying the initial design of the integrated circuit multiple times. In this way, according to actual different needs, the obtained application design can be further changed to obtain a new design, thereby reducing the amount of change and the time required in the process of changing the initial design multiple times, and reducing the number of new mask plates that need to be redesigned or prepared, thereby further reducing the research and development cost of the integrated circuit and improving the research and development efficiency. ​ For example, the vias in two non-adjacent insulating layers can adopt layout modes belonging to the same group, thereby facilitating the simplification of the preparation process of the integrated circuit and reducing the research and development cost of the integrated circuit.

[0120]

[0121] ​​​For example, in a new application design scheme where the positions of two input interfaces (or two output interfaces) are swapped by modifying any one of the first, second, and third insulating layers, the via layout in the selected insulating layer can be changed to another layout belonging to the same group of layouts.

[0122] For example, when modifying the layout of vias in the first insulating layer, the layout of vias in the first insulating layer can be changed to belong to the same first group of layouts. ​ The layout shown is (B). When modifying the layout of vias in the second insulating layer, the layout of vias in the second insulating layer can be changed to belong to the same second group of layouts. ​ The layout shown (D) allows modification of the via layout in the third insulating layer, changing it to belong to the same group of layouts as the first group. ​ The layout shown is (A).

[0123] For example, with ​ Taking the second adjacent conductive layer 102 in the initial design shown as an example, ​ The diagram shows the use of the first via H1 and the second via H2 respectively. ​ The four different via design methods shown, and the location of the input interface INPT1 (or output interface OUTPT1) of the first signal and the input interface INPT2 (or output interface OUTPT2) of the second signal in the first adjacent conductive layer 101 or the second adjacent conductive layer 102.

[0124] For example, such as ​ As shown, taking input interfaces INPT1 and INPT2 as examples, corresponding to different layouts of the first via H1 and the second via H2, the input interface INPT1 for the first signal and the input interface INPT2 for the second signal can respectively adopt... ​ The layout designs shown are (A), (B), (C), (D), (E), or (F).

[0125] For example, such as ​ As shown, in the stacking direction R1, neither the input interface INPT1 of the first signal nor the input interface INPT2 of the second signal overlaps with the first via H1 and the second via H2.

[0126] For example, in the eight positions for setting the first via hole H1, the second via hole H2, the input interface INPT1 and the input interface INPT2, the eight positions include four inner side positions (for example, referred to as inner side regions) relatively close to the center symmetry point of the first sub part 131 and the second sub part 141 and four outer side positions (for example, referred to as outer side regions) relatively far away from the center symmetry point of the first sub part 131 and the second sub part 141. For example, referring to the layout modes (A) and (B) shown in ​ , in the case of setting the first via hole H1 and the second via hole H2 in the outer side regions, the input interfaces INPT1 and INPT2 need to be set in the inner side regions; referring to the layout modes (C), (D), (E) and (F) shown in ​ , in the case of setting the first via hole H1 and the second via hole H2 in the inner side regions, the input interfaces INPT1 and INPT2 need to be set in the outer side regions, so as to ensure the stability and reliability of signal transmission.

[0127] It should be noted that, in addition to the layout modes shown in ​ , the input interface INPT1 and the output interface OUTPT1 of the first signal and the input interface INPT2 and the output interface OUTPT2 of the second signal can also correspondingly adopt other suitable layout designs, and the embodiments of the present disclosure do not make specific limitations thereon.

[0128] ​ A schematic diagram of another specific example of an initial design scheme of an integrated circuit provided by some embodiments of the present disclosure. It should be noted that, in addition to the number of the first via hole H1, the second via hole H2, the third via hole H3, the fourth via hole H4, the fifth via hole H5 and the sixth via hole H6 being multiple, ​ , the initial design scheme of the integrated circuit shown in ​ is basically the same or similar to the initial design scheme of the integrated circuit shown in , and the repeated parts will not be described herein.

[0129] ​ For example, as shown in , the number of the first via hole H1 and the number of the second via hole H2 are both 2, the number of the third via hole H3 and the number of the fourth via hole H4 are both 2, and the number of the fifth via hole H5 and the number of the sixth via hole H6 are both 2, which helps to improve the electrical connection effect between the first sub part 131 in the adjacent conductive layer and the electrical connection effect between the second sub part 141 in the adjacent conductive layer.

[0130] It should be noted that, in some other embodiments of the present disclosure, the number of the first via hole H1, the second via hole H2, the third via hole H3, the fourth via hole H4, the fifth via hole H5 and the sixth via hole H6 can also be 3, 4 or more, and the embodiments of the present disclosure do not make specific limitations thereon.

[0131] In some embodiments of the present disclosure, each of the conductive layers described above can be a metal layer. For example, the material of the conductive layer can include a metal material such as aluminum, molybdenum, copper, silver, or an alloy material of these metal materials, such as an APC (silver-palladium-copper) material, and the like.

[0132] For example, the material of each of the insulating layers described above can be an inorganic insulating material, for example, the inorganic insulating material is a transparent material. For example, the inorganic insulating material is an oxide of silicon such as silicon oxide, silicon nitride, silicon oxynitride, or a nitride or oxynitride of silicon, or a metal oxynitride insulating material including aluminum oxide, titanium nitride, and the like. For example, the material of the insulating layer can also be an organic insulating material to obtain good bending resistance. For example, the organic insulating material is a transparent material. For example, the organic insulating material is OCA optical glue. For example, the organic insulating material can include polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and the like.

[0133] It should be noted that in the embodiments of the present disclosure, the flow of the design method of the integrated circuit provided by each of the embodiments of the present disclosure can include more or fewer operations, and these operations can be executed sequentially or in parallel. Although the flow of the design method of the integrated circuit described above includes a plurality of operations appearing in a specific order, it should be clearly understood that the order of the plurality of operations is not limited. The design method of the integrated circuit described above can be executed once, or multiple times according to predetermined conditions.

[0134] The present disclosure at least one embodiment also provides an integrated circuit, the integrated circuit includes a plurality of conductive layers; the plurality of conductive layers are arranged in a stacked manner, and at least one insulating layer is arranged between each two adjacent conductive layers to insulate and separate the two adjacent conductive layers from each other; the integrated circuit includes a first conductive part and a second conductive part which are insulated from each other, the first conductive part includes a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between different conductive layers to connect the plurality of first sub-parts, and the second conductive part includes a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers include a first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part in the first adjacent conductive layer at least partially overlaps with the first sub-part and the second sub-part in the second adjacent conductive layer, and the second sub-part in the first adjacent conductive layer at least partially overlaps with the first sub-part and the second sub-part in the second adjacent conductive layer.

[0135] It should be noted that, in the embodiments of the present disclosure, the specific layout structure, functions and technical effects of the integrated circuit can refer to the description of the initial design scheme of the integrated circuit and the application design scheme in the design method of the integrated circuit in the foregoing, and will not be described here.

[0136] The integrated circuit design apparatus provided by at least one embodiment of the present disclosure can reduce the number of conductive layers and insulating layers that need to be changed in the integrated circuit when the connection mode between the first sub-part in the first conductive part and the first connection part and the connection mode between the second sub-part in the second conductive part and the second connection part need to be adjusted or modified, and can reduce the amount of change and the time required in the process of adjusting or modifying the layout structure based on the initial design scheme of the integrated circuit to obtain the application design scheme, thereby reducing the research and development cost of the integrated circuit and improving the research and development efficiency.

[0137] ​ A schematic block diagram of an integrated circuit design apparatus provided by some embodiments of the present disclosure is shown.

[0138] For example, as shown in ​ , the integrated circuit design apparatus 700 includes an initial design scheme acquisition unit 701 and an application design scheme acquisition unit 702.

[0139] The initial design scheme acquisition unit 701 is configured to acquire an initial design scheme of an integrated circuit. For example, the initial design scheme acquisition unit 701 can perform step S11 in the design method of the integrated circuit shown in ​

[0140] The application design scheme acquisition unit 702 is configured to obtain an application design scheme of the integrated circuit based on the initial design scheme. For example, the application design scheme acquisition unit 702 can perform step S12 in the design method of the integrated circuit shown in ​

[0141] ​​The integrated circuit includes a plurality of conductive layers, the plurality of conductive layers are arranged in a stack, at least one insulating layer is arranged between each two adjacent conductive layers to separate and insulate the two adjacent conductive layers from each other; in an initial design scheme, the integrated circuit includes a first conductive part and a second conductive part which are insulated from each other, the first conductive part includes a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between different conductive layers to connect the plurality of first sub-parts, the second conductive part includes a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers include a first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part in the first adjacent conductive layer at least partially overlaps the first sub-part and the second sub-part in the second adjacent conductive layer, and the second sub-part in the first adjacent conductive layer at least partially overlaps the first sub-part and the second sub-part in the second adjacent conductive layer.

[0142] For example, the initial design scheme acquisition unit 701 and the application design scheme acquisition unit 702 include codes and programs stored in a memory; a processor can execute the codes and programs to implement some or all functions of the initial design scheme acquisition unit 701 and the application design scheme acquisition unit 702 as described above. For example, the initial design scheme acquisition unit 701 and the application design scheme acquisition unit 702 can be special hardware devices to implement some or all functions of the initial design scheme acquisition unit 701 and the application design scheme acquisition unit 702 as described above. For example, the initial design scheme acquisition unit 701 and the application design scheme acquisition unit 702 can be one circuit board or a combination of multiple circuit boards to implement the functions as described above. In the embodiments of the present application, the one circuit board or the combination of multiple circuit boards can include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory and executable by the processor.

[0143] It should be noted that the initial design scheme acquisition unit 701 is configured to implement ​ The application design scheme acquisition unit 702 is configured to implement ​ The specific description of the initial design scheme acquisition unit 701 can be referred to the related description of step S11 in the embodiments of the design method of the integrated circuit described above, and the specific description of the application design scheme acquisition unit 702 can be referred to the related description of step S12 in the embodiments of the design method of the integrated circuit described above. ​ The specific description of the initial design scheme acquisition unit 701 can be referred to the related description of step S11 in the embodiments of the design method of the integrated circuit described above, and the specific description of the application design scheme acquisition unit 702 can be referred to the related description of step S12 in the embodiments of the design method of the integrated circuit described above. ​The relevant description of step S12 is shown. In addition, the integrated circuit design apparatus can achieve similar technical effects as the design method of the foregoing integrated circuit, and details are not described herein.

[0144] The electronic device provided by at least one embodiment of the present disclosure includes a processor, a memory, and one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the design method of the integrated circuit provided by any embodiment of the present disclosure.

[0145] ​ A schematic block diagram of an electronic device provided by some embodiments of the present disclosure is shown. As shown, the electronic device 300 includes a processor 310 and a memory 320. The memory 320 is configured to non-transiently store computer executable instructions (for example, one or more computer program modules). The processor 310 is configured to run the computer executable instructions, and the computer executable instructions can execute one or more steps in the design method of the integrated circuit described above when executed by the processor 310. The memory 320 and the processor 310 can be interconnected by a bus system and / or other forms of connection mechanism (not shown). ​

[0146] For example, the processor 310 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capability and / or program execution capability. For example, the central processing unit (CPU) can be X86 or ARM architecture, etc. The processor 310 can be a general-purpose processor or a special-purpose processor, and can control other components in the electronic device 300 to perform desired functions.

[0147] For example, the memory 320 can include any combination of one or more computer program products, which can include various forms of computer readable storage media, such as volatile memory and / or non-volatile memory. For example, the volatile memory can include random access memory (RAM), cache memory, etc. The non-volatile memory can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer readable storage medium, and the processor 310 can run the one or more computer program modules to implement various functions of the electronic device 300. Various application programs and various data used and / or generated by the application programs can also be stored in the computer readable storage medium.

[0148] ​It should be noted that the specific functions and technical effects of the electronic device 300 in the embodiments of the present disclosure can refer to the description of the design method of the integrated circuit and the integrated circuit design apparatus in the foregoing, and will not be described here.

[0149] ​ Another schematic block diagram of an electronic device is provided for some embodiments of the present disclosure. The electronic device 400 is suitable for implementing the design method of the integrated circuit provided by the embodiments of the present disclosure, for example. The electronic device 400 can be a terminal device or the like. It should be noted that, ​ The electronic device 400 shown is only an example, which does not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0150] As ​ shown, the electronic device 400 can include a processing apparatus (such as a central processor, a graphics processor, etc.) 410, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 420 or loaded into a random access memory (RAM) 430 from a storage apparatus 480. In the RAM 430, various programs and data required for the operation of the electronic device 400 are also stored. The processing apparatus 410, the ROM 420, and the RAM 430 are connected to each other through a bus 440. An input / output (I / O) interface 450 is also connected to the bus 440.

[0151] Generally, the following apparatuses can be connected to the I / O interface 450: an input apparatus 460 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output apparatus 470 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage apparatus 480 including, for example, a magnetic tape, a hard disk, etc.; and a communication apparatus 490. The communication apparatus 490 can allow the electronic device 400 to perform wireless or wired communication with other electronic devices to exchange data. Although ​ The electronic device 400 with various apparatuses is shown, but it should be understood that it is not required to implement or have all the apparatuses shown, and the electronic device 400 can instead implement or have more or fewer apparatuses.

[0152] For example, according to an embodiment of the present disclosure, the design method of the integrated circuit described above can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for executing the design method of the integrated circuit described above. In such an embodiment, the computer program can be downloaded and installed from a network through the communication apparatus 490, or installed from the storage apparatus 480, or installed from the ROM 420. When the computer program is executed by the processing apparatus 410, the functions defined in the design method of the integrated circuit provided by an embodiment of the present disclosure can be implemented.

[0153] ​ A schematic diagram of a storage medium provided by some embodiments of the present disclosure is shown. For example, as shown in ​ the storage medium 500 can be a non-transitory computer readable storage medium, and one or more computer readable instructions 501 can be non-transitorily stored on the storage medium 500. For example, when the computer readable instructions 501 are executed by a processor, one or more steps of the design method of the integrated circuit described above can be performed.

[0154] For example, the storage medium 500 can be applied in the electronic device described above, for example, the storage medium 500 can include a memory in the electronic device.

[0155] For example, the storage medium can include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage medium.

[0156] For example, the description of the storage medium 500 can refer to the description of the memory in the embodiments of the electronic device, and the repeated parts will not be described herein. The specific functions and technical effects of the storage medium 500 can refer to the description of the design method of the integrated circuit and the integrated circuit design apparatus above, and will not be described herein.

[0157] For the present disclosure, the following points need to be explained:

[0158] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0159] (2) In the drawings used to describe embodiments of the present application, the thickness and size of layers or structures are exaggerated for clarity. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or one or more intervening elements can also be present.

[0160] (3) The embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments without conflict.

[0161] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for designing an integrated circuit, comprising: obtaining an initial design of an integrated circuit; and obtaining an application design of the integrated circuit based on the initial design; wherein the integrated circuit comprises a plurality of conductive layers, the plurality of conductive layers are arranged in a stack, and at least one insulating layer is arranged between each two adjacent conductive layers to separate and insulate the two adjacent conductive layers; in the initial design, the integrated circuit comprises a first conductive part and a second conductive part which are insulated from each other, the first conductive part comprises a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between the different conductive layers to connect the plurality of first sub-parts, the second conductive part comprises a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between the different conductive layers to connect the plurality of second sub-parts, the plurality of conductive layers comprises a first adjacent conductive layer and a second adjacent conductive layer, the first conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part passes through at least the first adjacent conductive layer and the second adjacent conductive layer, in a stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, a first sub-part in the first adjacent conductive layer at least partially overlaps a first sub-part and a second sub-part in the second adjacent conductive layer, and a second sub-part in the first adjacent conductive layer at least partially overlaps the first sub-part and the second sub-part in the second adjacent conductive layer, the integrated circuit further comprises a first insulating layer between the first adjacent conductive layer and the second adjacent conductive layer, and the first connecting part and the second connecting part pass through the first insulating layer, wherein the obtaining the application design of the integrated circuit based on the initial design comprises: obtaining an application layout structure which is planarly rotated, flipped or mirrored relative to an original layout structure of any one of the first adjacent conductive layer, the second adjacent conductive layer and the first insulating layer. The application design of the integrated circuit is the same as the initial design. The first sub-part and the second sub-part in the first adjacent conductive layer are separated and insulated from each other and are centrally symmetrically arranged relative to a first reference point. The first sub-part and the second sub-part in the second adjacent conductive layer are separated and insulated from each other and are centrally symmetrically arranged relative to a second reference point. The integrated circuit further comprises a first insulating layer between the first adjacent conductive layer and the second adjacent conductive layer, the first insulating layer comprises at least one first via and at least one second via, the first via and the second via pass through the first insulating layer and are respectively used for arranging the first connecting part and the second connecting part, the first via and the second via are centrally symmetrically arranged relative to a third reference point, and the first reference point, the second reference point and the third reference point overlap with each other in the stacking direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The method of designing an integrated circuit according to claim 1, wherein, ​ 3. The design method of an integrated circuit according to claim 1 or 2, wherein, ​ ​ ​ ​ ​ ​ 4. The method of designing an integrated circuit according to claim 3, wherein, A first sub-portion and a second sub-portion in the first adjacent conductive layer are provided with a first interval region, and the first reference point is the center of the first interval region. A first sub-portion and a second sub-portion in the second adjacent conductive layer are provided with a second interval region, and the second reference point is the center of the second interval region.

5. The method of designing an integrated circuit according to claim 3, wherein, The first sub-portion and the second sub-portion in the first adjacent conductive layer have different orthographic projections in a reference plane from the first sub-portion and the second sub-portion in the second adjacent conductive layer, and the reference plane is perpendicular to the stacking direction.

6. The design method of an integrated circuit according to claim 5, wherein, The orthographic projections of the first sub-portion and the second sub-portion in the first adjacent conductive layer in the reference plane enclose a region having the same size and shape as the orthographic projections of the first sub-portion and the second sub-portion in the second adjacent conductive layer in the reference plane.

7. The design method of an integrated circuit according to claim 6, wherein, The orthographic projection of the first sub-portion in the first adjacent conductive layer in the reference plane encloses a region having the same size and shape as the orthographic projection of the first sub-portion in the second adjacent conductive layer in the reference plane, The orthographic projection of the second sub-portion in the first adjacent conductive layer in the reference plane encloses a region having the same size and shape as the orthographic projection of the second sub-portion in the second adjacent conductive layer in the reference plane.

8. The method of designing an integrated circuit according to claim 6, wherein, The overall pattern formed by the first sub-portion and the second sub-portion in the first adjacent conductive layer is a center-symmetric double-L pattern, and the overall pattern formed by the first sub-portion and the second sub-portion in the second adjacent conductive layer is a center-symmetric double-L pattern.

9. The method of designing an integrated circuit according to claim 5, wherein, The orthographic projection of the first sub-portion in the first adjacent conductive layer in the reference plane encloses a region having different size and shape from the orthographic projection of the first sub-portion in the second adjacent conductive layer in the reference plane, The orthographic projection of the second sub-portion in the first adjacent conductive layer in the reference plane encloses a region having different size and shape from the orthographic projection of the second sub-portion in the second adjacent conductive layer in the reference plane.

10. The design method of an integrated circuit according to Claim 9, wherein, The overall pattern formed by the first sub-portion and the second sub-portion in the first adjacent conductive layer is a center-symmetric double-U pattern, and the overall pattern formed by the first sub-portion and the second sub-portion in the second adjacent conductive layer is a center-symmetric double-Z pattern.

11. The method of designing an integrated circuit according to claim 3, wherein, The first conductive portion is used for transmitting a first signal, and the second conductive portion is used for transmitting a second signal different from the first signal, and the initial design scheme of the integrated circuit further includes: In response to the input interface of the first signal and the input interface of the second signal being arranged in the same conductive layer, the input interface of the first signal and the input interface of the second signal are arranged in a center-symmetric manner. In response to the output interface of the first signal and the output interface of the second signal being arranged in the same conductive layer, the output interface of the first signal and the output interface of the second signal are arranged in a center-symmetric manner.

12. The design method of an integrated circuit according to Claim 11, wherein, In the stacking direction, the input interface and the output interface of the first signal do not overlap with the first via and the second via in the first insulating layer, and the input interface and the output interface of the second signal do not overlap with the first via and the second via in the first insulating layer.

13. The method of designing an integrated circuit according to claim 3, wherein, In the initial design scheme, The plurality of conductive layers further comprises a third adjacent conductive layer, the third adjacent conductive layer is located on the side of the second adjacent conductive layer away from the first adjacent conductive layer, and the first conductive part and the second conductive part further pass through at least the third adjacent conductive layer; In the stacking direction, the first sub-part in the second adjacent conductive layer at least partially overlaps with the first sub-part and the second sub-part in the third adjacent conductive layer, and the second sub-part in the second adjacent conductive layer at least partially overlaps with the first sub-part and the second sub-part in the third adjacent conductive layer.

14. The design method of an integrated circuit according to Claim 13, wherein, The first sub-part and the second sub-part in the third adjacent conductive layer are spaced apart and insulated from each other, and are centrally symmetric with respect to a fourth reference point; The integrated circuit further comprises a second insulating layer between the second adjacent conductive layer and the third adjacent conductive layer, the second insulating layer comprises at least one third via and at least one fourth via, The third via and the fourth via pass through the second insulating layer and are used to set the first connecting part and the second connecting part, The third via and the fourth via are centrally symmetric with respect to a fifth reference point; The first reference point, the second reference point, the third reference point, the fourth reference point and the fifth reference point overlap with each other in the stacking direction; In the stacking direction, the first via in the first insulating layer does not overlap with the third via and the fourth via in the second insulating layer, and the second via in the first insulating layer does not overlap with the third via and the fourth via in the second insulating layer.

15. An integrated circuit comprising a plurality of conductive layers; wherein The plurality of conductive layers are stacked with each other, and at least one insulating layer is arranged between each two adjacent conductive layers to space and insulate the two adjacent conductive layers from each other; The integrated circuit comprises a first conductive part and a second conductive part which are insulated from each other, the first conductive part comprises a plurality of first sub-parts respectively located in different conductive layers and a first connecting part located between the different conductive layers to connect the plurality of first sub-parts, and the second conductive part comprises a plurality of second sub-parts respectively located in different conductive layers and a second connecting part located between the different conductive layers to connect the plurality of second sub-parts; The plurality of conductive layers comprises adjacent first adjacent conductive layer and second adjacent conductive layer, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; In the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-part of the first adjacent conductive layer and the first sub-part and the second sub-part of the second adjacent conductive layer at least partially overlap, and the second sub-part of the first adjacent conductive layer and the first sub-part and the second sub-part of the second adjacent conductive layer at least partially overlap. The integrated circuit further includes a first insulating layer located between the first adjacent conductive layer and the second adjacent conductive layer, and the first connection portion and the second connection portion penetrate the first insulating layer; The applied layout structure is a layout structure that is rotated, flipped, or mirrored relative to the original layout structure plane. The applied layout structure is obtained based on the original layout structure of any one of the first adjacent conductive layer, the second adjacent conductive layer, and the first insulating layer.

16. The integrated circuit of claim 15, wherein, The first sub-part and the second sub-part in the first adjacent conductive layer are spaced apart from each other and insulated from each other, and are arranged in a centrally symmetrical manner with respect to the first reference point; The first sub-part and the second sub-part in the second adjacent conductive layer are spaced apart from each other and insulated from each other, and are arranged in a centrally symmetrical manner with respect to the second reference point; The integrated circuit further includes a first insulating layer located between the first adjacent conductive layer and the second adjacent conductive layer, the first insulating layer including at least one first via and at least one second via. The first via and the second via penetrate the first insulating layer and are respectively used to provide the first connecting portion and the second connecting portion. The first via and the second via are centrally symmetrical about the third reference point; The first reference point, the second reference point, and the third reference point overlap each other in the stacking direction.

17. The integrated circuit of claim 16, wherein, The orthographic projection of the first and second sub-parts in the first adjacent conductive layer onto the reference plane is different from the orthographic projection of the first and second sub-parts in the second adjacent conductive layer onto the reference plane, which is perpendicular to the stacking direction.

18. The integrated circuit of claim 17, wherein, The area enclosed by the orthographic projections of the first sub-part and the second sub-part in the first adjacent conductive layer onto the reference plane has the same size and shape as the area enclosed by the orthographic projections of the first sub-part and the second sub-part in the second adjacent conductive layer onto the reference plane. The size and shape of the region enclosed by the orthographic projection of the first sub-part in the first adjacent conductive layer onto the reference plane are the same as the size and shape of the region enclosed by the orthographic projection of the first sub-part in the second adjacent conductive layer onto the reference plane. The size and shape of the area enclosed by the orthographic projection of the second sub-part in the first adjacent conductive layer onto the reference plane are the same as the size and shape of the area enclosed by the orthographic projection of the second sub-part in the second adjacent conductive layer onto the reference plane.

19. The integrated circuit of claim 17, wherein, The size and shape of the region enclosed by the orthographic projection of the first sub-part in the first adjacent conductive layer onto the reference plane are different from the size and shape of the region enclosed by the orthographic projection of the first sub-part in the second adjacent conductive layer onto the reference plane. A size and a shape of an area enclosed by a projection of the second sub-portion in the first adjacent conductive layer on the reference plane are different from a size and a shape of an area enclosed by a projection of the second sub-portion in the second adjacent conductive layer on the reference plane.

20. An integrated circuit design apparatus comprising: an initial design scheme obtaining unit configured to obtain an initial design scheme of an integrated circuit; and an application design scheme obtaining unit configured to obtain an application design scheme of the integrated circuit based on the initial design scheme; wherein the integrated circuit comprises a plurality of conductive layers, the plurality of conductive layers are arranged in a stack, and at least one insulating layer is arranged between each two adjacent conductive layers to separate and insulate the two adjacent conductive layers from each other; in the initial design scheme, the integrated circuit comprises a first conductive portion and a second conductive portion which are insulated from each other, the first conductive portion comprises a plurality of first sub-portions respectively located in different conductive layers and a first connecting portion located between the different conductive layers to connect the plurality of first sub-portions, the second conductive portion comprises a plurality of second sub-portions respectively located in different conductive layers and a second connecting portion located between the different conductive layers to connect the plurality of second sub-portions; the plurality of conductive layers comprise adjacent first and second adjacent conductive layers, the first conductive portion passes through at least the first and second adjacent conductive layers, and the second conductive portion passes through at least the first and second adjacent conductive layers; in a stacking direction of the first and second adjacent conductive layers, the first sub-portion in the first adjacent conductive layer at least partially overlaps the first and second sub-portions in the second adjacent conductive layer, and the second sub-portion in the first adjacent conductive layer at least partially overlaps the first and second sub-portions in the second adjacent conductive layer; the integrated circuit further comprises a first insulating layer located between the first and second adjacent conductive layers, and the first and second connecting portions penetrate the first insulating layer; wherein the application design scheme obtaining unit is further configured to obtain an application layout structure which is planarly rotated, flipped or mirrored relative to an original layout structure of any one of the first adjacent conductive layer, the second adjacent conductive layer and the first insulating layer.

21. An electronic device comprising: a memory which non-transitorily stores computer-executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the design method of the integrated circuit according to any one of claims 1-14.

22. A non-transitory computer-readable storage medium, wherein, The non-transitory computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by the processor, implement the design method of the integrated circuit according to any one of claims 1-14.

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