Memristor array and method for performing logical operations thereof

Abstract

The embodiment of the application discloses a memristor array and a logic calculation method thereof. The array comprises an operation area, a result area and a controller. The operation area comprises m rows of n columns of first memristors. The result area comprises m rows of n columns of second memristors. Each row of the operation area stores n first logic values. The controller is used for inputting n second logic values to the operation area and controlling the logic operation of the n first logic values of each row and the n second logic values. The logic operation result of the n second logic values and the n first logic values of each row is stored in the n second memristors of each row of the result area. The memristor array has simple structure, can reduce the elements used by a logic operation array, and reduce the area occupied by the array.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a memristor array and a method for performing logical operation thereof. BACKGROUND

[0002] Logical gate is one of the most basic elements of computer, and is a basic unit for performing computing function. With the continuous development of CMOS (complementary metal oxide semiconductor) technology and process, the size of chip is getting smaller and smaller, and the function is getting more and more powerful. However, the CMOS technology has reached many limits, which seriously limits the further development of chip and computer, especially in size, speed and power consumption.

[0003] Taking XOR gate (XOR) logic circuit as an example, XOR is a basic logic circuit in digital circuit. XOR gate logic circuit is combined with other logic circuits (such as OR gate, NAND gate, etc.) in digital circuit to complete complex logical operation. The current XOR gate logic circuit mainly includes a plurality of CMOS devices connected together. The current XOR gate logic circuit includes 12 CMOS devices. Further, for the array for inter-sequence logical operation composed of CMOS devices, since a plurality of CMOS devices are needed, the array occupies a large area and has high power consumption. In addition, the result of the calculation performed by the CMOS array needs to be saved in another storage setting. SUMMARY

[0004] The embodiments of the present application disclose a memristor array and a method for performing logical operation thereof, which are used for reducing the occupied area and power consumption of the logical operation array composed of CMOS devices, and realizing storage and calculation integration.

[0005] To achieve the above object, the present application provides a memristor array in one aspect, which comprises: an operation area, a result area and a controller, the operation area comprises m rows of n columns of first memristors, the result area comprises m rows of n columns of second memristors, each row of the operation area stores n first logic values, and the controller is used for inputting n second logic values to the operation area and controlling logical operation of the n first logic values of each row and the n second logic values, and the logical operation result of the n second logic values and the m first logic values of each row is stored in n second memristors of each row of the result area.

[0006] Due to the characteristics of storage and calculation integration of memristor, the logical operation is realized by the memristor array, the area occupied by the logical operation array composed of COMS devices is reduced, and the power consumption of the array is reduced.

[0007] In a specific embodiment, the first and second memristors of each row are connected to a word line through the same polarity of one pole, the other pole of each column of first memristors and each column of second memristors is connected to a bit line, each row of word lines is connected to one end of a constant resistance, each column of bit lines is connected to a controller, and the other end of the constant resistance is connected to the controller;

[0008] The resistance value of each row of first memristors in the operation area represents n first logic values subjected to logical operation;

[0009] The controller, when inputting n second logic values to the operation area, is specifically configured to convert m second logic values subjected to logical operation into n first voltages respectively, and input the n first voltages into the n first memristors respectively, the first voltage being lower than the threshold voltage of the memristor changing from a high resistance state to a low resistance state and the threshold voltage of the memristor changing from a low resistance state to a high resistance state;

[0010] The controller, when used to control the logical operation of n first logic values and n second logic values of each row, is specifically configured to:

[0011] Input n second voltages to the n second memristors;

[0012] Input a third voltage to the constant resistance, the third voltage being a voltage corresponding to a logic value obtained by performing logical NOT operation on the second logic value;

[0013] The controller is further configured to determine the logical operation result of n first logic values and n second logic values of each row according to the resistance value of n second memristors of each row in the result area.

[0014] In a specific embodiment, the controller is further configured to input a fourth voltage to the n second memristors, and determine the Hamming distance of the logical operation result of the first logic value and the second logic value of each row according to the output current of the n second memristors.

[0015] By converting the logical operation result represented by the resistance value of n second memristors into the Hamming distance between the logical operation sequence represented by the output current, the speed of the controller in the array to obtain the Hamming distance of logical operation is accelerated, and compared with the occupied area of the circuit structure for reading resistance in the related art, the occupied area of the array is reduced by reading current.

[0016] In a specific embodiment, the controller is further configured to input a fourth voltage to the n second memristors, and the array further comprises a trans-impedance amplifier connected in parallel with the fixed resistor, the trans-impedance amplifier being configured to convert the output current of each row of word lines after inputting the fourth voltage into an output voltage in a proportional manner and transmit the output voltage to the controller, and the controller is configured to determine the Hamming distance of the logical operation result of each row of the n first logic values and the n second logic values according to the output voltage of each row of the trans-impedance amplifier.

[0017] The Hamming distance between the logical operation sequences represented by the output voltage of the trans-impedance amplifier accelerates the speed of the controller in obtaining the Hamming distance of the logical operation, and compared with the area occupied by the circuit structure for reading the resistance in the related art, reading the voltage reduces the area occupied by the array.

[0018] In a specific embodiment, the array further comprises a voltage comparator, two input terminals of the voltage comparator being connected to the controller and the trans-impedance amplifier respectively, and an output terminal of the voltage comparator being connected to the controller, the output voltage of the trans-impedance amplifier being used as a first input voltage of the voltage comparator, the controller converts the target Hamming distance set by the controller into a second input voltage of the voltage comparator, the voltage comparator compares the first input voltage and the second input voltage and outputs the comparison result to the controller through the output terminal, and the controller determines the size relationship between the Hamming distance of the logical operation result output by each row of word lines and the target Hamming distance set by the controller according to the comparison result.

[0019] Further comparing the Hamming distance between the logical operation sequences with the target Hamming distance accelerates the speed of the controller in obtaining the logical operation result.

[0020] In a specific embodiment, the array further comprises an A / D converter, two terminals of the A / D converter being connected to the controller and the trans-impedance amplifier respectively, the A / D converter being configured to convert the output voltage of the trans-impedance amplifier into a digital signal and send the digital signal to the controller, and the controller is configured to determine the Hamming distance of the logical operation result output by each row of word lines according to the digital signal.

[0021] Converting the Hamming distance between the logical operation sequences into a digital signal by the A / D converter reduces the processing process of the controller on the signal.

[0022] In a specific embodiment, the array further comprises an inverter, two terminals of the inverter being connected to the controller and the fixed resistor respectively, and the inverter is configured to generate the third voltage input by the controller.

[0023] By the inverter, the controller reduces the processing procedure of converting the second voltage into the third voltage, and reduces the load of the controller.

[0024] The second aspect of the present application provides a method for performing logical operation in a memristor array, the memristor array comprising an operation area, a result area and a controller, the operation area comprising m rows of n columns of first memristors, the result area comprising m rows of n columns of second memristors, each row of the operation area storing n first logic values, the method comprising: the controller inputting n second logic values to the operation area; the controller controlling logical operation of each row of n first logic values and the n second logic values, and storing the logical operation results of the n second logic values and each row of n first logic values in each row of n second memristors in the result area.

[0025] In a specific embodiment, the first memristor and the second memristor of each row are connected to a word line through the same polarity of one pole, the first memristor of each column and the second memristor of each column are connected to a bit line through the other pole, each row of word lines is connected to one end of a constant resistance, each column of bit lines is connected to the controller, the other end of the constant resistance is connected to the controller, and the resistance value of each row of first memristors in the operation area represents n first logic values for logical operation.

[0026] The n second logic values inputted to the operation area comprise:

[0027] The n second logic values for logical operation are respectively converted into n first voltages, and the n first voltages are respectively inputted to the n first memristors, wherein the first voltages are lower than the threshold voltage of the change from high resistance state to low resistance state of the memristor and the threshold voltage of the change from low resistance state to high resistance state of the memristor.

[0028] The logical operation of each row of n first logic values and the n second logic values comprises:

[0029] n second voltages are inputted to the n second memristors.

[0030] A third voltage is inputted to the constant resistance, wherein the third voltage is the voltage corresponding to the logic value obtained by performing logical NOT operation on the second logic value.

[0031] The logical operation results of each row of n first logic values and n second logic values are determined according to the resistance values of each row of n second memristors in the result area.

[0032] In a specific embodiment, the method further comprises: the controller inputting a fourth voltage to the n second memristors, and determining the Hamming distance of the logical operation results of each row of first logic values and second logic values according to the output current of each row of n second memristors.

[0033] In a specific embodiment, the method further comprises that the controller inputs a fourth voltage to the n second memristors, the memristor array further comprises: a trans-impedance amplifier connected in parallel with the fixed resistor, the trans-impedance amplifier is configured to: convert the output current of each row of word lines after inputting the fourth voltage into an output voltage in a proportional manner and transmit to the controller, and the controller is configured to determine the Hamming distance of the logical operation result of the n first logic values and the n second logic values of each row according to the output voltage of the trans-impedance amplifier of each row.

[0034] In a specific embodiment, the array further comprises: the array further comprises: a voltage comparator, two input terminals of the voltage comparator are connected with the controller and the trans-impedance amplifier respectively, and an output terminal is connected with the controller, the output voltage of the trans-impedance amplifier is used as the first input voltage of the voltage comparator, the controller converts the target Hamming distance set by the controller into the second input voltage of the comparator, the comparator compares the first input voltage and the second input voltage, and outputs the comparison result to the controller through the output terminal, and the controller determines the size relationship between the Hamming distance of the logical operation result output by each row of word lines and the target Hamming distance set by the controller according to the comparison result.

[0035] In a specific embodiment, the array further comprises: the array further comprises: an A / D converter, two terminals of the A / D converter are connected with the controller and the trans-impedance amplifier respectively, and the A / D converter is configured to convert the output voltage of the trans-impedance amplifier into a digital signal and send the digital signal to the controller, and the controller determines the Hamming distance of the logical operation result output by each row of word lines according to the digital signal.

[0036] In a specific embodiment, the array further comprises: an inverter, two terminals of the inverter are connected with the controller and the fixed resistor respectively, and the inverter is configured to generate the third voltage input by the controller.

[0037] The third aspect of the present application provides a chip, the chip comprising the memristor array of the first aspect.

[0038] The fourth aspect of the present application provides a computing device, the computing device comprising the memristor array of the first aspect or the chip of the third aspect. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 A logic gate device according to an embodiment of the present application is shown;

[0041] Figures 2a-2d Show Figure 1 The specific implementation principle of the logic gate of the logic gate device;

[0042] Figure 3 Show Figure 1 Method of implementing logical operations using logic gate devices in a

[0043] Figure 4a The memristor array of an embodiment of the present application is shown;

[0044] Figure 4b Another memristor array according to an embodiment of the present application is shown;

[0045] Figure 5 Show Figure 4a Flowchart of logic operation implemented by memristor array;

[0046] Figure 6a Show Figure 4a A specific implementation of the Hamming distance calculation of the logical results of the first row of word lines;

[0047] Figure 6b Show Figure 4a Another specific implementation of the Hamming distance calculation of the logical result of the first row of word lines;

[0048] Figure 6c Show Figure 4a Another specific implementation of the Hamming distance calculation of the logical result of the first row of word lines;

[0049] Figure 7a A specific implementation of the Hamming distance calculation array is shown;

[0050] Figure 7b Another specific implementation of the Hamming distance calculation array is shown;

[0051] Figure 7c Another specific implementation of the Hamming distance calculation array is shown; DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0053] In view of the large size and large power consumption of the logic operation array realized by CMOS, the embodiment of the present application proposes a logic operation array based on a memristor array. Since the logic gate realized by the memristor device has the characteristics of integration of storage and calculation, the size of the logic operation array can be reduced, and the power consumption of the array can be further reduced by realizing the logic operation through the memristor array.

[0054] The basic element constituting the embodiment of the present application is a memristor. The memristor, also known as a memory resistor, is a resistor with a memory resistance function. The memristor is a bipolar device including a positive electrode and a negative electrode. The resistance of the memristor changes with the change of the voltage applied between the positive electrode and the negative electrode of the memristor. When a forward voltage is applied between the positive electrode and the negative electrode of the memristor, if the value of the forward voltage is less than the value of the starting voltage corresponding to the memristor, the resistance of the memristor remains unchanged. If the value of the forward voltage applied to the memristor is greater than the value of the starting voltage and less than the value of the first threshold voltage, the greater the value of the applied forward voltage, the smaller the resistance of the memristor. If the value of the forward voltage applied to the memristor is greater than or equal to the value of the first threshold voltage Vrl, the resistance of the memristor will decrease to a minimum value and will no longer change, i.e. the memristor is in a low resistance state. When a negative voltage is applied between the positive electrode and the negative electrode of the memristor, if the value of the negative voltage is less than the value of the starting voltage, the resistance of the memristor remains unchanged. If the negative voltage applied to the memristor is greater than the starting voltage and the negative voltage is less than the second threshold voltage, the greater the negative voltage applied, the greater the resistance of the memristor. When the negative voltage applied to the memristor is greater than or equal to the second threshold voltage Vrh, the resistance of the memristor will increase to a maximum value and will no longer change, i.e. the memristor is in a high resistance state. When the voltage applied between the positive electrode and the negative electrode of the memristor is removed, the memristor will maintain the resistance value when the positive and negative electrodes are removed, thereby achieving the function of "remembering" the resistance value. The forward voltage and the negative voltage refer to the voltage difference between the voltage applied to the positive electrode of the memristor and the voltage applied to the negative electrode of the memristor. When the voltage difference is positive, it means that a forward voltage is applied between the positive electrode and the negative electrode of the memristor. When the voltage difference is negative, it means that a negative voltage is applied between the positive electrode and the negative electrode of the memristor.

[0055] The memristor array of the present application is based on a memristor XOR gate device. The memristor logic gate device is a logic circuit that performs XOR operation on two input logic values. First, the memristor logic gate device is introduced:

[0056] The logic value input by each input terminal can be any one of 0 or 1. If the two logic values input by the XOR gate device are A and B of the above-mentioned device, the truth table of the XOR operation is shown in Table 1.

[0057] Table 1

[0058] Input A Input B Output C 0 0 0 0 1 1 1 0 1 1 1 0 ​

[0059] In the embodiment of the present application, the high resistance state of the memristor represents logic 1, the low resistance state of the memristor represents logic 0, the high level of the input voltage represents logic 1, and the low level of the input voltage represents logic 0. When the input voltage is greater than the third threshold voltage, the input voltage is high level, and when the input voltage is less than the third threshold voltage, the input voltage is low level.

[0060] Firstly, the present application will be described by the implementation of the XOR gate device by using the memristor. The circuit diagram is shown in Fig. 1. Figure 1 The XOR gate device 1 comprises a first memristor 10, a second memristor 20, a constant resistance 40 and a controller 30. The positive electrodes 101, 201 of the first memristor 10 and the second memristor 20 are connected to the output terminals 301, 302 of the controller 30; the negative electrodes 102, 202 of the first memristor 10 and the second memristor 20 are connected and connected to one end 401 of the constant resistance 40; the other end 402 of the constant resistance is connected to the controller 30.

[0061] In the embodiment of the present application, the first logic value for the XOR logic operation is converted into the resistance value of the first memristor 10, and the second logic value for the XOR logic operation is converted into the voltage input into the first memristor 10. According to the different logic values for the logic operation, different resistances and voltages are input into the first memristor, so that the resistance value of the second memristor changes differently, and the result of the XOR operation can be determined by reading the resistance value of the second memristor. After the above conversion relationship, the XOR logic in Table 1 becomes the expression in Table 2:

[0062] Table 2

[0063]

[0064] Hamming distance: Hamming distance is a concept used in error control coding for data transmission, which represents the number of corresponding bit differences between two (same length) sequences. We use d(x, y) to represent the Hamming distance between two words x and y. XOR operation is performed on two strings, and the number of results of 1 is counted, which is the Hamming distance. Hamming weight is the Hamming distance of a string relative to a zero string of the same length, that is, it is the number of non-zero elements in the string: for a binary string, it is the number of 1s, so the Hamming weight of 11101 is 4.

[0065] Next, how to implement the XOR gate device by using the circuit shown in Fig. 2 will be described in detail. Figure 1

[0066] ​When it is required to represent logic 1 by the first memristor 10, the controller inputs a negative voltage greater than the second threshold voltage to the first memristor 10, so that the first memristor is in a high resistance state, and when it is required to represent logic 0 by the first memristor 10, the controller inputs a positive voltage greater than the first threshold voltage to the first memristor 10, so that the first memristor is in a low resistance state.

[0067] In practical applications, the first memristor 10 is generally used to store data. For example, if the data stored by the first memristor 10 is 1, the first memristor is set to a high resistance state, and if the data stored by the first memristor 10 is 0, the first memristor is set to a low resistance state.

[0068] In the embodiment of the present application, the voltage value corresponding to the high level and the voltage value corresponding to the low level are respectively preset in the controller 30. When the controller 30 receives the second logic value for logic operation, the second logic value is converted into the voltage value corresponding to the level of the second logic value, i.e. the first voltage value. For example, when the second logic value is 1, the controller 30 converts the logic value into the voltage VH corresponding to the high level, and inputs the voltage corresponding to the high level to the first memristor 10, and when the controller 30 receives the second logic value for logic operation, the controller 30 converts the logic value into the voltage VL corresponding to the low level, and inputs the voltage corresponding to the low level to the first memristor 10. The voltage value corresponding to the high level and the voltage value corresponding to the low level are both less than the first voltage threshold and the second threshold for changing the resistance of the memristor, so that the resistance of the first memristor can be prevented from changing after the input voltage VH or VL is applied to the first memristor.

[0069] In practical applications, when the data represented by the first logic value has been stored by the resistance of the memristor 10, if it is required to compare whether the data represented by the second logic value is consistent with the data represented by the first logic value which has been stored, the second logic value is input to the controller 30, the control circuit 30 converts the second logic value into the corresponding voltage, and then determines the exclusive or operation result of the first logic value and the second logic value according to the resistance state of the second memristor after the input voltage, and determines whether the first logic value and the second logic value are consistent according to the exclusive or operation result.

[0070] In the embodiment of the present application, first, a negative voltage greater than the second voltage threshold is input to the second memristor to initialize the second memristor to a high resistance state, and when a logic operation is needed, a second voltage VCC is input to the second memristor, the second voltage is a steady voltage, and the voltage value of the steady voltage VCC is greater than the first threshold voltage for changing the memristor from the high resistance state to the low resistance state, so as to ensure that the resistance state of the second memristor 20 can be reversed during the logic operation.

[0071] The controller 30 also inputs a third voltage corresponding to the logic value after the non-operation of the second logic value to the fixed resistor 40. For example, when the second logic value is 1, the controller inputs a voltage corresponding to the logic value 0 to the fixed resistor 40, and when the second logic value is 0, the controller inputs a voltage corresponding to the logic value 1 to the fixed resistor 40. The purpose of inputting the voltage to the fixed resistor 40 is to change the voltage difference between the two ends of the second memristor when the input of the first memristor changes, and to determine whether the second memristor changes from the high resistance state to the low resistance state according to the voltage difference of the second memristor, so as to determine the output of the exclusive or logic operation. For how to change the resistance value of the second memristor after the first voltage, the second voltage, and the third voltage are input, so as to determine the result of the logic operation according to the resistance value of the second memristor, please refer to the description of Figures 2a-2d .

[0072] In the embodiment of the present application, the resistance value of the first memristor in the high resistance state is much greater than the resistance value of the fixed resistor 40, so that the resistance value of the fixed resistor 40 relative to the high resistance state can be ignored, and the resistance value of the first memristor in the low resistance state is much smaller than the resistance value of the fixed resistor 40, so that the resistance value of the low resistance state relative to the resistance value of the fixed resistor 40 can be ignored.

[0073] The controller 30 is used to determine the logic operation result according to the resistance value of the second memristor 20. In actual application, the controller determines the result of the logic operation according to the resistance value of the second memristor specifically as follows: when the resistance value of the second memristor is in the high resistance state, it is determined that the result of the logic operation is logic 1, and when the resistance value of the second memristor is in the low resistance state, it is determined that the result of the logic operation is logic 0.

[0074] In the embodiment of the present application, the manner of determining the logic result according to the resistance value is not limited to the following manner: the second voltage is adjusted to a fourth voltage, the fourth voltage does not cause a change in the resistance value of the second memristor, and the absolute value of the fourth voltage is less than the first threshold voltage Vrl and the second threshold voltage Vrh; and the current value of the second memristor is read. According to Ohm's law, when the voltage is constant, the current is negatively correlated with the value of the resistance; due to the characteristics of the memristor, when the second memristor is in the high-resistance state, the current value thereof is small, and when the second memristor is in the low-resistance state, the current value thereof is large, and the size of the current value can be used to determine the size of the resistance value, and then the output of the corresponding logic gate is determined.

[0075] In order to ensure that the resistance value of the fixed resistor is between the resistance values of the high-resistance state and the low-resistance state of the memristor, and when the fixed resistor and the high-resistance state memristor form a series circuit, the voltage division is not obvious; and when the fixed resistor and the low-resistance state memristor form a series circuit, the voltage division is obvious, and the resistance value of the fixed resistor is preferably the square root of the product of the high-resistance value and the low-resistance value of the memristor.

[0076] In actual application, the implementation manner of the negative third voltage is specifically but not limited to the following manner: the first voltage is implemented through an inverter or a CMOS NOT gate.

[0077] The following will be described in detail how to determine the result of the exclusive OR operation of the first logic value and the second logic value according to the resistance state of the second memristor 20 after the resistance value of the first memristor is set to the first logic value and the input voltage corresponding to the second logic value, that is, the comparison result of whether the first logic value and the second logic value are consistent.

[0078] Figures 2a-2d The implementation process of the exclusive OR logic is as follows:

[0079] The following implementation of the exclusive OR logic is based on the premise that the resistance value of the first memristor is set to the resistance value corresponding to the first logic value, the resistance value of the second memristor is set to the resistance value corresponding to the high-resistance state, and the controller 30 simultaneously applies the first voltage, the second voltage, and the third voltage to the corresponding ports 101, 201, and 402, so that the third logic value corresponding to the exclusive OR logic operation result can be output by the resistance value of the second memristor.

[0080] As Figure 2aAs shown, if the first logic value A for the logical operation is 0, the first memristor 10 is set to a low resistance state, and if the second logic value B for the logical operation is 0, the first voltage VL corresponding to the low level is input to the positive electrode 101 of the first memristor, and at the same time, the second voltage VCC is input to the second memristor, and the third voltage VH corresponding to the logic value 1 after the non-operation of the first logic value A is input to the fixed resistor. Since the first memristor 10 and the fixed-value resistor 40 are connected in series, and the resistance of the first memristor 10 is much smaller than that of the fixed-value resistor 40, the resistance of the first memristor 10 can be ignored relative to the resistance of the fixed-value resistor 40. Thus, according to the principle of voltage division in a series circuit, the fixed-value resistor 40 divides almost all the voltage, and the voltage drop of the first memristor 10 can be ignored. Then, the voltage of the negative electrode 202 of the second memristor 20 is approximately equal to the third voltage VL, and the voltage drop of the second memristor 20 is VCC minus VL, and VCC minus VL is greater than the first threshold voltage, thereby converting the second memristor 20 from a high-resistance state to a low-resistance state, which means that the result of the exclusive-OR operation of the first logic value 0 and the second logic value 0 is a logic value 0, which is consistent with the XOR gate. The results are consistent.

[0081] like Figure 2b As shown, if the first logic value A for the logic operation is 0, the first memristor 10 is set to a low resistance state, and if the second logic value B for the logic operation is 1, the first voltage VH corresponding to the high level is input to the positive electrode 101 of the first memristor, and at the same time, the second voltage VCC is input to the second memristor, and the third voltage VL corresponding to the logic value 0 after the first logic value is not operated is input to the fixed resistor. Since the first memristor 10 and the fixed-value resistor 40 are connected in series, and the resistance of the first memristor 10 is much smaller than the resistance of the fixed-value resistor 40, that is, the resistance of the first memristor is negligible relative to the resistance of the fixed-value resistor 40, then, according to the principle of voltage division in a series circuit, the fixed-value resistor 40 divides almost all the voltage, and the divided voltage drop of the first memristor 10 is negligible, then the voltage of the negative electrode 202 of the second memristor is approximately equal to the third voltage VH, then the voltage drop of the second memristor is VCC minus VH, and VCC minus VH is less than the first threshold voltage, and the resistance of the second memristor 20 is still in a high-resistance state, which means that the result obtained after the first logic value 0 and the second logic value 1 are XORed is logic value 1, which is consistent with the XOR gate. The results are consistent.

[0082] like Figure 2cAs shown, if the first logic value A for the logic operation is 1, the first memristor 10 is set to a high-impedance state, and if the second logic value B for the logic operation is 0, the first voltage VL corresponding to the low level is input to the positive electrode 101 of the first memristor, and at the same time, the second voltage VCC is input to the second memristor, and the third voltage VH corresponding to the logic value 1 after the first logic value is not operated is input to the fixed resistor. Since the first memristor 10 and the fixed resistor 40 are connected in series, and the resistance of the fixed resistor 40 is much smaller than that of the first memristor 10, the resistance of the fixed resistor 40 can be ignored relative to the resistance of the first memristor. Thus, according to the principle of voltage division in a series circuit, the first memristor 10 divides almost all the voltage, and the voltage drop of the fixed resistor 40 can be ignored. Then the voltage of the negative electrode 202 of the second memristor is approximately equal to the third voltage VH, and the voltage drop of the second memristor is VCC minus VH, and VCC minus VH is less than the first threshold voltage. The resistance of the second memristor 20 is still in a high-resistance state, which means that the result obtained after the first logic value 1 and the second logic value 0 are XORed is logic value 1, which is consistent with the XOR gate. The results are consistent.

[0083] like Figure 2d As shown, if the first logic value A for the logic operation is 1, the first memristor 10 is set to a high-impedance state, and if the second logic value B for the logic operation is 1, the first voltage VH corresponding to the high level is input to the positive electrode 101 of the first memristor, the second voltage VCC is input to the second memristor, and the third voltage VL corresponding to the logic value 0 after the first logic value is not operated is input to the fixed resistor. Since the first memristor 10 and the fixed-value resistor 40 are connected in series, and the resistance of the first memristor 10 is much greater than the resistance of the fixed-value resistor 40, the resistance of the fixed-value resistor 40 is negligible relative to the resistance of the first memristor. Thus, according to the principle of voltage division in a series circuit, the voltage drop of the fixed-value resistor is negligible, and the voltage of the negative electrode of the second memristor is approximately equal to the third voltage VL. The voltage drop of the second memristor is VCC minus VL, and VCC minus VL is greater than the second threshold voltage, thereby converting the second memristor from a high-resistance state to a low-resistance state, which means that the result obtained after the first logic value 1 and the second logic value 1 are subjected to an XOR operation is a logic value 0, which is consistent with the XOR gate. The results are consistent.

[0084] Figure 3 The specific steps of the method for implementing logic operation of the logic gate device of the first embodiment of the present application include: Figure 1The logic gate device comprises a first memristor 10, a second memristor 20, a constant resistor 40 and a controller 30. The positive poles 101 and 201 of the first and second memristors 10 and 20 are connected with the output ends 301 and 302 of the controller 30; the negative poles 102 and 202 of the first and second memristors 10 and 20 are connected and connected with one end 401 of the constant resistor 40; the other end 402 of the constant resistor is connected with the controller 30; and the method comprises the following steps:

[0085] In step S301, the controller 30 sets the resistance value of the first memristor according to the first logic value of the logic operation.

[0086] In step S302, the controller 30 converts the second logic value B for logic operation into a first voltage, and inputs the first voltage into the positive pole 101 of the first memristor 10, wherein the first voltage is lower than the threshold voltage for changing the high resistance state of the memristor into the low resistance state and the threshold voltage for changing the low resistance state into the high resistance state.

[0087] In step S303, the controller 30 inputs a second voltage into the second memristor 20, wherein the second voltage is higher than the threshold voltage.

[0088] In step S304, the controller 30 inputs a third voltage into the constant resistor 40, wherein the third voltage is the voltage corresponding to the logic value obtained by performing logic NOT operation on the second logic value.

[0089] The third voltage is set corresponding to the first voltage, so that the voltage difference between the first memristor and the constant circuit in series is constant, thereby facilitating the constant control of the subsequent voltage division of the circuit and obtaining the corresponding output result smoothly.

[0090] In step S305, the controller 30 determines the logic operation result C according to the resistance value of the second memristor 20.

[0091] By Figures 1-3 The basic device of the memristor for realizing the XOR gate in the embodiment of the application is introduced, and then the method for realizing the logic operation based on the memristor array in the application is introduced.

[0092] Combined Figure 4a The structure of the memristor array in the application is introduced.

[0093] Figure 4a The structure of the array 400 is a simplified diagram, and the array 400 comprises m*n memristors in the operation area and m*n memristors in the result area. Figure 1 The circuit in the array 400 comprises the m*n memristors in the operation area, the m*n memristors in the result area, the controller 30 and the m constant resistors 40.

[0094] The memristors in the operation area and the memristors in the result area of ​​each row of the array 400 are connected by a pole with the same polarity ( Figure 4a The negative electrodes of the memristors in the operation area and the result area are connected to the word lines, and the other electrodes of the first memristors in each column and the second memristors in each column are connected to the word lines. Figure 4a The positive electrodes of the memristors in the operation area and the result area are connected to the bit lines, each row of word lines is connected to one end of the fixed resistor 40, each column of bit lines is connected to the controller 30, and the other end of the fixed resistor 40 is connected to the controller 30. Figure 4a The array can realize the logical operation of m first sequences and second sequences. The specific operation implementation process is as follows Figure 5 The flowchart is shown in FIG.

[0095] Taking a row in the array as an example, the n memristors 11-1n in the operation area function as follows: Figure 1 The memristor 10 in the result area is used for inputting two logic values ​​for XOR operation; the n memristors 21-2n in the result area are equivalent to Figure 1 Memristor 20 in the memory is used to output the logical value of the exclusive-OR operation. Each memristor in the operation area corresponds one-to-one with a memristor in the result area. Specifically, memristor 11 corresponds to memristor 21, memristor 12 corresponds to memristor 22, and so on. Memristor 1n corresponds to memristor 2n. The correspondence between the memristors in the operation area and the result area, specifically the correspondence between the memristor identifiers, is stored in controller 30.

[0096] The process of performing logic operations of the array 400 is as follows: Figure 5 shown.

[0097] In step S501 , the controller 30 sets the resistance value of the memristor in each row of the operation area according to m first sequences.

[0098] As a first example, the controller 30 sets the resistance values of the n memristors in the operation area according to the n logic values in the first sequence of the m first sequences. Specifically, the controller 30 sets the resistance values of each memristor in the operation area according to the logic values in the first sequence, and sets each memristor in the result area to a high resistance state. When the memristor 1i (1i represents the i-th memristor in the operation area, 1<=i<=n) in the operation area is required to represent logic 1, the controller 30 inputs a negative voltage greater than the second threshold voltage to the memristor 1i, so that the memristor 1i is in a high resistance state, and when the memristor 1i is required to represent logic 0, the controller 30 inputs a positive voltage greater than the first threshold voltage to the first memristor 10, so that it is in a low resistance state. After step S501, the n first logic values A1-An are stored in the memristors in the operation area, and the n first logic values A1-An are represented by the resistance values R11-R1n of the n memristors 11-1n. The n first logic values A1-An stored constitute a first sequence. The resistance values of each memristor 21-2n in the result area are set to a high resistance value. Specifically, the memristors 21-2n are inputted with a negative voltage greater than the second voltage threshold Vrh to initialize the second memristor to a high resistance state.

[0099] The second to m-th rows of the array 400 store the second to m-th first sequences, respectively, and the setting process is the same as that of the first row, which will not be described herein.

[0100] It should be explained that when the controller sets the resistance values of each memristor in the operation area, it is set by row. When setting the resistance values of the memristors in each row of the operation area, it is considered that the controller 30 applies a negative voltage greater than the first threshold voltage or the second threshold voltage to the bit line, which will simultaneously set the resistance values of the memristors in the same column position of other rows. Therefore, the array sets a blocking mechanism between rows. For example, a conduction switch (not shown in FIG. 4) can be provided on the word line of each row, and the controller 30 controls the conduction switch to ensure that when the resistance values of the memristors in the operation area are set by row, the resistance values of the memristors in the operation area of the other rows in the same column will not be affected.

[0101] Optionally, the resistance values of the memristors in the operation area can be set and then connected as Figure 4a the memristor array shown.

[0102] Step S502, the controller 30 controls the logical operation of each row of n first logic values and n second logic values.

[0103] Specifically, the controller 30 applies the voltages meeting the conditions to the bit lines of the resistive memories in each column of the operation area and the bit lines of the resistive memories in each column of the result area and the constant resistance in sequence according to the logic values of the second sequence. The controller 30 converts the n second logic values B1-Bn into first voltages V11-V1n in sequence and applies the first voltages to the bit lines of the resistive memories in the operation area in sequence. Meanwhile, the controller 30 inputs third voltages V11'-V1n' to the m constant resistances 40 in sequence, the third voltages being the voltages corresponding to the logic values obtained by performing logical NOT operation on the second logic values. Meanwhile, the controller 30 inputs second voltages VCC to the bit lines of the resistive memories in the result area in sequence. Specifically, the steps S502 are performed in sequence according to a period T. At time T, the controller 30 applies the first voltage V11 corresponding to the first logic value B1 of the sequence B1-Bn to the bit lines of the resistive memories in the first column of the operation area, applies the voltage V11' corresponding to the logic value obtained by performing logical NOT operation on B1 to the constant resistance 40, and applies VCC to the bit lines of the resistive memories in the first column of the result area. At time 2T, the controller 30 applies the first voltage V12 corresponding to the second logic value B2 of the sequence B1-Bn to the bit lines of the resistive memories in the second column of the operation area, applies the voltage V12' corresponding to the logic value obtained by performing logical NOT operation on B2 to the constant resistance 40, and applies VCC to the bit lines of the resistive memories in the second column of the result area. At time nT, the controller 30 applies the first voltage V1n corresponding to the n-th logic value Bn of the sequence B1-Bn to the bit lines of the resistive memories in the n-th column of the operation area, applies the voltage V1n' corresponding to the logic value obtained by performing logical NOT operation on Bn to the constant resistance 40, and applies VCC to the bit lines of the resistive memories in the n-th column of the result area.

[0104] It should be explained that, since the n resistive memories in each row of the operation area and the resistive memories in the result area share one constant resistance, when the step S502 is performed, the controller 30 needs to apply different voltages to the constant resistance 40 for the operation of the resistive memories in each row of the operation area and the resistive memories in the result area. Since the m resistive memories in one column are connected in parallel and do not affect each other, the present application can only perform one column of XOR operation at a time.

[0105] In actual application, an inverter 60 is connected between the constant resistance 40 and the controller 30 in FIG. 4, as shown in FIG. 5. Figure 4b In the step S502, the controller 30 directly inputs the voltage values V11-V1n corresponding to the logic values of the second sequence to the inverter 60 through the inverter. Under the action of the inverter 60, the m constant resistances receive the third voltages V11'-V1n', the third voltages being the voltages corresponding to the logic values obtained by performing logical NOT operation on the second logic values.

[0106] Step S503, the controller 30 determines m*n logic operation results according to the resistance values of the m*n result area memristors.

[0107] The controller 30 reads the resistance values of the m*n result area memristors to determine the m*n logic operation results, specifically, the high resistance state represents the operation result as 1, and the low resistance state represents the operation result as 0. Further, the controller 30 obtains the Hamming distance between each first sequence and second sequence in the sequence by counting the number of 1s (i.e. Hamming weight) in each row of the operation result.

[0108] Since the design of the device for obtaining the resistance value in the array is relatively complex, further, the present application converts the resistance value of the result area memristor into an output current or an output voltage, and determines the Hamming distance of the logic operation results of different rows of the result area through the output current or the output voltage.

[0109] Specifically, after step S502, the controller 30 applies a fourth voltage to the m memristors in each column of the result area, and obtains an output current on the m word lines, and sends the output current to the controller 30, and the controller obtains the Hamming distance corresponding to the output current according to the matching relationship between the output current and the target current in the controller. Before step S501, a preset output current interval corresponding to the Hamming distance of the logic operation result is set in the controller 30, which is used to determine the Hamming distance corresponding to the output current. It should be noted that the absolute value of the fourth voltage is less than the values of the first threshold voltage Vrl and the second threshold voltage Vrh, so as to ensure that the resistance value of the result area memristor does not change.

[0110] Further, after the output current, the output current of the result area memristor word line is converted into an output voltage in proportion and sent to the controller 30, and different Hamming distances are obtained in the controller 30 through different output voltages. Specifically, taking the first row as an example, as shown in Figure 6a , after step S502 is completed (i.e. after the exclusive OR operation is performed on each bit of the two sequences), the Hamming distance of the logic operation result is obtained through the circuit of Figure 6a . Different from the first row of Figure 4a , the Figure 6a increases a transimpedance amplifier component 50, as shown in Figure 6aThe components shown in the dashed box. The trans-impedance amplifier includes a resistor 51, an amplifier 52, for converting current to voltage in proportion. The trans-impedance amplifier 50 is connected in parallel with the fixed resistor 40, and optionally, the fixed resistor 40 can be switched to the trans-impedance amplifier 50 by adding a selection circuit after step S502. After step S502, the n logical operation results C1-Cn are saved in the resistance values R21-R2n of the memristors in the result area. When step S502 is completed, the fourth voltage is applied to the anodes 3021-302n of the memristors in the result area at the same time, and the output currents of the memristors 21-2n are collected by the trans-impedance amplifier 50 and converted to an output voltage in proportion, and sent back to the controller 30. In step S501, a preset voltage interval is set in the controller 30, which corresponds to the Hamming distance of the logical operation result, for judging the Hamming distance of the logical operation result corresponding to the output voltage of the trans-impedance amplifier. For the logical operation of multiple rows at the same time, as shown in Figure 7a , the output voltage corresponding to the Hamming distance of the logical operation of each row is sent to the controller by the trans-impedance amplifier of each row, and the Hamming distance of the logical operation result of each row is obtained by the controller.

[0111] Further, as shown in Figure 6b , a voltage comparator 53 can be added after the trans-impedance amplifier 50, which includes two input terminals and an output terminal, the two input terminals are connected to the controller 30 and the trans-impedance amplifier respectively, and the output terminal is connected to the controller 30. Before step S501, the controller 30 inputs a preset target voltage into the voltage comparator 53, which is used to compare the size of the output voltage of the trans-impedance amplifier with the preset target voltage. When the output voltage of the trans-impedance amplifier 50 in the result area is output to the voltage comparator in step S503, the voltage comparator compares the target voltage and outputs the result to the controller 30. For example, the lengths of the first sequence and the second sequence are 8, and the controller 30 inputs the target voltage corresponding to the Hamming distance 4 into the voltage comparator 53. After comparing the voltage output by the trans-impedance amplifier in the result area with the voltage corresponding to the Hamming weight 4 in the voltage comparator, the voltage comparator 53 outputs the comparison result, such as the voltage output by the trans-impedance amplifier is greater than the target voltage corresponding to the Hamming weight 4, output 1, and the voltage output by the trans-impedance amplifier is less than the target voltage corresponding to the Hamming weight 4, output 0. For the logical operation of multiple rows at the same time, as shown in Figure 7b , the comparison result of the Hamming distance of the logical operation result with the target Hamming distance is sent to the controller 30 by the voltage comparator of each row, and the number of first sequences meeting the condition is counted by the controller. Specifically, the controller can filter out the number of first sequences with a Hamming distance greater than 4.

[0112] Further, as shown in Figure 6cAs shown, an analog / digital signal converter (A / D converter) 54 can be added after the transimpedance amplifier 50, which is used to convert the output voltage of the transimpedance amplifier into a digital signal and directly send it to the controller 30, and the controller 30 obtains the Hamming distance corresponding to the digital signal according to the received digital signal. For the logic operation of multiple rows at the same time, as shown in Figure 7c As shown, the output end of each transimpedance amplifier can be connected to an A / D converter, and the transimpedance amplifier sends an output current to the A / D converter, and the A / D converter converts the output voltage of each row of transimpedance amplifiers into a digital signal and sends it to the controller 30, and the controller obtains the Hamming distance corresponding to the logic operation result of each row of logic operations.

[0113] The embodiment of the present application also provides a chip, which comprises one or more of the memory resistor arrays shown in 6a, 6b, 6c, 7a, 7b, and 7c, and when performing a calculation including a logic operation, the chip can use the memory resistor array described in the above embodiment to implement an XOR logic operation. The method for implementing the XOR operation by the chip can refer to the method for implementing the logic operation by the memory resistor array in the above embodiment, and will not be described here. Figure 4a 4b

[0114] The embodiment of the present application also provides a computing device, which comprises the chip described above, and the computing device performs a logic operation through the chip.

[0115] It should be understood that the "first", "second", and the like descriptions herein are only for the sake of distinguishing similar concepts for the sake of simplicity of description, and do not have other limiting effects.

[0116] Those skilled in the art should further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0117] The above description is only a preferred embodiment of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.​​

Claims

1. A memristor array, characterized by, The array comprises an operation area, a result area and a controller, the operation area comprises m rows of n columns of first memristors, the result area comprises m rows of n columns of second memristors, each row of the operation area stores n first logic values, the controller is configured to input n second logic values to the operation area and control logical operation of the n first logic values of each row and the n second logic values, and a logical operation result of the n second logic values and the n first logic values of each row is stored in n second memristors of each row of the result area; The first memristor and the second memristor of each row are connected to a word line through the same one of the two polarities, the first memristor of each column and the second memristor of each column are connected to a bit line through the other of the two polarities, one end of a constant resistance is connected to each row of word lines, and the other end of the constant resistance is connected to the controller, and each column of bit lines is connected to the controller; The resistance value of each row of first memristors of the operation area represents n first logic values subjected to logical operation; When the n second logic values subjected to logical operation are input to the operation area, the controller is specifically configured to convert the n second logic values subjected to logical operation into n first voltages respectively, and input the n first voltages to the n first memristors respectively, wherein the first voltages are lower than threshold voltages at which the memristor changes from a high resistance state to a low resistance state and threshold voltages at which the memristor changes from a low resistance state to a high resistance state; When the controller is configured to control logical operation of the n first logic values of each row and the n second logic values, the controller is specifically configured to: input n second voltages to the n second memristors; input a third voltage to the constant resistance, wherein the third voltage is a voltage corresponding to a logic value obtained by performing logical NOT operation on the second logic values; The controller is further configured to determine a logical operation result of the n first logic values of each row and the n second logic values according to resistance values of the n second memristors of each row of the result area.

2. The memristor array of claim 1, wherein, The controller is further configured to input fourth voltages to the n second memristors of each row, and determine a Hamming distance of the logical operation result of the first logic values and the second logic values of each row according to output currents of the n second memristors of each row.

3. The memristor array of claim 1, wherein, The controller is further configured to input fourth voltages to the n second memristors, and the array further comprises a transimpedance amplifier connected in parallel with the constant resistance, wherein the transimpedance amplifier is configured to convert output currents of each row of word lines after inputting the fourth voltages into output voltages at a same ratio and transmit the output voltages to the controller, and the controller is configured to determine a Hamming distance of the logical operation result of the n first logic values of each row and the n second logic values according to the output voltages of the transimpedance amplifier of each row.

4. The memristor array of claim 3, wherein, The array further comprises a voltage comparator, two inputs of the voltage comparator are connected with the controller and the transimpedance amplifier respectively, and an output is connected with the controller, the output voltage of the transimpedance amplifier is taken as the first input voltage of the voltage comparator, the controller converts the set target Hamming distance into the second input voltage of the voltage comparator, the voltage comparator compares the first input voltage and the second input voltage, and outputs the comparison result to the controller through the output, and the controller determines the size relationship between the Hamming distance of the logic operation result output by each row of word lines and the target Hamming distance set by the controller according to the comparison result.

5. The memristor array of claim 3, wherein, The array further comprises an A / D converter, two ends of the A / D converter are connected with the controller and the transimpedance amplifier respectively, the A / D converter is used for converting the output voltage of the transimpedance amplifier into a digital signal and sending the digital signal to the controller, and the controller determines the Hamming distance of the logic operation result output by each row of word lines according to the digital signal.

6. A method of performing logical operations in a memristor array, characterized by, The memristor array comprises an operation area, a result area and a controller, the operation area comprises m rows of n columns of first memristors, the result area comprises m rows of n columns of second memristors, each row of the operation area stores n first logic values, and the method comprises the following steps of: The controller inputs n second logic values to the operation area; The controller controls the logic operation of the n first logic values and the n second logic values, the logic operation result of the n second logic values and the n first logic values of each row is stored in n second memristors of each row of the result area, each row of first memristors and second memristors are connected to a word line through one pole with the same polarity, each column of first memristors and each column of second memristors are connected to a bit line through the other pole, each row of word lines is connected to one end of a constant resistance, each column of bit lines is connected to the controller, the other end of the constant resistance is connected to the controller, and the resistance value of each row of first memristors of the operation area represents the n first logic values subjected to the logic operation. The n second logic values subjected to the logic operation are converted into n first voltages respectively, and the n first voltages are input to n first memristors respectively, and the first voltages are lower than the threshold voltage of the high resistance state to the low resistance state of the memristor and the threshold voltage of the low resistance state to the high resistance state of the memristor; The n second logic values subjected to the logic operation are converted into n first voltages respectively, and the n first voltages are input to n first memristors respectively, and the first voltages are lower than the threshold voltage of the high resistance state to the low resistance state of the memristor and the threshold voltage of the low resistance state to the high resistance state of the memristor; The n second logic values subjected to the logic operation are converted into n first voltages respectively, and the n first voltages are input to n first memristors respectively, and the first voltages are lower than the threshold voltage of the high resistance state to the low resistance state of the memristor and the threshold voltage of the low resistance state to the high resistance state of the memristor; The resistance value of each row of n second memristors of the result area is determined to determine the logic operation result of the n first logic values and the n second logic values. ​ ​ 7. The method of claim 6, wherein, The method further comprises: the controller inputs a fourth voltage to the n second memristors, and determines the Hamming distance of the logical operation result of the first logic value and the second logic value of each row according to the output current of the n second memristors of each row.

8. The method of claim 6, wherein, The method further comprises: the controller inputs a fourth voltage to the n second memristors, and the memristor array further comprises: a transimpedance amplifier connected in parallel with the fixed resistor, the transimpedance amplifier being configured to: convert the output current of each row of word lines after inputting the fourth voltage into an output voltage in a proportional manner and transmit the output voltage to the controller, and the controller being configured to determine the Hamming distance of the logical operation result of the n first logic values and the n second logic values of each row according to the output voltage of the transimpedance amplifier of each row.

9. The method of claim 8, wherein, The array further comprises: a voltage comparator, two input ends of the voltage comparator being connected with the controller and the transimpedance amplifier respectively, and an output end being connected with the controller, the output voltage of the transimpedance amplifier being used as a first input voltage of the voltage comparator, the controller converting the set target Hamming distance into a second input voltage of the comparator, the comparator comparing the first input voltage and the second input voltage and outputting a comparison result to the controller through the output end, and the controller determining the size relationship between the Hamming distance of the logical operation result output by each row of word lines and the target Hamming distance set by the controller according to the comparison result.

10. The method according to claim 9, wherein The array further comprises: the array further comprises: an A / D converter, two ends of the A / D converter being connected with the controller and the transimpedance amplifier respectively, the A / D converter being configured to convert the output voltage of the transimpedance amplifier into a digital signal and send the digital signal to the controller, and the controller determining the Hamming distance of the logical operation result output by each row of word lines according to the digital signal.

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