A complete non-volatile boolean logic circuit based on 1t1r array and a control method thereof

Abstract

The application discloses a kind of complete non-volatile Boolean logic circuit based on 1T1R array and control method thereof, belong to microelectronic device technical field, for the logic value P and / or logic value Q of input is carried out logic operation;Wherein, the input resistance state of memristor M1 is determined by logic input Q, input voltage is fixed as-V0, the input voltage of memristor M2 is fixed as V1, the input voltage C on word line WL is determined by logic operation type and logic value Q, P;The input voltage D on source control end is determined by logic operation type, logic value P and voltage C, the resistance state of memristor M2 is as the output of calculation result;The application fully utilizes the switching characteristic of transistor in 1T1R structure on logic algorithm, by dynamically configuring the input voltage on word line WL and source control end, i.e., complete Boolean logic function can be realized in two steps, and non-volatile Boolean logic operation efficiency can be improved with less operation steps and fixed circuit topology.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and more specifically, relates to a complete non-volatile Boolean logic circuit based on a 1T1R array and its control method. Background Technology

[0002] Modern computers are primarily based on the von Neumann architecture. In this architecture, data is retrieved from storage units, transferred to computing units, and then transferred back to storage units after computation. Today, processors and memory operate at considerably high speeds, making the bus connecting these two parts a bottleneck for further speed improvements. Frequent data transfers consume a significant portion of the time and power consumption during data processing. The advent of the big data era has presented computers with more computationally intensive tasks, exacerbating this bottleneck and limiting the development of modern computers, a phenomenon known as the "memory wall." In-memory computing is a highly promising solution. Similar to the human brain, in-memory computing aims to achieve the coexistence of storage and computation within the same physical structure, significantly reducing energy consumption and clock cycles, enabling parallel computing, and offering enormous potential for research and application.

[0003] Memristors, as a novel type of non-volatile memory device, have become a strong candidate for in-memory computing architectures due to their ability to maintain their resistive state even after power is removed. Logic implementations based on memristors can be broadly categorized into three types. The first type represents both the input and output as the memristor's resistance state. This approach facilitates logic cascading but requires a large number of components, and both the number of components and operational complexity increase with computational complexity. The second type uses voltage as the input across the memristor and represents the output as its resistance state. This significantly reduces the number of components and operation steps, but logic cascading requires analog-to-digital conversion, necessitating complex external circuitry. The third type uses the voltage applied to one end of the memristor and its initial resistance value as the inputs, with the output representing the memristor's resistance state. This method uses fewer components and operation steps, and logic cascading is easy. However, this type of logic computation is destructive and serial, which is detrimental to protecting the integrity of input information and improving computational parallelism. Most current solutions are based on arrays of simple memristors. While this structure offers advantages such as small area and high integration, it is highly susceptible to leakage current, leading to calculation errors or failures, which is detrimental to large-scale parallel data processing. Furthermore, most solutions require an additional read step to convert the calculated resistance state into a digital signal consistent with traditional digital circuits, hindering the construction of heterogeneous computing systems. Therefore, it is necessary to propose a fixed-topology, logically complete implementation scheme that, with minimal operation steps, facilitates logic cascading without compromising input data integrity, increases computational parallelism, reduces the probability of leakage current, improves accuracy, and not only preserves the output as a non-volatile resistance state but also provides digital domain calculation results while minimizing resource consumption. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a complete non-volatile Boolean logic circuit based on a 1T1R array and its control method, so as to solve the technical problem that the prior art cannot improve the efficiency of non-volatile Boolean logic operation with fewer operation steps and fixed circuit topology.

[0005] To achieve the above objectives, the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, used to perform logic operations on the input logic value P and / or the input logic value Q.

[0006] The above logic circuit includes: a control unit, memristor M1, memristor M2, a first transistor, a second transistor, and a resistor;

[0007] The positive terminal of memristor M1 is connected to the bit line BL0, and the negative terminal is connected to the drain terminal of the first transistor; the positive terminal of memristor M2 is connected to the bit line BL1, and the negative terminal is connected to the drain terminal of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are led out through the source line SL and connected to the first end of the resistor, and the second end of the resistor serves as the source control terminal; the first transistor and the second transistor are identical; memristor M1 and memristor M2 are identical, and both are initially in a high-resistance state.

[0008] The control unit is used to apply voltage -V0 to memristor M1 through bit line BL0, voltage V1 to memristor M2 through bit line BL1, voltage C to word line WL, voltage D to source control terminal, and read the resistance state of memristor M2 during logic operation, which is the result of logic operation.

[0009] When the logic circuit performs an operation related to the logic value Q, the control unit is also used to set the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation; the operation related to the logic value Q includes the operation of performing logic operations on logic values ​​P and Q and the operation of performing logic operations only on logic value Q;

[0010] V0 and V1 simultaneously satisfy: V set / 2≤V0 <V set V set / 2≤V1 <V set And V0 + V1 ≥ V; V set V is the threshold value for memristor M1 or memristor M2 to change from a high-resistance state to a low-resistance state; V is the upper limit of the fluctuation range of the threshold voltage of memristor M1 or memristor M2.

[0011] The value of voltage C is determined by the logic operation type and logic values ​​Q and P, while the value of voltage D is determined by the logic operation type, logic value P, and voltage C.

[0012] More preferably, V0 takes the value of V1 takes the value of

[0013] More preferably, both memristor M1 and memristor M2 include a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1".

[0014] More preferably, when the type of logic operation is a true logic operation, the voltage C takes the value of V. on The voltage D is 0V;

[0015] When the type of logical operation is pseudo-logical operation, voltage C takes the value of 0V and voltage D takes the value of 0V;

[0016] When the logic operation type is P logic operation: if the logic value P is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0017] When the logic operation type is Q logic operation: if the logic value Q is 1, then the voltage C takes the value of V. on If the logic value Q is 0, then the voltage C is 0V; the voltage D is 0V.

[0018] When the logic operation is a NOT logic operation: if the logic value P is 1, then voltage C is 0V, and voltage D is also 0V; if the logic value P is 0, then voltage C is V. on At this time, the voltage D is -2V2;

[0019] When the logic operation is a NOT Q logic operation: if the logic value Q is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value Q is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0020] When the logical operation type is AND: if the logical operation result of the expression Q? P:0 is 1, then the voltage C takes the value of V. on If the logical operation result of the expression Q? P:0 is 0, then voltage C takes the value of 0V; voltage D takes the value of 0V.

[0021] When the logical operation type is AND NOT: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this point, the voltage D is -2V²; if the expression is chosen... If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0022] When the logical operation type is OR: if the logical operation result of the expression Q? 1:P is 1, the voltage C takes the value of V. on At this time, if the logic value P is 1, then the voltage D is -2V2; if the logic value P is 0, then the voltage D is 0V; when the logical operation result of the selection expression Q? 1:P is 0, the voltage C is 0V, and at this time, the voltage D is 0V.

[0023] When the logical operation type is OR or NOT: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. onAt this point, the voltage D is -2V2; if we choose expression Q? If the logical operation result of P is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0024] When the logical operation is of the type of substantial implication logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0025] When the type of the logical operation is negative substantial implication: if the logical operation result of the expression Q? 0:P is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logical operation result of the expression Q? 0:P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0026] When the logical operation type is inverse implied logic: if the logical operation result of the expression Q? P:1 is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logical operation result of the expression Q? P:1 is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0027] When the logical operation type is a negation-substantial logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If you choose an expression If the logical operation result is 0, then voltage C takes the value of 0V; voltage D takes the value of 0V.

[0028] When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0029] When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value of V. onAt this point, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0030] Among them, V on V2 is the voltage at which the first or second transistor operates in the linear region; both the first and second transistors are NMOS transistors; V2 = V - V1.

[0031] More preferably, V2 takes the value of

[0032] More preferably, the resistance value of the resistor is between the high-resistance value and the low-resistance value of memristor M1 or memristor M2; the resistance value is... Where R H R is the high-resistance resistance value of memristor M1 or memristor M2. L This is the low-resistance resistance value of memristor M1 or memristor M2.

[0033] More preferably, the above-mentioned complete non-volatile Boolean logic circuit further includes: a read circuit; wherein the read circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M2.

[0034] In a second aspect, the present invention provides a control method for a complete non-volatile Boolean logic circuit, applied to a control unit in the complete non-volatile Boolean logic circuit provided in the first aspect of the present invention, comprising the following steps:

[0035] S1. Initialize both memristors M1 and M2 to a high-impedance state;

[0036] S2. Determine whether the current operation is related to the logic value Q. If so, set the memristor M1 to the resistance state corresponding to the logic value Q. Operations related to the logic value Q include operations that perform logical operations on both logic values ​​P and Q, and operations that perform logical operations only on the logic value Q.

[0037] S3. Apply voltage to memristor M1 via bit line BL0. - V0, apply voltage V1 to memristor M2 through bit line BL1, apply voltage C to word line WL, apply voltage D to source control terminal, and read the resistance state of memristor M2, which is the result of logic operation;

[0038] Wherein, V0 and V1 simultaneously satisfy: V set / 2≤V0 <V set V set / 2≤V1 <V set And V0 + V1 ≥ V; V set V is the threshold value for memristor M1 or memristor M2 to change from a high-resistance state to a low-resistance state; V is the upper limit of the fluctuation range of the threshold voltage of memristor M1 or memristor M2.

[0039] The value of voltage C is determined by the logic operation type and logic values ​​Q and P, while the value of voltage D is determined by the logic operation type, logic value P, and voltage C.

[0040] More preferably, when the type of logic operation is a true logic operation, the voltage C takes the value of V. on The voltage D is 0V;

[0041] When the type of logical operation is pseudo-logical operation, voltage C takes the value of 0V and voltage D takes the value of 0V;

[0042] When the logic operation type is P logic operation: if the logic value P is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0043] When the logic operation type is Q logic operation: if the logic value Q is 1, then the voltage C takes the value of V. on If the logic value Q is 0, then the voltage C is 0V; the voltage D is 0V.

[0044] When the logic operation is a NOT logic operation: if the logic value P is 1, then voltage C is 0V, and voltage D is also 0V; if the logic value P is 0, then voltage C is V. on At this time, the voltage D is -2V2;

[0045] When the logic operation is a NOT Q logic operation: if the logic value Q is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value Q is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0046] When the logical operation type is AND: if the logical operation result of the expression Q? P:0 is 1, then the voltage C takes the value of V. on If the logical operation result of the expression Q? P:0 is 0, then voltage C takes the value of 0V; voltage D takes the value of 0V.

[0047] When the logical operation type is AND NOT: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this point, the voltage D is -2V²; if the expression is chosen... If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0048] When the logical operation type is OR: if the logical operation result of the expression Q? 1:P is 1, the voltage C takes the value of V. on At this time, if the logic value P is 1, then the voltage D is -2V2; if the logic value P is 0, then the voltage D is 0V; when the logical operation result of the selection expression Q? 1:P is 0, the voltage C is 0V, and at this time, the voltage D is 0V.

[0049] When the logical operation type is OR or NOT: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this point, the voltage D is -2V²; if the expression is chosen... If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0050] When the logical operation is of the type of substantial implication logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0051] When the type of the logical operation is negative substantial implication: if the logical operation result of the expression Q? 0:P is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logical operation result of the expression Q? 0:P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0052] When the logical operation type is inverse implied logic: if the logical operation result of the expression Q? P:1 is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logical operation result of the expression Q? P:1 is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0053] When the logical operation type is a negation-substantial logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If you choose an expression If the logical operation result is 0, then voltage C takes the value of 0V; voltage D takes the value of 0V.

[0054] When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0055] When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0056] Among them, V on V2 is the voltage at which the first or second transistor operates in the linear region; both the first and second transistors are NMOS transistors; V2 = V - V1.

[0057] Thirdly, the present invention provides a bit-by-bit logic cascading method based on the above-described complete non-volatile Boolean logic circuit, comprising:

[0058] The result of the previous logical operation obtained by operating according to the control method described in the second aspect is used as the new input logical value Q, and the operation is carried out again according to the control method described in the second aspect, thereby realizing the step-by-step logic cascading.

[0059] Fourthly, the present invention proposes a complete non-volatile Boolean logic parallel operation circuit, including multiple complete non-volatile Boolean logic operation circuits provided in the first aspect of the present invention.

[0060] The positive terminals of memristors M1 in each complete non-volatile Boolean logic operation circuit are all connected to the same bit line BL0, and the positive terminals of memristors M2 are all connected to the same bit line BL1, so as to implement multiple logic operations in parallel within the same logic calculation pulse cycle.

[0061] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0062] 1. This invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, used to perform logic operations on input logic values ​​P and / or Q. The logic circuit mainly consists of memristors, transistors, and resistors. The input resistance state of memristor M1 is determined by the logic input Q, with a fixed input voltage of -V0. The input voltage of M2 is fixed at V1. The input voltage C on the word line WL is determined by the logic operation type and logic values ​​Q and P. The input voltage D on the source control terminal is determined by the logic operation type, logic value P, and voltage C. The resistance state of memristor M2 serves as the output of the calculation result. This invention fully utilizes the switching characteristics of transistors in the 1T1R structure in its logic algorithm. By dynamically configuring the input voltages on the word line WL and the source control terminal, the steps to achieve complete Boolean logic functions can be reduced to two steps, improving the efficiency of non-volatile Boolean logic operations with fewer operation steps and a fixed circuit topology.

[0063] 2. The complete non-volatile Boolean logic operation circuit provided by this invention does not require the addition of the reading step of the traditional scheme when real-time output results are needed. By opening the transmission gate switch, the current on the fixed resistor can be sampled and compared with the fixed reference voltage value, and the calculation result in the digital domain can be obtained synchronously, which is beneficial to the construction of a mixed digital-analog system.

[0064] 3. The complete non-volatile Boolean logic operation circuit provided by this invention does not change the resistance state of the memristor M1 during the logic calculation operation. The entire operation process is non-destructive, which is beneficial to protecting the integrity of the input information.

[0065] 4. This invention provides a bit-by-bit logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, which can directly use the result of the previous logic calculation as the input of the next logic operation. The logic cascading is simple and easy to implement, and helps to realize more complex logic functions.

[0066] 5. This invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising multiple such complete non-volatile Boolean logic operation circuits. The positive terminals of the memristors M1 in each circuit are connected to the same bit line BL0, and the positive terminals of the memristors M2 are connected to the same bit line BL1. Bit line BL0 has a fixed input voltage -V0, and bit line BL1 has a fixed input voltage V1. By controlling the voltages C and D input to each word line WL and source control terminal, multiple logic operations can be performed in parallel within the same logic calculation pulse cycle. This invention requires fewer operation steps. Using a 1T1R array completely avoids the problems of misoperation or unsuccessful operation caused by leakage current during large-scale parallel processing. Because the excitation at the BL terminal is fixed, multiple logic operations can be performed simultaneously within one clock cycle, significantly improving computational parallelism and efficiency, and increasing the advantages of using non-volatile devices for computation. Attached Figure Description

[0067] Figure 1 A schematic diagram of the structure of a complete non-volatile Boolean logic operation circuit based on a 1T1R array provided by the present invention;

[0068] Figure 2 This invention provides a schematic diagram of a 1T1R structure based on a memristor used in a complete non-volatile Boolean logic operation circuit and a 100-cycle test diagram of its IV characteristics; wherein, (a) is a schematic diagram of the 1T1R structure; and (b) is a 100-cycle test diagram of the IV characteristics of the 1T1R structure.

[0069] Figure 3 A schematic diagram of the structure of a complete non-volatile Boolean logic operation circuit with a read circuit provided by the present invention;

[0070] Figure 4 A schematic diagram of a complete non-volatile Boolean logic parallel operation circuit provided by the present invention;

[0071] Figure 5 Simulation results of four-bit input bitwise XOR logic calculation provided by the present invention, and the voltage relationship between WL and SL terminals according to the input configuration;

[0072] Figure 6 A schematic diagram showing the change in resistance state of memristor M2, which stores the output results, during the logic calculation process for each row provided by this invention;

[0073] Figure 7 A schematic diagram showing the change in voltage drop across each row of the output memristor M2 during logic calculation, as provided in this invention.

[0074] Figure 8 This is a schematic diagram of the digital domain calculation results output in high and low level form provided by the present invention. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0076] To achieve the above objectives, firstly, such as Figure 1 As shown, the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, used to perform logic operations on the input logic value P and / or the input logic value Q;

[0077] The above logic circuit includes: a control unit, memristor M1, memristor M2, a first transistor, a second transistor, and a resistor;

[0078] The positive terminal of memristor M1 is connected to the bit line BL0, and the negative terminal is connected to the drain terminal of the first transistor; the positive terminal of memristor M2 is connected to the bit line BL1, and the negative terminal is connected to the drain terminal of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are led out through the source line SL and connected to the first end of the resistor, and the second end of the resistor serves as the source control terminal; the first transistor and the second transistor are identical; memristor M1 and memristor M2 are identical, and both are initially in a high-resistance state.

[0079] The control unit is used to apply voltage -V0 to memristor M1 through bit line BL0, voltage V1 to memristor M2 through bit line BL1, voltage C to word line WL, voltage D to source control terminal, and read the resistance state of memristor M2 during logic operation, which is the result of logic operation.

[0080] When the logic circuit performs an operation related to the logic value Q, the control unit is also used to set the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation; the operation related to the logic value Q includes the operation of performing logic operations on logic values ​​P and Q and the operation of performing logic operations only on logic value Q;

[0081] It should be noted that the excitation signals used in the logic operations are all voltage pulse signals; to meet the requirements of the logic operations, V0 and V1 should simultaneously satisfy: V set / 2≤V0 <V set V set / 2≤V1 <V set And V0 + V1 ≥ V; V setV is the threshold voltage at which memristor M1 or M2 transitions from a high-resistance state to a low-resistance state; V is the upper limit of the fluctuation range of the threshold voltage of memristor M1 or M2; in one optional embodiment, V = E set +3RMS set E set For V set The mean; RMS set For V set The mean square error. Specifically, the voltage amplitude of V1 is between V... set With V set The value between / 2 ensures that V1 is insufficient to cause the memristor, which was originally in a high-resistance state, to change to a low-resistance state; simultaneously, when a voltage drop greater than or equal to V is applied across the memristor, it ensures that the memristor undergoes a resistance change; because there is almost no voltage drop loss at the BL terminal and a larger voltage drop at the SL terminal, based on simulation test results, the optimal value for V0 is... The preferred value for V1 is...

[0082] The value of voltage C is determined by the logic operation type and logic values ​​Q and P, while the value of voltage D is determined by the logic operation type, logic value P, and voltage C.

[0083] Taking an NMOS transistor at the 0.18 process node as an example, such as Figure 2 The diagram shows the 1T1R structure based on memristors used in the above-mentioned complete non-volatile Boolean logic operation circuit and its IV characteristic test diagram after 100 cycles; wherein, Figure (a) is the schematic diagram of the 1T1R structure; and Figure (b) is the IV characteristic test diagram after 100 cycles of the 1T1R structure.

[0084] Specifically, when 2.5V is applied to the gate of the transistor, the source and substrate are connected to GND, and a positive voltage is applied to the positive terminal of the memristor, the resistance of the memristor is set to a low-resistance state; when 3.3V is applied to the gate of the transistor, and a negative voltage V is applied to the positive terminal of the memristor... reset When the source and substrate are connected to GND, the resistance of the memristor is set to a high-resistance state. By controlling the voltage at the gate of the transistor and the memristor, the memristor can switch between a high-resistance state and a low-resistance state. In this invention, the high-resistance state of the memristor corresponds to the logic value "0", and the low-resistance state of the memristor corresponds to the logic value "1".

[0085] Preferably, in the logic circuit proposed in this invention, the switching ratio of the memristor is in the range of [10, 500]. A large switching ratio can make the low-resistance state, high-resistance state of the memristor and the resistance value of the fixed resistor R clearly distinguishable, which is beneficial for completing logic calculations based on voltage divider relationships.

[0086] Furthermore, the resistance value is between the high-resistance value and the low-resistance value of memristor M1 or memristor M2; in some optional implementations, the fixed resistor is taken as... In this circuit, its main function is to act as a voltage divider to distinguish between the high and low resistance values ​​of the memristor. Considering that the memristor exhibits a certain fluctuation range between its high and low resistance states, the fixed resistor R can be selected to be slightly larger than [value missing]. The result provides better assurance for the reliability of the circuit.

[0087] Furthermore, in one alternative implementation, such as Figure 3 As shown, the above-mentioned complete non-volatile Boolean logic circuit also includes a read circuit; wherein, the read circuit includes a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, used to read the resistance state of memristor M2. This invention provides a logic calculation read circuit that, by sampling the node voltage and current at the fixed resistor end during the logic calculation pulse, and adding a comparator to the circuit, can achieve real-time acquisition of the digital domain output result. Specifically, a constant operating voltage pulse amplitude A = -V0 is applied to M1 through BL0, a constant operating voltage pulse amplitude B = V1 is applied to M2 through BL1, the on / off state of the transistor is controlled by the voltage C on the control terminal WL, and a voltage D is applied to one end of the fixed resistor through the SL terminal, together completing the corresponding logic calculation operation. The calculation result is stored in the output memristor M2 in the form of the resistance state; simultaneously, during the read operation, the transmission gate enable terminal is controlled to select whether to obtain a digital output result. The comparator reference voltage is a fixed voltage value in all types of logic calculations, and each pin is floating in the idle state. It should be noted that the comparator's input voltage is the source line voltage, which is connected to the lower electrode of the memristor via a transistor, and a voltage V is applied through the word line WL. on The transistor operates in the linear region, and its voltage drop is negligible. According to the memristor state-flipping principle, the voltage drop at this node needs to be greater than or equal to V / 3 before the memristor changes from high resistance to low resistance. Therefore, the reference voltage can be fixed at -V2 / 2. When the comparator input voltage is less than -V2 / 2, the comparator output level flips, and the external digital circuit D flip-flop samples the rising edge to obtain the result in the digital domain. Alternatively, the reference voltage can be fixed at V2 / 2 because the memristor M2, after changing to low resistance, will pull up the potential of the sampling node, while the memristor M2, which remains at high resistance, does not have this effect. Therefore, setting it to V2 / 2 can also distinguish the two state changes of the memristor.

[0088] This invention provides a complete non-volatile Boolean logic implementation method based on memristors, which completes 16 logic calculations in just 2 steps, and meets the requirements of easy logic cascading and protection of the integrity of input information during the calculation process, as shown in Table 1:

[0089] When the logic operation is a true logic operation (TRUE), regardless of the P and Q inputs, the voltage C input to the WL terminal is a fixed voltage V. on The voltage D input at terminal SL is a fixed voltage pulse amplitude of 0, and the resistance state of memristor M1 is determined according to the input Q.

[0090] When the logic operation type is a false logic operation (FALSE), regardless of the input P and Q, the voltage C of the WL input is a fixed voltage of 0V, the voltage D of the SL input is a fixed voltage of 0V, and the resistance state of the memristor M1 depends on the input Q.

[0091] When the logical operation type is P logical operation (COPYP), V is selected based on the result of the selection expression P. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of -2V². Specifically, if the logic value P is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logic value P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0092] When the logical operation type is Q logical operation (COPY Q): V is selected based on the result of the selection expression Q. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of 0, and the resistance state of memristor M1 is determined by the input Q. Specifically, if the logic value Q is 1, then the voltage C takes the value V. on If the logic value Q is 0, then the voltage C is 0V; the voltage D is 0V.

[0093] When the logical operation is of type NOT P: select the expression The result is V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed pulse amplitude of -2V2. Specifically, if the logic value P is 1, then the voltage C is 0V, and at this time, the voltage D is 0V; if the logic value P is 0, then the voltage C is V. on At this time, the voltage D is -2V2;

[0094] When the logical operation is of type NOT Q: V is selected based on the result of the selection expression Q. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of -2V2, and the resistance state of memristor M1 is determined by the input Q. Specifically, if the logic value Q is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logic value Q is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0095] When the logical operation is of type AND: select the result of the expression Q? P:0 and choose V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of 0, and the resistance state of memristor M1 is determined by the input Q. Specifically, if the logical operation result of the expression Q? P:0 is 1, then the voltage C takes the value V. on If the logical operation result of the expression Q? P:0 is 0, then voltage C takes the value of 0V; voltage D takes the value of 0V.

[0096] When the logical operation type is NAND: select the expression The result is V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of -2V², and the resistance state of the memristor M1 depends on the input Q. Specifically, if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this point, the voltage D is -2V²; if the expression is chosen... If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0097] When the logical operation is of type OR: select the result of the expression Q? 1:P and select V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). onWhen the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The voltage pulse amplitude is selected to be either -2V2 or 0V and applied to the SL terminal based on the input P (-2V2 is selected when P=1, and 0V is selected when P=0). The resistance state of the memristor M1 is determined by the input Q. Specifically, when the logical operation result of the expression Q? 1:P is 1, the voltage C takes the value of V. on At this time, if the logic value P is 1, then the voltage D is -2V2; if the logic value P is 0, then the voltage D is 0V; when the logical operation result of the selection expression Q? 1:P is 0, the voltage C is 0V, and at this time, the voltage D is 0V.

[0098] When the logical operation is of type NOR: select the expression The result is V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of -2V², and the resistance state of the memristor M1 depends on the input Q. Specifically, if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this point, the voltage D is -2V²; if the expression is chosen... If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0099] When the logical operation is of the type of material implication logical operation (IMP): select the expression The result is V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The voltage pulse amplitude is selected to be 0 or -2V2 based on the input P and applied to the SL terminal (0V for P=1, -2V2 for P=0). The resistance state of the memristor M1 is determined by the input Q. Specifically, in the selection expression... When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0100] When the logical operation is of type Negative Substantial Implication (NIMP): the result of the selection expression Q? 0:P selects V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of -2V2, and the resistance state of memristor M1 is determined by the input Q. Specifically, if the logical operation result of the expression Q? 0:P is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logical operation result of the expression Q? 0:P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0101] When the logical operation is of the type of Inverse Substantial Implication (RIMP): the result of the selection expression Q? P:1 selects V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of -2V2, and the resistance state of memristor M1 is determined by the input Q. Specifically, if the logical operation result of the expression Q? P:1 is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the logical operation result of the expression Q? P:1 is 0, then the voltage C is 0V, and at this time, the voltage D is 0V.

[0102] When the logical operation is of type Negative Substantial Implication (RNIMP): select the expression The result is V. on Alternatively, 0V can be applied to the WL terminal (when the expression result is 1, V is selected). on When the expression result is 0, select 0V; if WL is configured with 0V, then SL is 0V, if WL is configured with V on The SL terminal has a fixed voltage pulse amplitude of 0, and the resistance state of memristor M1 depends on the input Q. Specifically, if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If you choose an expression If the logical operation result is 0, then voltage C takes the value of 0V; voltage D takes the value of 0V.

[0103] When the logical operation type is XOR: select the expression The result is V. onAlternatively, 0 is applied to the WL end (when the expression result is 1, V is selected). on (If the expression result is 0, select 0V); If WL is configured with 0V, then SL must be 0V; if WL is configured with V... on The voltage pulse amplitude is selected to be either -2V2 or 0V and applied to the SL terminal according to the input P (-2V2 is selected when P=1, and 0V is selected when P=0). The resistance state of the memristor M1 is determined according to the input Q; specifically, in the selection expression... When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0104] When the logical operation is of type XNOR: select the expression The result is V. on Alternatively, 0 can be applied to the WL terminal; if WL is configured to 0V, then SL is 0V, and if WL is configured to V... on The voltage pulse amplitude is selected to be 0V or -2V2 based on the input P and applied to the SL terminal (-2V2 is selected when P=0, and 0V is selected when P=1). The resistance state of the memristor M1 is determined by the input Q. Specifically, in the selection expression... When the logical operation result is 1, the voltage C takes the value of V. on At this point, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V.

[0105] Among them, V on This is the voltage at which the first or second transistor operates in the linear region, where the source and drain of the transistor are connected, equivalent to a variable resistor; both the first and second transistors mentioned above are NMOS transistors. Taking a transistor at the 0.18 process node as an example, V... on The value is 3.3V. V2 = V - V1, and the range of V2 is the same as that of the memristor V. set The voltage range is proportional, and the preferred value is [value missing].

[0106] Table 1

[0107]

[0108]

[0109] In a second aspect, the present invention provides a control method for a complete non-volatile Boolean logic circuit, applied to a control unit in the complete non-volatile Boolean logic circuit provided in the first aspect of the present invention, comprising the following steps:

[0110] S1. Initialize both memristors M1 and M2 to a high-impedance state;

[0111] S2. Determine whether the current operation is related to the logic value Q. If so, set the memristor M1 to the resistance state corresponding to the logic value Q. Operations related to the logic value Q include operations that perform logical operations on both logic values ​​P and Q, and operations that perform logical operations only on the logic value Q.

[0112] S3. Apply voltage -V0 to memristor M1 through bit line BL0, apply voltage V1 to memristor M2 through bit line BL1, apply voltage C on word line WL, apply voltage D on source control terminal, and read the resistance state of memristor M2, which is the result of logic operation.

[0113] Wherein, V0 and V1 simultaneously satisfy: V set / 2≤V0 <V set V set / 2≤V1 <V set And V0 + V1 ≥ V; V set The threshold value for the transition of memristor M1 or M2 from a high-resistance state to a low-resistance state; V = E set +3RMS set E represents the upper limit of the threshold voltage fluctuation range of memristor M1 or memristor M2. set For V set The mean; RMS set For V set The mean squared error;

[0114] The value of voltage C is determined by the logic operation type and logic values ​​Q and P, while the value of voltage D is determined by the logic operation type, logic value P, and voltage C.

[0115] The related technical solutions are the same as the complete non-volatile Boolean logic operation circuit provided in the first aspect of this invention, and will not be described in detail here.

[0116] In summary, the logic circuit provided by this invention, composed of memristors, transistors, fixed resistors, and configurable comparators, achieves 16 complete logic calculations in two steps by configuring different operating voltages at the control terminal, and simultaneously obtains the calculation results in the digital domain. The purpose of this invention is to provide a complete non-volatile Boolean logic circuit based on a memristor (1T1R array) and its control method. While using as few operation steps and a fixed circuit topology as possible, it improves computational parallelism and efficiency, increases computational reliability, reduces calculation errors caused by leakage current in the memristor array, and the calculation scheme easily implements logic cascading while protecting the integrity of input information during the calculation process. Therefore, this solution can serve as a general logic implementation method.

[0117] Thirdly, the present invention provides a bit-by-bit logic cascading method based on the above-described complete non-volatile Boolean logic circuit, comprising:

[0118] The result of the previous logical operation obtained by operating according to the control method described in the second aspect is used as the new input logical value Q, and the operation is carried out again according to the control method described in the second aspect, thereby realizing the step-by-step logic cascading.

[0119] The related technical solutions are the same as the control method of the complete non-volatile Boolean logic circuit of this invention, and will not be described in detail here.

[0120] Fourthly, the present invention proposes a complete non-volatile Boolean logic parallel operation circuit, including multiple complete non-volatile Boolean logic operation circuits provided in the first aspect of the present invention.

[0121] The positive terminals of memristors M1 in each complete non-volatile Boolean logic operation circuit are all connected to the same bit line BL0, and the positive terminals of memristors M2 are all connected to the same bit line BL1, so as to process multiple logic operations in parallel within the same logic calculation pulse cycle.

[0122] Specifically, such as Figure 4 The following is based on Figure 1 The diagram shows a complete non-volatile Boolean logic parallel operation circuit, with 4 WL and 2 BL cross structures.

[0123] To further illustrate the complete non-volatile Boolean logic parallel operation circuit provided by this invention, in one optional embodiment, the Vset of a hafnium oxide memristor compatible with CMOS technology is used for averaging to obtain V. set mean E set The value is 0.6V, and the root mean square error (RMS) is 0.6%. set Since the value is 0.05V, V = 0.75V. The operating pulse width is set to 100ns, and the selected transistor is a 0.18μm process Mn33 NMOS, with a voltage V in its linear region. on The value is 3.3V. For example... Figure 5 The diagram shows the simulation results of a four-bit XOR logic calculation and the voltage relationship between WL and SL terminals based on the input configuration: P = 0011, Q = 0101, the logic calculation result of P⊕Q should be 0110. The first row of the optional array represents the least significant bit, and the fourth row represents the most significant bit. The simulation calculates whether the voltage drop across the second memristor in each row is as expected. For example, if the calculation result is 1, it means that the voltage drop across the second memristor needs to be greater than V. set The resistance state flips; the calculation result is 0, meaning the voltage drop across the second memristor needs to be less than V. set In a 1T1R array, the WL switch can be used to isolate this row, and the voltage drop across the second memristor is approximately 0. The simulation results are in line with expectations.

[0124] Furthermore, such as Figure 6 The image shows the change in resistance state of memristor M2, which stores the output results, during the logic calculation (pulse application) process. Figure 7 The figure shows the change in voltage drop across each row of output memristor M2 during logic calculation (pulse application). Figure 8 The results shown are the digital domain calculation results output in high and low level form.

[0125] When input P=0 and Q=0, M1 is set to high impedance state. The operating pulse amplitude at BL0 is connected to -V0, the operating pulse amplitude at BL1 is connected to V1, WL is connected to 0V, and the operating pulse amplitude at SL is connected to 0V. At this time, the voltage V across M2 is... M2 When the impedance is approximately 0, M2 remains in a high-impedance state, outputting a logic value of 0, and the comparator outputs a low level.

[0126] When input P=0 and Q=1, M1 is set to low impedance state. The operating pulse amplitude of BL0 is connected to -V0, the operating pulse amplitude of BL1 is connected to V1, the voltage of 3.3V for the transistor to operate in the linear region is connected to WL, and the operating pulse amplitude of SL is connected to 0. At this time, the voltage V across M2 is... M2 Greater than V set When M2 transitions to a low-impedance state, it outputs a logic value of 1, and the comparator outputs a high level.

[0127] When input P=1 and Q=0, M1 is set to high impedance state. The operating pulse amplitude of BL0 is connected to -V0, the operating pulse amplitude of BL1 is connected to V1, the voltage of 3.3V (the voltage in the linear region of the transistor) is connected to WL, and the operating pulse amplitude of SL is connected to -2V2. At this time, the voltage V across M2 is... M2 Greater than V setWhen M2 transitions to a low-impedance state, it outputs a logic value of 1, and the comparator outputs a high level.

[0128] When input P=1 and Q=1, M1 is set to low impedance state, the operating pulse amplitude of BL0 is connected to -V0, the operating pulse amplitude of BL1 is connected to V1, WL is connected to 0V, the operating pulse amplitude of SL is connected to 0, and the voltage across M2 is V. M2 Less than V set M2 remains in a high impedance state, outputs a logic value of 0, and the comparator outputs a low level.

[0129] Similarly, other basic Boolean logic functions can also be implemented in the same way.

[0130] In summary, this invention discloses a complete non-volatile Boolean logic circuit based on a 1T1R array. This logic circuit consists of two memristors, two enhancement-mode NMOS transistors, a fixed resistor, a transmission gate switch, and a comparator. The logic algorithm fully utilizes the switching characteristics of the transistors in the 1T1R structure. By dynamically configuring the control pins on the word and source lines of the circuit, the logic iteration steps are reduced to two steps. During logic operation, selecting to open the transmission gate switch allows sampling the current on the fixed resistor, comparing it with a fixed reference voltage value to obtain the digital domain output. Based on 16 excitation configuration schemes and a limited number of power supply amplitude types, 16 reconfigurable Boolean logic functions are implemented. Specifically, the positive terminal of the memristor is connected to the bit lines (BL0, BL1), and the negative terminal of the memristor is connected to the drain of the transistor. The transistors are connected using a common-gate and common-source configuration. The source terminals of transistors in the same row are connected together and then connected to the SL pin (source control terminal) through a fixed resistor. The node where the fixed resistor is connected to the source line can be selectively connected to a comparator. The input resistance state of memristor M1 is determined by the logic input Q, while the resistance state of memristor M2 serves as the output of the calculation result. During the logic calculation, the voltage pulse amplitude applied to the BL terminal is fixed, and the upper limit of the fluctuation range of the memristor threshold voltage is V = E. set +3RMS set Among them, E set For V set The mean; RMS set For V set The mean square error. The input voltage on the upper electrode of the input memristor M1 is -V0 (V0 is the voltage across the memristor V). set The voltage range is proportional to the input voltage (V0 + V1 ≥ V), and the input voltage on the upper electrode of the output memristor M2 is V1 (the range of V1 is proportional to the memristor voltage). set The voltage range is proportional, and V0 + V1 ≥ V must be satisfied. The voltage at the WL terminal varies between two voltage ranges depending on the logic type and the inputs Q and P. onThe voltage at the SL terminal is selected between 0V and -2V2, depending on the logic type, the voltage value of WL, and the input P. (V2 = V - V1, and its range is the same as that of the memristor V). set (The voltage range is proportional to the input voltage). When real-time output results are required, there is no need to add the reading steps of traditional solutions. By opening the transmission gate switch, the digital calculation result is obtained synchronously after the logic calculation is completed, which is beneficial for building a mixed-signal system. Compared with existing logic calculation solutions, this solution uses fewer operation steps. Using a 1T1R array can completely avoid the problem of misoperation or operation failure caused by leakage current during large-scale parallel processing. Because the excitation at the BL terminal is fixed, multiple logic operations can be performed simultaneously within one clock cycle, which greatly improves the parallelism and efficiency of the calculation and increases the advantage of using non-volatile devices for calculation. This solution has logical integrity. The logic implementation method used in this solution is non-destructive, which is beneficial for protecting the integrity of input information. The logic cascading of this solution is simple and easy to implement, which helps to realize more complex logic function applications.

[0131] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A complete non-volatile Boolean logic operation circuit based on a 1T1R array, used to perform logical operations on input logic values ​​P and / or input logic values ​​Q, characterized in that, include: Control unit, memristor M1, memristor M2, first transistor, second transistor, and resistor; The positive terminal of memristor M1 is connected to bit line BL0, and the negative terminal is connected to the drain terminal of the first transistor; the positive terminal of memristor M2 is connected to bit line BL1, and the negative terminal is connected to the drain terminal of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are led out through the source line SL and connected to the first end of the resistor, and the second end of the resistor serves as the source control terminal; the first transistor is the same as the first transistor; the memristor M1 and the memristor M2 are the same, and both are initially in a high-resistance state; The control unit is used to apply voltage -V0 to memristor M1 through bit line BL0, voltage V1 to memristor M2 through bit line BL1, voltage C to word line WL, voltage D to source control terminal, and read the resistance state of memristor M2 during logic operation, which is the result of logic operation. When the logic operation circuit performs an operation related to the logic value Q, the control unit is further configured to set the memristor M1 to the resistive state corresponding to the logic value Q before performing the logic operation; the operation related to the logic value Q includes an operation of performing logic operations on the logic value P and the logic value Q and an operation of performing logic operations only on the logic value Q; V0 and V1 simultaneously satisfy: V set / 2 V0 <V set V set / 2 V1 <V set And V0+V1 V;V set The threshold for the memristor M1 or the memristor M2 to transition from a high-resistance state to a low-resistance state; This is the upper limit of the threshold voltage fluctuation range of the memristor M1 or the memristor M2; The value of voltage C is determined by the type of the logical operation and the logical values ​​Q and P, and the value of voltage D is determined by the type of the logical operation, the logical value P, and the voltage C. When the type of the logical operation is a true logical operation, the voltage C takes the value V. on The voltage D is 0V; When the type of the logic operation is a pseudo logic operation, the voltage C is 0V and the voltage D is 0V.

2. The complete non-volatile Boolean logic operation circuit according to claim 1, characterized in that, V0 takes the value of V1 takes the value of .

3. The complete non-volatile Boolean logic operation circuit according to claim 1, characterized in that, When the type of the logic operation is P logic operation: if the logic value P is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V. When the type of the logic operation is Q logic operation: if the logic value Q is 1, then the voltage C takes the value V. on If the logic value Q is 0, then the voltage C is 0V; the voltage D is 0V. When the logic operation is a non-P logic operation: if the logic value P is 1, then the voltage C is 0V, and the voltage D is 0V; if the logic value P is 0, then the voltage C is V. on At this time, the voltage D is -2V2; When the type of the logic operation is a non-Q logic operation: if the logic value Q is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value Q is 0, then the voltage C is 0V, and at this time, the voltage D is 0V. When the logical operation is of type AND logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V. When the logical operation is of type AND NOT: if the expression is selected If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the logical operation is of type OR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the logical operation is of type OR or NOT: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a substantial implication logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a negative substantial implication logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a non-substantial implication logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a negation-substantial implied logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V. When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. Among them, V on V2 is the voltage at which the first transistor or the second transistor operates in the linear region; both the first transistor and the second transistor are NMOS transistors; V2 = V - V1.

4. The complete non-volatile Boolean logic operation circuit according to claim 1, characterized in that, V2 takes the value of .

5. The complete non-volatile Boolean logic operation circuit according to claim 1, characterized in that, The resistance value is between the high-resistance value and the low-resistance value of memristor M1 or memristor M2; the resistance value is... , where R H R is the high-resistance resistance value of the memristor M1 or the memristor M2. L The low-resistance resistance value of the memristor M1 or the memristor M2.

6. The complete non-volatile Boolean logic operation circuit according to any one of claims 1-5, characterized in that, Also includes: A reading circuit; wherein the reading circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M2.

7. A control method for a complete non-volatile Boolean logic circuit, used to perform logical operations on input logic values ​​P and / or input logic values ​​Q, characterized in that, A control unit applied in a complete non-volatile Boolean logic circuit according to any one of claims 1-6 includes the following steps: S1. Initialize both memristor M1 and memristor M2 to a high-resistance state; S2. Determine whether the current operation is related to the logic value Q. If so, set the memristor M1 to the resistive state corresponding to the logic value Q. The operation related to the logic value Q includes operations that perform logical operations on the logic value P and the logic value Q, and operations that perform logical operations only on the logic value Q. S3. Apply voltage -V0 to memristor M1 through bit line BL0, apply voltage V1 to memristor M2 through bit line BL1, apply voltage C on word line WL, apply voltage D on source control terminal, and read the resistance state of memristor M2, which is the result of logic operation. Wherein, V0 and V1 simultaneously satisfy: V set / 2 V0 <V set V set / 2 V1 <V set And V0+V1 V;V set The threshold for the memristor M1 or the memristor M2 to transition from a high-resistance state to a low-resistance state; This is the upper limit of the threshold voltage fluctuation range of the memristor M1 or the memristor M2; For V set The mean; For V set The mean squared error; The value of voltage C is determined by the type of the logical operation and the logical values ​​Q and P, and the value of voltage D is determined by the type of the logical operation, the logical value P, and the voltage C. When the type of the logical operation is a true logical operation, the voltage C takes the value V. on The voltage D is 0V; When the type of the logic operation is a pseudo logic operation, the voltage C is 0V and the voltage D is 0V.

8. The control method for a complete non-volatile Boolean logic circuit according to claim 7, characterized in that, When the type of the logic operation is P logic operation: if the logic value P is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value P is 0, then the voltage C is 0V, and at this time, the voltage D is 0V. When the type of the logic operation is Q logic operation: if the logic value Q is 1, then the voltage C takes the value V. on If the logic value Q is 0, then the voltage C is 0V; the voltage D is 0V. When the logic operation is a non-P logic operation: if the logic value P is 1, then the voltage C is 0V, and the voltage D is 0V; if the logic value P is 0, then the voltage C is V. on At this time, the voltage D is -2V2; When the type of the logic operation is a non-Q logic operation: if the logic value Q is 1, then the voltage C takes the value V. on At this time, the voltage D is -2V2; if the logic value Q is 0, then the voltage C is 0V, and at this time, the voltage D is 0V. When the logical operation is of type AND logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V. When the logical operation is of type AND NOT: if the expression is selected If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the logical operation is of type OR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the logical operation is of type OR or NOT: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a substantial implication logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a negative substantial implication logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a non-substantial implication logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on At this time, the voltage D is -2V2; if the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the type of the logical operation is a negation-substantial implied logical operation: if the expression is selected... If the logical operation result is 1, then the voltage C takes the value of V. on If the selection expression If the logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V. When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is -2V; if the logic value P is 0, then the voltage D is 0V; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. When the logical operation is of type XOR logical operation: in the selection expression When the logical operation result is 1, the voltage C takes the value V. on At this time, if the logic value P is 1, then the voltage D is 0V; if the logic value P is 0, then the voltage D is -2V2; in the selection expression When the logical operation result is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V. Among them, V on V2 is the voltage at which the first transistor or the second transistor operates in the linear region; both the first transistor and the second transistor are NMOS transistors; V2 = V - V1.

9. A method for cascading bit-by-bit logic of a complete non-volatile Boolean logic circuit, characterized in that, The complete non-volatile Boolean logic circuit is the complete non-volatile Boolean logic circuit according to any one of claims 1-6; the bit-by-bit logic cascading method includes: The result of the previous logical operation obtained by operating according to the control method described in claim 7 or 8 is used as the new input logical value Q, and the operation is carried out again according to the control method described in claim 7 or 8, thereby realizing the step-by-step logical cascading.

10. A complete non-volatile Boolean logic parallel operation circuit, characterized in that, Includes a complete non-volatile Boolean logic operation circuit as described in any one of claims 1-6; The positive terminals of the memristors M1 in each of the complete non-volatile Boolean logic operation circuits are all connected to the same bit line BL0, and the positive terminals of the memristors M2 are all connected to the same bit line BL1, so as to implement multiple logic operations in parallel within the same logic calculation pulse cycle.

Images