Ball grid array package and its package substrate

Abstract

The present disclosure relates to a ball grid array package and a package substrate thereof. A package substrate is suitable for a ball grid array package. The substrate comprises two board contacts, two solder ball pads, two connecting holes and two signal lines. The connection line of the two board contacts is perpendicular to the connection line of the two solder ball pads. The two signal lines respectively connect the two board contacts to the connecting holes. Each signal line comprises a wiring segment, a close segment and a divergent segment connected in sequence. The two wiring segments are substantially arranged in parallel. The two close segments are substantially arranged in parallel and substantially symmetrical to the connection line of the solder ball pads. The two divergent segments are substantially symmetrical to the connection line of the solder ball pads and are respectively electrically connected to the two connecting holes.

Description

Technical Field

[0001] The present invention relates to a packaging substrate, in particular to a substrate for ball grid array packaging and the ball grid array packaging. Background Art

[0002] Ball Grid Array Package is a type of surface mount packaging technology used to package chips (Integrated Circuits) on circuit boards. The circuit board has multiple solder balls arranged in an array, multiple contacts for electrically connecting the chips, and multiple wirings for electrically connecting the contacts and solder balls. Among them, the design requirements for wiring used to transmit differential signals are higher than those for wiring that transmits other signals.

[0003] The U.S. patent application No. 2016 / 0358866 "Package substrate differential impedance optimization for 25G bps and beyond" published on December 8, 2016 and the patent application No. 2018 / 0368260 "High-speed printed circuit board and differential wiring method thereof" published on December 20, 2018 describe the design requirements for differential signal wiring. Differential signal wiring often needs to overcome the signal delay problem, differential return loss, and differential insertion loss caused by the different wiring lengths of the positive and negative ends of the differential signal. Summary of the invention

[0004] In view of this, according to some embodiments, a ball grid array package includes a chip and a substrate. The chip includes two chip contacts. The substrate includes two board contacts, two solder ball pads, two connecting holes, and two signal lines. The connection between the two board contacts is a contact connection, and the two chip contacts are electrically connected to the two board contacts. The connection between the two solder ball pads is a pad connection, and the contact connection is not substantially parallel to the pad connection. The two connecting holes are substantially symmetrical to the pad connection, and the two connecting holes are electrically connected to the two solder ball pads respectively. Each signal line includes a wiring segment, a proximity segment, and a divergent segment connected in sequence, the two wiring segments are electrically connected to the two board contacts respectively and are arranged substantially in parallel, the two proximity segments are arranged substantially in parallel and are substantially symmetrical to the pad connection, and the two divergent segments are substantially symmetrical to the pad connection and are electrically connected to the two connecting holes respectively.

[0005] According to some embodiments, a distance between a connection point between each of the divergent segments and the proximal segment and the solder ball pad is 100 microns to 250 microns.

[0006] According to some embodiments, the lengths of the two branched segments are substantially the same.

[0007] According to some embodiments, each of the branch segments includes an oblique segment and a straight segment, the two oblique segments are electrically connected to the two adjacent segments respectively, and the two straight segments are substantially parallel to the pad connection line and are electrically connected to the two connecting holes respectively.

[0008] According to some embodiments, each of the branch segments sequentially includes an oblique sub-segment, a straight sub-segment and an introduction sub-segment, the two oblique sub-segments are respectively electrically connected to the two adjacent segments, the two straight sub-segments are substantially parallel to the solder ball pad connection line, and the two introduction sub-segments are respectively electrically connected to the two connecting holes.

[0009] According to some embodiments, the angle between each oblique sub-segment and the line connecting the solder ball pad is between 35 degrees and 55 degrees, each oblique sub-segment is 50 to 150 microns away from the adjacent solder ball pad, each straight sub-segment is 50 to 150 microns away from the adjacent solder ball pad, and the outer diameter of each solder ball pad is 300 microns to 600 microns.

[0010] According to some embodiments, the two signal lines have a preset impedance, and there is a preset relationship between the length of each branch segment and the distance between the two connecting holes, wherein the preset relationship makes the impedance of the two connecting holes lower than the preset impedance and the impedance of the two branch segments higher than the preset impedance.

[0011] According to some embodiments, a packaging substrate is suitable for packaging a chip, and the chip has two chip contacts. The packaging substrate includes two board contacts, two solder ball pads, two connecting holes, and two signal lines. One of the connecting lines of the two board contacts is a contact connection line, and the two board contacts are suitable for electrically connecting the two chip contacts. One of the connecting lines of the two solder ball pads is a pad connection line, and the contact connection line is not substantially parallel to the pad connection line. The two connecting holes are substantially symmetrical to the pad connection line, and the two connecting holes are electrically connected to the two solder ball pads respectively. Each of the signal lines includes a wiring segment, a proximity segment, and a divergent segment connected in sequence, the two wiring segments are electrically connected to the two board contacts respectively and are arranged substantially in parallel, the two proximity segments are arranged substantially in parallel and substantially symmetrical to the pad connection line, and the two divergent segments are substantially symmetrical to the pad connection line and are electrically connected to the two connecting holes respectively.

[0012] In summary, according to some embodiments, the differential signal line of the package substrate includes a diverging segment, which is symmetrical to the pad connection and electrically connected to the via, and the via is also symmetrical to the pad connection. Therefore, the lengths of the two signal lines in the same pair of differential signal lines are substantially the same, reducing the time difference in differential signal transmission. In some embodiments, by adjusting the relationship between the length of the diverging segment and the fifth distance, the impedance of the differential signal line can be made closer to the designed impedance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A illustrates a bottom view of a ball grid array package according to some embodiments;

[0014] Figure 1B Draw Figure 1A A side view of a ball grid array package;

[0015] Figure 2 A partial top view of a chip, wiring and solder ball pads of a ball grid array package according to some embodiments is shown (the cover is not shown);

[0016] Figure 3 A partial three-dimensional schematic diagram of a chip, a pair of differential signal lines and solder ball pads of a ball grid array package according to some embodiments is shown (only a pair of differential signal lines are shown);

[0017] Figure 4 A partial schematic diagram of a chip, wiring and solder ball pads of a ball grid array package according to some embodiments is shown;

[0018] Figure 5 Draw Figure 2 and Figure 4 The differential reflection loss diagram of a pair of differential signal lines;

[0019] Figure 6 Draw Figure 2 and Figure 4 The differential insertion loss diagram of a pair of differential signal lines;

[0020] Figure 7 Draw Figure 2 and Figure 4 Insertion loss diagram of the mode conversion of a differential signal line pair into common mode noise;

[0021] Figure 8 Draw Figure 2 and Figure 4 The differential time domain reflectometry (TDR) diagram of a pair of differential signal lines;

[0022] Fig. 9 A partial enlarged view of a pair of differential signal lines is shown according to some embodiments; and

[0023] Fig.10 A partial enlarged view of a pair of differential signal lines according to some embodiments is shown. DETAILED DESCRIPTION

[0024] Please refer to Figure 1A and Figure 1B , Figure 1A A bottom view of a ball grid array package is shown according to some embodiments. Figure 1B Draw Figure 1A The side view of the ball grid array package of the present invention. The ball grid array package (BGA Package) includes a substrate 10, a chip 20, solder balls 30 and a cover 40. The substrate 10 has circuit traces, which are used to electrically connect multiple contacts (described later) of the chip 20 to multiple solder balls 30. The cover 40 covers the chip 20 and the substrate 10 to protect the chip 20 and the wiring on the substrate 10. In some embodiments, the contacts of the chip 20 are electrically connected to the corresponding wiring by wirebonds. In some embodiments, the chip 20 is a flip chip, and the chip 20 is electrically connected to the corresponding wiring by flip chip. In some embodiments, the substrate 10 is a circuit board, which can be a multi-layer circuit board, such as but not limited to a four-layer or six-layer circuit board. The number of layers of the circuit board is designed according to the characteristics and number of the contacts of the chip 20. In some embodiments, the material of the cover 40 is metal, plastic, glass or ceramic.

[0025] See also Figure 2 , Figure 2 A partial top view of a chip, wiring and solder ball pad of a ball grid array package is shown according to some embodiments (only part of the chip, part of the wiring and part of the solder ball pad are shown, and the cover 40 is not shown). The chip 20 includes a plurality of chip contacts 22. In some embodiments, the chip contacts 22 include differential contacts 24a, 24b, 26a, 26b and general contacts 28. The differential contacts 24a, 24b are hereinafter referred to as the first pair of differential contacts, which are respectively positive and negative terminal contacts and are used to transmit differential signals; the differential contacts 26a, 26b are hereinafter referred to as the second pair of differential contacts, which are used to transmit differential signals. The general contacts 28 can be output contacts, input contacts or detection contacts.

[0026] The substrate 10 includes a plurality of substrate contacts 12. In some embodiments, the substrate contacts 12 include differential substrate contacts 14a, 14b, 16a, 16b and general substrate contacts 18 (the differential substrate contacts 14a, 14b are hereinafter referred to as a first pair of differential substrate contacts; the differential substrate contacts 16a, 16b are hereinafter referred to as a second pair of differential substrate contacts).

[0027] The board contacts 12 are electrically connected to the chip contacts 22 respectively. Figure 2 In the embodiment, the board contact 12 is electrically connected to the corresponding chip contact 22 through the differential lead 17a, the differential lead 17b and the general lead 17c, wherein the differential leads 17a, 17b are used to connect the differential board contacts 14a, 14b, 16a, 16b and the differential crystal contacts 24a, 24b, 26a, 26b, and the general lead 17c is used to connect the general board contact 18 and the general crystal contact 28.

[0028] The substrate 10 includes a plurality of connecting holes 52. In some embodiments, the connecting holes 52 include differential connecting holes 54a, 54b, 56a, 56b and a general connecting hole 58 (the differential connecting holes 54a, 54b are hereinafter referred to as a first pair of differential connecting holes; the differential connecting holes 56a, 56b are hereinafter referred to as a second pair of differential connecting holes).

[0029] The substrate 10 includes a plurality of signal lines 62 (i.e., the aforementioned wiring), and the signal lines 62 are used to electrically connect the board contacts 12 to the connecting holes 52. In some embodiments, the signal lines 62 include differential signal lines 64a, 64b, 66a, 66b and general signal lines 68 (the differential signal lines 64a, 64b are hereinafter referred to as the first pair of differential signal lines; the differential signal lines 66a, 66b are hereinafter referred to as the second pair of differential signal lines).

[0030] The substrate 10 includes a plurality of solder ball pads 72 (shown as circles formed by dashed lines in the figure), each solder ball pad 72 being electrically connected to the connecting hole 52. In some embodiments, the solder ball pads 72 include differential solder ball pads 74a, 74b, 76a, 76b and general solder ball pads 78 (the differential solder ball pads 74a, 74b are hereinafter referred to as a first pair of differential solder ball pads; the differential solder ball pads 76a, 76b are hereinafter referred to as a second pair of differential solder ball pads).

[0031] The connection line of the first pair of differential board contacts 14a, 14b is called the connection line L1 (a virtual connection line, which is generally horizontal in the figure, and the connection line L1 includes an extension line extending beyond the first pair of differential board contacts 14a, 14b). In some embodiments, the connection line L1 is a connection line of the corresponding positions of the positive and negative differential board contacts 14a, 14b of the first pair of differential board contacts 14a, 14b, such as but not limited to the connection line of the center of the positive and negative differential board contacts 14a, 14b (such as Figure 2As shown in the figure), the connection line of the vertices of the positive and negative differential board contacts 14a, 14b, or the connection line of the bottom ends of the positive and negative differential board contacts 14a, 14b. The connection line of the first pair of differential solder ball pads 74a, 74b is called the solder pad connection line L2 (a virtual connection line, which is roughly vertically shown in the figure, and the solder pad connection line L2 includes an extension line extending beyond the first pair of differential solder ball pads 74a, 74b). In some embodiments, the solder pad connection line L2 is a connection line of the corresponding positions of the positive and negative differential solder ball pads 74a, 74b of the first pair of differential solder ball pads 74a, 74b, such as but not limited to the connection line of the centers of the positive and negative differential solder ball pads 74a, 74b (such as Figure 2 ), or a line connecting the same quadrant point of the positive and negative differential solder ball pads 74a, 74b. Figure 2 In some embodiments, the contact line L1 is not substantially parallel to the pad line L2. In some embodiments, the non-substantially parallel relationship between the contact line L1 and the pad line L2 is substantially perpendicular (e.g. Figure 2 ), or the angle between the contact line L1 and the pad line L2 is substantially 45 degrees, or between 45 degrees and 90 degrees (“non-substantially parallel” will be described later). In some embodiments, the first pair of differential solder ball pads 74a, 74b are close to one side of the substrate 10 ( Figure 2 The pad connection line L2 is substantially perpendicular to the side edge. Figure 2 In the embodiment of the present invention, the first pair of differential solder ball pads 74a, 74b are close to the bottom edge of the substrate 10 (ie Figure 2 The direction, the lower side, corresponds to Figure 1A In some embodiments, the pad connection line L2' of the second pair of differential solder ball pads 76a, 76b is not substantially parallel to the contact connection line L1' of the second pair of differential board contacts 16a, 16b.

[0032] At least one pair of the differential communication holes 54a, 54b, 56a, 56b is disposed substantially symmetrically to the corresponding pad connection lines L2, L2'. Figure 2 In the embodiment, the first pair of differential communication holes 54a, 54b are symmetrical to the pad connection line L2, and the second pair of differential communication holes 56a, 56b are symmetrical to the pad connection line L2'.

[0033] Please match Figure 3 Read it. Figure 3 A partial three-dimensional schematic diagram of a chip, a pair of differential signal lines and solder ball pads of a ball grid array package according to some embodiments is shown (only a pair of differential signal lines are shown). Figure 3The first pair of differential crystal contacts 24a, 24b, the first pair of differential board contacts 14a, 14b, the first pair of differential signal lines 64a, 64b, the first pair of differential vias 54a, 54b, and the first pair of differential solder ball pads 74a, 74b are shown (hereinafter, the first pair of differential signal lines 64a, 64b are used for explanation. To save space, the corresponding component names are not described as "first pair"). Figure 3 It can be seen that the substrate 10 is a multilayer board, the differential board contacts 14a, 14b and the differential signal lines 64a, 64b are located on the top layer of the substrate 10, the differential solder ball pads 74a, 74b are located on the bottom layer of the substrate 10, the differential signal lines 64a, 64b are electrically connected to the differential vias 54a, 54b, and the differential vias 54a, 54b are electrically connected to the top layer and the bottom layer, and are electrically connected to the differential solder ball pads 74a, 74b located on the bottom layer. In addition, the solder balls 30a, 30b are electrically connected to the corresponding differential solder ball pads 74a, 74b.

[0034] The differential signal line 64a includes a wiring segment 80a, a proximity segment 82a, and a divergent segment 84a that are electrically connected in sequence, and the differential signal line 64b includes a wiring segment 80b, a proximity segment 82b, and a divergent segment 84b that are electrically connected in sequence. The two ends of the differential signal line 64a are electrically connected to the differential board contact 14a and the differential via 54a, respectively, and the two ends of the differential signal line 64b are electrically connected to the differential board contact 14b and the differential via 54b, respectively, that is, one end of the wiring segments 80a, 80b is electrically connected to the differential board contacts 14a, 14b, respectively, and one end of the divergent segments 84a, 84b is electrically connected to the differential vias 54a, 54b, respectively.

[0035] The wiring segments 80a and 80b are substantially arranged in parallel, so the lengths of the two wiring segments 80a and 80b are substantially the same. In some embodiments, the wiring segments 80a and 80b include a plurality of turns, and the number and angle of the turns depend on the overall wiring requirements of the substrate 10. The wiring segments 80a and 80b turn into adjacent segments 82a and 82b at an appropriate distance from the differential solder ball pads 74a and 74b. The adjacent segments 82a and 82b are substantially arranged in parallel and substantially symmetrical to the pad connection line L2 (see FIG. Figure 2 ), therefore, the lengths of the two adjacent segments 82a, 82b are substantially the same. In some embodiments, the lengths of each pair of adjacent segments 82a, 82b are substantially different (e.g. Figure 2The length of the proximity segments 82a, 82b of the first pair of differential signal lines 64a, 64b is different from that of the proximity segments of the second pair of differential signal lines 66a, 66b. In some embodiments, the lengths of each pair of proximity segments 82a, 82b are substantially the same. When the proximity segments 82a, 82b are a predetermined distance (to be described later) from the differential solder ball pads 74a, 74b, the two proximity segments 82a, 82b are respectively turned into divergent segments 84a, 84b. The divergent segments 84a, 84b are substantially symmetrical to the pad connection line L2, so the lengths of the divergent segments 84a, 84b are substantially the same. Therefore, the lengths of the differential signal lines 64a, 64b are substantially the same, so the time for the differential signal to be transmitted between the differential board contacts 14a, 14b and the differential vias 54a, 54b is substantially the same, and the quality of the differential signal transmission is correspondingly improved. In some embodiments, the aforementioned symmetry may be at least one of length symmetry, width symmetry, and shape symmetry.

[0036] Next, to explain Figure 2 For the signal transmission characteristics of the embodiment, please refer to Figure 4 , Figure 4 A partial schematic diagram of a chip, wiring and solder ball pads of a ball grid array package according to some embodiments is shown. Figure 4 The embodiment of the present invention is a ball grid array package of the previous generation of the inventor, wherein the differential signal lines 69a, 69b are used to electrically connect the differential board contacts 19a, 19b to the differential vias 59a, 59b, respectively. Figure 4 In the embodiment of the present invention, the differential vias 59a, 59b are located on the same side of the pad connection line L2 (ie Figure 4 The right side of the pad connection L2), the differential signal lines 69a, 69b do not have Figure 3 The proximal sections 82a, 82b and the divergent sections 84a, 84b of the embodiment include traces with larger turning angles to electrically connect to the differential vias 59a, 59b. When the angle between the contact line L1 and the pad line L2 is substantially 45 degrees, between 45 degrees and 90 degrees, or substantially 90 degrees (substantially vertical, such as Figure 4 ), the turning angle of the differential signal lines 69a, 69b causes a length difference between the two differential signal lines 69a, 69b. This length difference makes the differential signal lines 69a, 69b transmit differential signals worse than Figure 2 Embodiment of.

[0037] See also Figure 5 , Figure 5 Draw Figure 2 and Figure 4The differential return loss (DRL) graph of a pair of differential signal lines in the figure. The horizontal axis of the differential return loss graph represents the frequency in GHz (10 9 The vertical axis represents differential return loss in dB (decibel). Figure 5 The mark RL4 is Figure 4 The differential reflection loss curve RL4 of the differential signal lines 69a and 69b is obtained by inputting the differential signal from the differential crystal contacts 24a and 24b at the chip 20 and receiving the reflected signal strength from the differential crystal contacts 24a and 24b to obtain the differential reflection loss curve RL4. Figure 5 The RL2 is marked as Figure 2 The differential reflection loss curve RL2 of the differential signal lines 64a and 64b is shown in FIG. 1 . The differential signal is input from the differential crystal contacts 24a and 24b at the chip 20, and the reflected signal strength is received from the differential crystal contacts 24a and 24b to obtain the differential reflection loss curve RL2. As can be seen from the comparison in the figure, when the signal frequency is less than about 18 GHz (corresponding to about 36 Gbps, 36 x 10 9 bit rate), Figure 2 The differential reflection loss curve RL2 of the embodiment is better than Figure 4 The differential reflection loss curve RL4 of the embodiment. Therefore, Figure 4 When the embodiment meets the transmission requirements of differential signals, Figure 2 The embodiment has better performance in differential reflection loss in applications with a rate less than about 36 Gbps.

[0038] See also Figure 6 , Figure 6 Draw Figure 2 and Figure 4 The differential insertion loss (DIL) graph of a pair of differential signal lines in the figure. The horizontal axis of the differential insertion loss graph represents frequency in GHz, and the vertical axis represents differential insertion loss in dB. Figure 6 IL4 is marked as Figure 4 The differential insertion loss curve IL4 of the differential signal lines 69a and 69b is shown in FIG. 1 . The differential signal is input from the differential contacts 24a and 24b at the chip 20 end, and is received from the solder balls 30a and 30b to obtain the differential insertion loss curve IL4. Similarly, Figure 6 IL2 is marked as Figure 2The differential signal is input from the differential contacts 24a, 24b of the chip 20, and received from the solder balls 30a, 30b to obtain the differential insertion loss curve IL2. As can be seen from the comparison in the figure, when the signal frequency is less than about 27GHz (corresponding to about 54Gbps, 54x 10 9 bit rate), Figure 2 The differential insertion loss curve IL2 of the embodiment is better than Figure 4 The differential insertion loss curve IL4 of the embodiment of FIG. From the differential insertion loss graph, it can be seen that even if Figure 2 The differential signal lines 64a, 64b of the embodiment include branch segments 84a, 84b. The branch segments 84a, 84b are quasi-single-ended signal lines. The effect of quasi-single-ended signal lines in transmitting differential signals is usually poor. Figure 2 The differential insertion loss curve IL2 of the differential signal lines 64a, 64b in the embodiment for transmitting differential signals is still better than Figure 4 The differential insertion loss curve IL4 of the embodiment. Therefore, in Figure 4 When the embodiment meets the transmission requirements of differential signals, Figure 2 The embodiment has better performance in differential insertion loss in applications with a rate less than about 54 Gbps.

[0039] See also Figure 7 , Figure 7 Draw Figure 2 and Figure 4 The insertion loss diagram of the mode conversion of the differential-mode signal (differential-mode signal) to common-mode noise (common-mode noise) of a pair of differential signal lines. The horizontal axis of the insertion loss diagram represents the frequency in GHz; the vertical axis represents the insertion loss of the mode conversion in dB. Figure 7 The MC4 is marked as Figure 4 Insertion loss curve MC4 of the mode conversion of the differential signal lines 69a, 69b, the differential-mode signal is input from the differential crystal contacts 24a, 24b at the chip 20 end, and receives the common-mode noise generated by the wiring of the differential signal from the solder balls 30a, 30b to obtain the insertion loss curve MC4 of its mode conversion. Figure 4 The differential signal lines 69a, 69b have a relatively large turning angle, so the symmetry of the positive and negative differential signal lines 69a, 69b is not good enough. The poor symmetry indirectly causes common-mode noise to be generated in the transmission of the differential signal. Figure 7 MC2 is marked as Figure 2The insertion loss curve MC2 of the modal conversion of the differential signal lines 64a, 64b is shown in FIG. The differential modal signal is input from the differential crystal contacts 24a, 24b at the chip 20 end, and the common mode noise generated by the wiring of the differential signal is received from the solder balls 30a, 30b to obtain the insertion loss curve MC2 of the modal conversion. As can be seen from the comparison in the figure, Figure 2 The insertion loss curve MC2 of the mode conversion of the embodiment is better than Figure 4 The insertion loss curve MC4 of the modal conversion of the embodiment is about 6dB.

[0040] See also Figure 8 , Figure 8 Draw Figure 2 and Figure 4 The differential time domain reflectometry (TDR) diagram of a pair of differential signal lines in the figure shows time in nanoseconds (ns, 10 -9 seconds); the vertical axis represents the time domain reflection impedance in Ohms. Figure 8 The TDR4 indicated in the figure is Figure 4 The differential time domain reflection curve TDR4 of the differential signal lines 69a and 69b is shown in FIG. 4. The impedance of the time domain reflectometer is 100 ohms. The test signal of the time domain reflectometer is input from the solder balls 30a and 30b and transmitted to the differential crystal contacts 24a and 24b. That is, the start time of the horizontal axis of the differential time domain reflection graph is calculated from the input of the test signal from the solder balls 30a and 30b. Figure 4 The preset impedance (also called design impedance) of the differential signal lines 69a and 69b is 90 ohms. Figure 8 The interval marked BV4 (horizontal axis about 2.5 to 2.53ns interval) reflects the impedance curve of the test signal transmitted from the solder balls 30a, 30b to the differential vias 59a, 59b. After the test signal enters the differential signal lines 69a, 69b (horizontal axis about 2.53ns later), the measured impedance rises to close to the preset impedance of 90 ohms. The position marked W4 indicates the time point when the test signal leaves the differential board contacts 19a, 19b and enters the differential leads 17a, 17b. It can be seen from the figure that the lowest impedance value between the solder balls 30a, 30b and the differential vias 59a, 59b is about 77 ohms, which is about 13 ohms lower than the preset impedance (90 ohms).

[0041] Figure 8 TDR2 is marked as Figure 2 The differential time domain reflection curve TDR2 of the differential signal lines 64a and 64b is shown in FIG. 2 . The test signal of the time domain reflectometer is input from the solder balls 30a and 30b and transmitted to the differential crystal contacts 24a and 24b. Figure 2 The default impedance of the differential signal lines 64a, 64b is 90 ohms. Figure 8The interval marked BV2 (horizontal axis approximately 2.5 to 2.53ns interval) reflects the impedance curve of the test signal transmitted from the solder balls 30a, 30b to the differential vias 54a, 54b, and the interval marked BS (horizontal axis approximately 2.53 to 2.54ns interval) reflects the impedance curve BS measured by the test signal in the divergent segments 84a, 84b. The interval after the BS mark to W2 is the impedance measured by the test signal in the proximity segments 82a, 82b and the wiring segments 80a, 80b (horizontal axis approximately 2.54ns later), which is close to the preset impedance of 90 ohms. The position marked W2 indicates the time point when the test signal leaves the differential board contacts 14a, 14b and enters the differential leads 17a, 17b. As can be seen in the figure, due to Figure 2 The distance between the differential communication holes 54a and 54b in the embodiment is relatively large. Figure 4 The distance between the differential connecting holes 59a and 59b in the embodiment of FIG. 5 is long, therefore, Figure 2 The impedance of the differential vias 54a, 54b is higher than the impedance of the differential vias 59a, 59b, so that Figure 2 The impedance value between the solder balls 30a, 30b and the differential vias 59a, 59b of the embodiment is about 86 ohms at the lowest and about 95 ohms at the highest. The impedance value is between plus and minus 5 ohms of the preset impedance (90 ohms). Figure 2 The impedance between the solder balls 30a, 30b and the differential vias 59a, 59b of the embodiment is relatively Figure 4 The embodiment is closer to the preset impedance.

[0042] From the above, we can see that Figure 2 Example compared to Figure 4 The embodiment has better electrical characteristics.

[0043] Figure 2 Although the chip 20 is shown to include multiple pairs of differential crystal contacts 24a, 24b, 26a, 26b, the implementation is not limited thereto. The chip 20 may include only one pair of differential crystal contacts 24a, 24b or 26a, 26b. Similarly, the substrate 10 may include only one pair of differential board contacts 14a, 14b or 16a, 16b, one pair of differential signal lines 64a, 64b or 66a, 66b, and one pair of differential vias 54a, 54b or 56a, 56b.

[0044] Please refer to Fig. 9 , Fig. 9 A partial enlarged view of a pair of differential signal lines is shown according to some embodiments. In some embodiments, the divergent segments 84a, 84b extend from the proximal segments 82a, 82b toward the pad connection L2 (see FIG. Figure 2), the distance D1 (hereinafter referred to as the first distance) between the connection point between the divergent segments 84a, 84b and the adjacent segments 82a, 82b and the differential solder ball pad 74a is about 100 microns (um) to 250 microns. Figure 3 It can be seen that the divergent segments 84a, 84b are located on the top layer of the substrate 10, and the differential solder ball pad 74a is located on the bottom layer of the substrate 10. The first distance D1 refers to the distance from Fig. 9 Perspective (i.e. Figure 3 (top view), the distance from the center point of the two connections between the divergent segments 84a, 84b and the proximal segments 82a, 82b to the edge of the differential solder ball pad 74a along the pad connection line L2.

[0045] In some embodiments, the branch segments 84a, 84b include oblique segments 86a, 86b, straight segments 88a, 88b, and lead-in segments 89a, 89b. The oblique segments 86a, 86b are electrically connected to the proximity segments 82a, 82b, respectively. The straight segments 88a, 88b are substantially parallel to the pad connection line L2 and have their two ends electrically connected to the oblique segments 86a, 86b and the lead-in segments 89a, 89b, respectively. The lead-in segments 89a, 89b are electrically connected to the differential vias 54a, 54b, respectively.

[0046] In some embodiments, the angle θ between the oblique segments 86a, 86b and the pad connection line L2 is approximately between 35 degrees and 55 degrees (for example, 45 degrees), each oblique segment 86a, 86b is approximately 50 to 150 microns away from the adjacent differential solder ball pad 74a (hereinafter referred to as the second distance D2), each straight segment is approximately 50 to 150 microns away from the adjacent solder ball pad (hereinafter referred to as the third distance D3), the outer diameter of each solder ball pad is approximately 300 microns to 600 microns (hereinafter referred to as the fourth distance D4), and the distance between the differential connecting holes 54a, 54b is approximately 70 to 600 microns (hereinafter referred to as the fifth distance D5). The second, third, fourth, and fifth distances D2, D3, D4, and D5 refer to the distances from Fig. 9 Perspective (i.e. Figure 3 The distance between the top view and the

[0047] In some embodiments, the differential vias 54a, 54b are located on the plumb line of the midpoint of the pad connection line L2 (the line connecting the center points of the differential solder ball pads 74a, 74b), so the lengths of the electrical connections between the vias 54a, 54b and the differential solder ball pads 74a, 74b are substantially the same. The lengths from the paired differential board contacts 14a, 14b, 16a, 16b of the substrate 10 to the differential solder ball pads 74a, 74b, 76a, 76b are substantially the same, so that the transmission time difference of the differential signal is reduced.

[0048] In some embodiments, please also refer to Figure 8 and Fig. 9, the lengths of the branch segments 84a, 84b and the fifth distance D5 have a predetermined relationship, and the predetermined relationship makes the impedance of the two differential vias 54a, 54b lower than the preset impedance (ie, the design impedance) and the impedance of the two branch segments 84a, 84b higher than the preset impedance. Figure 8 As shown, Figure 4 The impedance curve BV4 of the solder balls 30a, 30b and the differential vias 54a, 54b of the embodiment is lower than the preset impedance and is Figure 2 The impedance curve BV2 of the embodiment is low. In some embodiments, the distance between the differential vias 54a and 54b (the fifth distance D5) can be adjusted to appropriately control the impedance of the differential vias 54a and 54b, that is, increasing the distance between the differential vias 54a and 54b increases the impedance of the differential vias 54a and 54b. Secondly, the branch segments 84a and 84b are quasi-single-ended signal lines, and their impedance (i.e. Figure 8 The impedance curve BS of the embodiment is that the preset impedance of the closer connecting segments 82a, 82b and the wiring segments 80a, 80b is high. Therefore, by adjusting the length of the branching segments 84a, 84b, the impedance of the branching segments 84a, 84b can be adjusted. The longer the length of the branching segments 84a, 84b is, the higher the impedance is. In this embodiment, by adjusting the predetermined relationship between the length of the branching segments 84a, 84b and the fifth distance D5, the impedance of the two differential vias 54a, 54b can be lower than the preset impedance (i.e., the design impedance) and the impedance of the two branching segments 84a, 84b is higher than the preset impedance (i.e., the design impedance). Figure 8 The impedance curve between BV2 and BS in the circuit is obtained to obtain better transmission quality of differential signal lines. The adjustment method of the predetermined relationship includes, for example but not limited to, adjusting the angle θ between the oblique segments 86a, 86b and the pad connection line L2, adjusting the second distance D2, adjusting the third distance D3, adjusting the angle between the straight segments 88a, 88b and the oblique segments 86a, 86b, lengthening or shortening the length of the lead-in segments 89a, 89b (or even removing the entire lead-in segments 89a, 89b, which will be described later), etc. In addition, the length of the divergent sections 84a, 84b and the upper and lower limits of the fifth distance D5 are constrained by the overall wiring of the substrate 10. For example, the divergent sections 84a, 84b and the adjacent wiring need to maintain a standard distance to maintain the signal transmission quality between the divergent sections 84a, 84b and the adjacent wiring. For example, the distance between the differential connecting holes 54a, 54b (the fifth distance D5) cannot be so short that the signal quality transmitted by the differential connecting holes 54a, 54b is affected, and the fifth distance D5 cannot be so large that the differential connecting holes 54a, 54b are too close to the adjacent wiring to affect their signal transmission quality.

[0049] Please continue to refer to Fig.10 , Fig.10A partial enlarged view of a pair of differential signal lines according to some embodiments is shown. In some embodiments, the branch segments 84a', 84b' include oblique segments 86a', 86b' and straight segments 88a', 88b', the oblique segments 86a', 86b' are electrically connected to the proximity segments 82a, 82b, respectively, and the straight segments 88a', 88b' are substantially parallel to the pad connection line L2 and are electrically connected to the differential vias 54a, 54b, respectively. Fig.10 The fifth distance D5' of the embodiment is Fig. 9 The fifth distance D5 is long, so that Fig.10 The diverging sections 84a', 84b' of the embodiment do not have the introduction subsections 89a, 89b. Fig.10 The angle θ' between the oblique segments 86a', 86b' and the pad connection line L2 is relatively large. Fig. 9 The angle θ between the oblique segments 86a, 86b and the pad connection line L2 is small. In this embodiment, Fig.10 The length of the first distance D1' shown in Fig. 9 In some embodiments (not shown in the drawings), the diverging segments 84a, 84b include oblique segments 86a, 86b, and lead-in segments 89a, 89b, but no straight segments 88a, 88b, i.e., the oblique segments 86a, 86b and lead-in segments 89a, 89b are arranged in a slightly diamond shape.

[0050] Please refer to Figure 2 and Figure 3 According to some embodiments, a package substrate 10 is suitable for packaging a chip 20, and the chip 20 has two differential crystal contacts 24a, 24b. The package substrate 10 includes two differential board contacts 14a, 14b, two differential solder ball pads 74a, 74b, two differential vias 54a, 54b, and two differential signal lines 64a, 64b. The connection line of the two differential board contacts 14a, 14b is a contact connection line L1, and the two differential board contacts 14a, 14b are suitable for electrically connecting the two differential crystal contacts 24a, 24b. The connection line of the two differential solder ball pads 74a, 74b is a pad connection line L2, and the contact connection line L1 is substantially perpendicular to the pad connection line L2. The two differential vias 54a, 54b are substantially symmetrical to the pad connection line L2, and the two differential vias 54a, 54b are respectively electrically connected to the two differential solder ball pads 74a, 74b. Each differential signal line 64a, 64b includes a wiring segment 80a, 80b, a proximity segment 82a, 82b, and a divergent segment 84a, 84b connected in sequence, the two wiring segments 80a, 80b are respectively electrically connected to the two differential board contacts 14a, 14b and are substantially arranged in parallel, the two proximity segments 82a, 82b are substantially arranged in parallel and substantially symmetrical to the pad connection line L2, and the two divergent segments 84a, 84b are substantially symmetrical to the pad connection line L2 and are respectively electrically connected to the two differential vias 54a, 54b.

[0051] Therefore, the packaging substrate 10 can better transmit differential signals when packaging the differential die contacts of the chip.

[0052] In summary, in some embodiments, the differential signal line of the package substrate includes a diverging section, which is symmetrical to the pad connection and electrically connected to the differential via, and the differential via is also symmetrical to the pad connection. Therefore, the lengths of the two differential signal lines in the same pair of differential signal lines are substantially the same, reducing the time difference in differential signal transmission. In some embodiments, by adjusting the relationship between the length of the diverging section and the fifth distance, the impedance of the differential signal line and the differential via can be made closer to the design impedance.

[0053]

Explanation of symbols

[0054] 10:Substrate

[0055] 14a: Differential board contact

[0056] 14b: Differential board contact

[0057] 16a: Differential board contact

[0058] 16b: Differential board contact

[0059] 17a: Differential leads

[0060] 17b: Differential lead

[0061] 17c: General lead

[0062] 18: General board contact

[0063] 19a: Differential board contact

[0064] 19b: Differential board contact

[0065] 20: Chip

[0066] 22: Chip contacts

[0067] 24a: Differential crystal contact

[0068] 24b: Differential crystal contact

[0069] 26a: Differential crystal contact

[0070] 26b: Differential crystal contact

[0071] 28: General crystal contact

[0072] 30: Solder ball

[0073] 30a: Solder ball

[0074] 30b: Solder ball

[0075] 40: Covering body

[0076] 52: Connecting hole

[0077] 54a: Differential communication hole

[0078] 54b: Differential communication hole

[0079] 56a: Differential communication hole

[0080] 56b: Differential communication hole

[0081] 58: General connecting hole

[0082] 59a: Differential communication hole

[0083] 59b: Differential communication hole

[0084] 62:Signal line

[0085] 64a: Differential signal line

[0086] 64b: Differential signal line

[0087] 66a: Differential signal line

[0088] 66b: Differential signal line

[0089] 68: General signal line

[0090] 69a: Differential signal line

[0091] 69b: Differential signal line

[0092] 72: Solder ball pad

[0093] 74a: Differential solder ball pad

[0094] 74b: Differential solder ball pad

[0095] 76a: Differential solder ball pad

[0096] 76b: Differential solder ball pad

[0097] 78: General solder ball pad

[0098] 80a: Wiring segment

[0099] 80b: Wiring segment

[0100] 82a: close section

[0101] 82b: close section

[0102] 84a: Divergence

[0103] 84a': Divergence segment

[0104] 84b: Divergence

[0105] 84b': Divergence segment

[0106] 86a: oblique sub-segment

[0107] 86a': oblique sub-segment

[0108] 86b: oblique sub-segment

[0109] 86b': oblique sub-segment

[0110] 88a: Straight segment

[0111] 88a': Straight segment

[0112] 88b: Straight segment

[0113] 88b': Straight segment

[0114] 89a: Introduce subsection

[0115] 89b: Introduce subsection

[0116] BV2: Impedance curve

[0117] BV4: Impedance curve

[0118] BS: Impedance curve

[0119] D1: First distance

[0120] D1': First distance

[0121] D2: Second distance

[0122] D3: The third distance

[0123] D4: The fourth distance

[0124] D5: The fifth distance

[0125] D5': Fifth distance

[0126] IL2: Differential Insertion Loss Curve

[0127] IL4: Differential Insertion Loss Curve

[0128] L1: Contact connection

[0129] L1': Contact connection

[0130] L2: solder pad connection

[0131] L2': solder pad connection

[0132] MC2: Insertion loss curve of mode conversion

[0133] MC4: Insertion loss curve of mode conversion

[0134] RL2: Differential reflection loss curve

[0135] RL4: Differential reflection loss curve

[0136] TDR2: Differential Time Domain Reflectometry

[0137] TDR4: Differential Time Domain Reflectometry

[0138] θ': Angle

[0139] θ: Angle

Claims

1. A ball grid array package, comprising: A chip comprising two chip contacts; and A substrate comprising: Two board contacts, one connection line of the two board contacts is a contact connection line, and the two chip contacts are electrically connected to the two board contacts; Two solder ball pads, one connection line of the two solder ball pads is a solder pad connection line, and the contact connection line is not substantially parallel to the solder pad connection line; two connecting holes, the two connecting holes are substantially symmetrical to the pad connection line, and the two connecting holes are electrically connected to the two solder ball pads respectively; and Two signal lines, each of which includes a wiring segment, a proximity segment, and a divergent segment connected in sequence, the two wiring segments are electrically connected to the two board contacts and are substantially arranged in parallel, the two proximity segments are substantially arranged in parallel and are substantially symmetrical to the pad connection, and the two divergent segments are substantially symmetrical to the pad connection and are electrically connected to the two connecting holes.

2. The ball grid array package according to claim 1, wherein: The lengths of the two branching sections are substantially the same.

3. The ball grid array package according to claim 1, wherein: Each of the branch segments sequentially comprises an oblique segment, a straight segment and an introduction segment, the two oblique segments are respectively electrically connected to the two adjacent segments, the two straight segments are substantially parallel to the solder ball pad connection line, and the two introduction segments are respectively electrically connected to the two connecting holes.

4. The ball grid array package according to claim 3, wherein: The distance between each connection point between the divergent segment and the proximal segment and the solder ball pad is 100 to 250 microns, the angle between each oblique segment and the connecting line of the solder ball pad is between 35 and 55 degrees, each oblique segment is 50 to 150 microns away from the adjacent solder ball pad, each straight segment is 50 to 150 microns away from the adjacent solder ball pad, and the outer diameter of each solder ball pad is 300 to 600 microns.

5. The ball grid array package according to any one of claims 1 to 4, wherein: The two solder ball pads are close to one side of the substrate, and the solder pad connection line is substantially perpendicular to the side.

6. A packaging substrate, the packaging substrate comprising: Two plate contacts, one connecting line of the two plate contacts is a contact connecting line; Two solder ball pads, one connection line of the two solder ball pads is a solder pad connection line, and the contact connection line is not substantially parallel to the solder pad connection line; two connecting holes, the two connecting holes are substantially symmetrical to the pad connection line, and the two connecting holes are electrically connected to the two solder ball pads respectively; and Two signal lines, each of which includes a wiring segment, a proximity segment, and a divergent segment connected in sequence, the two wiring segments are electrically connected to the two board contacts and are substantially arranged in parallel, the two proximity segments are substantially arranged in parallel and are substantially symmetrical to the pad connection, and the two divergent segments are substantially symmetrical to the pad connection and are electrically connected to the two connecting holes.

7. The packaging substrate according to claim 6, wherein: The lengths of the two branching sections are substantially the same.

8. The packaging substrate according to claim 6, wherein: Each of the branch segments sequentially comprises an oblique segment, a straight segment and an introduction segment, the two oblique segments are respectively electrically connected to the two adjacent segments, the two straight segments are substantially parallel to the pad connection line, and the two introduction segments are respectively electrically connected to the two connecting holes.

9. The packaging substrate according to claim 8, wherein: The distance between each connection point between the divergent segment and the proximal segment and the solder ball pad is 100 to 250 microns, the angle between each oblique segment and the solder pad connection line is between 35 and 55 degrees, each oblique segment is 50 to 150 microns away from the adjacent solder ball pad, each straight segment is 50 to 150 microns away from the adjacent solder ball pad, and the outer diameter of each solder ball pad is 300 to 600 microns.

10. The packaging substrate according to any one of claims 6 to 9, wherein: The two solder ball pads are close to one side of the substrate, and the solder pad connection line is substantially perpendicular to the side.

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