Semiconductor element and method for manufacturing the same

Abstract

The invention discloses a semiconductor element and a preparation method thereof. In the semiconductor element, a side of an epitaxial layer away from a substrate includes a groove; an oxide layer is located in the groove; a gate polysilicon layer and a source polysilicon layer are both embedded in the oxide layer and separated by the oxide layer; a body region and a source region are both located on the left and right sides of the gate polysilicon layer, and the body region is located on the side of the source region close to the substrate; a source electrode is located on the side of the body region away from the substrate and is electrically connected to the source region and the source polysilicon layer, and the source polysilicon layer includes at least two source polysilicon sublayers stacked in a direction perpendicular to the substrate; the type of doping ions in the source polysilicon layer is opposite to the type of doping ions in the source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the groove is lower than the concentration of doping ions in the source polysilicon sublayer away from the bottom of the groove; the total amount of charge required by the MOSFET during the reverse recovery of the body diode is reduced, thereby reducing the drain-source voltage spike.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor element and a method for manufacturing the same. Background Art

[0002] Compared with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs), deep-channel MOSFETs have better figure of merit (FOM). Due to the use of electrically balanced design, split-gate power MOSFETs can achieve both low on-resistance and low reverse transfer capacitance, thereby reducing the conduction loss and switching loss of the system and improving the efficiency of electronic products.

[0003] However, also because of the split-gate design, the lower gate is actually connected to the source, which increases the output capacitance (Coss) of the SGTMOSFET. The output capacitance mainly includes the capacitance Cds between the drain and the source. In practical applications, such as resonant topology power supplies or brushless motor applications, the MOSFET body diode will experience reverse recovery during each switching process. When the body diode reverses, the capacitance Cds between the drain and the source is large in both the low voltage section and the high voltage section of the drain-source voltage VDS, making the drain-source voltage VDS prone to excessive spikes, which directly leads to MOSFET overvoltage failure. Therefore, how to reduce the drain-source voltage VDS spike has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor element and a method for preparing the same, so as to reduce the capacitance between the drain and the source in the entire voltage range of the drain-source voltage, thereby reducing the total amount of charge required for the MOSFET during reverse recovery of the body diode, thereby reducing the drain-source voltage VDS peak and ensuring good performance of the MOSFET.

[0005] In a first aspect, an embodiment of the present invention provides a semiconductor element, including:

[0006] substrate;

[0007] An epitaxial layer is located on one side of the substrate, and a side of the epitaxial layer away from the substrate includes a trench;

[0008] an oxide layer located in the trench;

[0009] The gate polysilicon layer and the source polysilicon layer are both embedded in the oxide layer; the gate polysilicon layer and the source polysilicon layer are separated by the oxide layer, and the oxide layer at least exposes the surface of the gate polysilicon layer away from the substrate;

[0010] The body region and the source region are both formed in one end of the epitaxial layer away from the substrate; the body region and the source region are both located on the left and right sides of the gate polysilicon layer; relative to the source region, the body region is located on the side of the source region close to the substrate;

[0011] A source electrode, located at a side of the body region away from the substrate and electrically connected to the source region and the source polysilicon layer;

[0012] Among them, the source polysilicon layer includes at least two source polysilicon sublayers, and the at least two source polysilicon sublayers are stacked in a direction perpendicular to the substrate; the type of doping ions in the gate polysilicon layer is opposite to the type of doping ions in each source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench.

[0013] Optionally, the concentration of doped ions in the same source polysilicon sublayer is the same.

[0014] Optionally, the concentration of doped ions in the same source polysilicon sublayer is distributed in a gradient, and the concentration of doped ions is positively correlated with the height of the doping position relative to the bottom of the trench.

[0015] Optionally, the doping ions of the substrate, the epitaxial layer, the source region and the gate polysilicon layer are all of P type; the doping ions of the body region and the source polysilicon layer are all of N type.

[0016] Alternatively, the doping ions of the substrate, the epitaxial layer, the source region and the gate polysilicon layer are all of N type; and the doping ions of the body region and the source polysilicon layer are of P type.

[0017] Optionally, the gate polysilicon layer is located on a side of the source polysilicon layer away from the substrate;

[0018] The oxide layer between the gate polysilicon layer and the trench is a first oxide layer;

[0019] The oxide layer between the gate polysilicon layer and the source polysilicon layer is an intermediate oxide layer;

[0020] The oxide layer between the source polysilicon layer and the trench is a second oxide layer;

[0021] Wherein, the intermediate oxide layer and the first oxide layer are integrally formed.

[0022] Optionally, the gate polysilicon layer surrounds the source polysilicon layer;

[0023] The oxide layer exposes a surface of the gate polysilicon layer away from the substrate and a surface of the source polysilicon layer away from the substrate; the surface of the gate polysilicon layer away from the substrate is flush with the surface of the source polysilicon layer away from the substrate; the distance between the surface of the gate polysilicon layer close to the substrate and the bottom of the trench is smaller than the distance between the surface of the source polysilicon layer close to the substrate and the bottom of the trench;

[0024] The oxide layer between the gate polysilicon layer and the trench is a first oxide layer;

[0025] The oxide layer between the gate polysilicon layer and the source polysilicon layer is an intermediate oxide layer;

[0026] The oxide layer between the source polysilicon layer and the trench is a second oxide layer;

[0027] Wherein, the first oxide layer, the middle oxide layer and the second oxide layer are integrally formed.

[0028] Optionally, the semiconductor element further includes: a drain electrode, wherein the drain electrode is located on a side of the substrate away from the epitaxial layer and is electrically connected to the substrate.

[0029] In a second aspect, an embodiment of the present invention provides a method for preparing a semiconductor element, the method comprising:

[0030] providing a substrate;

[0031] forming an epitaxial layer on one side of the substrate, wherein a side of the epitaxial layer away from the substrate comprises a trench;

[0032] An oxide layer, a gate polysilicon layer and a source polysilicon layer are formed in the trench, wherein the gate polysilicon layer and the source polysilicon layer are both embedded in the oxide layer, the gate polysilicon layer and the source polysilicon layer are separated by the oxide layer, and the oxide layer at least exposes a surface of the gate polysilicon layer away from the substrate;

[0033] A body region and a source region are formed in one end of the epitaxial layer away from the substrate, wherein the body region and the source region are both located on the left and right sides of the gate polysilicon layer; relative to the source region, the body region is located on a side of the source region close to the substrate;

[0034] forming a source electrode on a side of the body region away from the substrate;

[0035] Among them, the source polysilicon layer includes at least two source polysilicon sublayers, and the at least two source polysilicon sublayers are stacked in a direction perpendicular to the substrate; the type of doping ions in the gate polysilicon layer is opposite to the type of doping ions in each source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench.

[0036] Optionally, the oxide layer includes a first oxide layer, an intermediate oxide layer, and a second oxide layer; and forming the oxide layer, the gate polysilicon layer, and the source polysilicon layer in the trench includes:

[0037] forming a second oxide layer at the bottom of the trench, the sidewalls of the trench, and the surface of the epitaxial layer away from the substrate;

[0038] At least two first intrinsic polysilicon layers are sequentially formed in the space surrounded by the second oxide layer, and first type doping ions of different concentrations are implanted into different first intrinsic polysilicon layers to form a source polysilicon layer; wherein the concentration of the implanted ions in the first intrinsic polysilicon layer close to the bottom of the trench is lower than the concentration of the implanted ions in the first intrinsic polysilicon layer far from the bottom of the trench; and the total height of the at least two first intrinsic polysilicon layers in the trench is less than the depth of the trench;

[0039] removing the second oxide layer which is not covered by the source polysilicon layer and is located on the surface of the epitaxial layer away from the substrate and in the trench;

[0040] forming an initial oxide layer on a side of the source polysilicon layer away from the substrate and on a sidewall of the trench not covered by the source polysilicon layer;

[0041] forming a second intrinsic polysilicon layer in the space surrounded by the initial oxide layer, wherein a surface of the second intrinsic polysilicon layer away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and implanting second type doping ions into the second intrinsic polysilicon layer to form a gate polysilicon layer;

[0042] Wherein, the initial oxide layer between the gate polysilicon layer and the trench is a first oxide layer;

[0043] The initial oxide layer between the gate polysilicon layer and the source polysilicon layer is an intermediate oxide layer;

[0044] When the first type doping ions are P-type doping ions, the second type doping ions are N-type doping ions; when the first type doping ions are N-type doping ions, the second type doping ions are P-type doping ions.

[0045] Optionally, forming an oxide layer, a gate polysilicon layer and a source polysilicon layer in the trench includes:

[0046] forming an oxide layer in the trench;

[0047] Etching the oxide layer to form a source trench on a side of the oxide layer away from the substrate;

[0048] At least two first intrinsic polysilicon layers are formed in the source trench, and first type doping ions of different concentrations are implanted into different first intrinsic polysilicon layers to form source polysilicon layers; wherein the concentration of the implanted ions in the first intrinsic polysilicon layer close to the bottom of the trench is lower than the concentration of the implanted ions in the first intrinsic polysilicon layer far from the bottom of the trench; and among the at least two first intrinsic polysilicon layers, the surface of the first intrinsic polysilicon layer farthest from the substrate away from the substrate is flush with the surface of the epitaxial layer away from the substrate;

[0049] Etching the oxide layer to form a gate trench on a side of the oxide layer away from the substrate, wherein the gate trench surrounds the source polysilicon layer, and the gate trench is separated from the source polysilicon layer by the oxide layer;

[0050] forming a second intrinsic polysilicon layer in the gate trench, wherein a surface of the second intrinsic polysilicon layer away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and implanting second type doping ions into the second intrinsic polysilicon layer to form a gate polysilicon layer;

[0051] When the first type of doping ions are P-type doping ions, the second type of doping ions are N-type doping ions; when the first type of doping ions are N-type doping ions, the second type of doping ions are P-type doping ions.

[0052] The semiconductor element and the preparation method thereof provided by the embodiment of the present invention increase the work function difference between the source polysilicon layer and the epitaxial layer by setting the type of doping ions of the source polysilicon layer to be opposite to the type of doping ions of the gate polysilicon layer, thereby reducing the drain-source capacitance CDS of the MOSFET, and on this basis, the source polysilicon layer is set to include at least two source polysilicon sublayers, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench, thereby further reducing the drain-source capacitance CDS at the bottom of the trench, so that the capacitance between the drain and the source has a good reduction effect in the full voltage range of the drain-source voltage, thereby reducing the total charge required by the MOSFET during the reverse recovery of the body diode, thereby reducing the drain-source voltage VDS peak and ensuring the good performance of the MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a body diode reverse recovery simulation circuit diagram provided by an embodiment of the present invention;

[0054] Figure 2 These are several waveform diagrams involved in the reverse recovery of the body diode provided by the embodiments of the present invention;

[0055] Figure 3 is a schematic cross-sectional structure diagram of a semiconductor element provided by an embodiment of the present invention;

[0056] Figure 4 is a curve diagram showing the relationship between drain-source capacitance and drain-source voltage of a semiconductor element provided by an embodiment of the present invention;

[0057] Figure 5 It is a comparison diagram of several waveform diagrams involved in the reverse recovery of the body diode provided in the embodiment of the present invention before and after optimization;

[0058] Figure 6 is a schematic cross-sectional structure diagram of another semiconductor element provided by an embodiment of the present invention;

[0059] Figure 7 It is a flow chart of a method for preparing a semiconductor element provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0061] As mentioned in the background technology, the drain-source voltage VDS of the MOSFET tends to be too large when the body diode reverse recovers. The inventors have found that: for example, referring to Figure 1 , the first transistor T1 is an N-channel MOSFET under test, the second transistor T2 is an N-channel driving MOSFET, the power supply 10 is used to supply power to the first transistor T1, and the inductor L is used to simulate the stray inductance in the loop. Among them, the drain D of the first transistor T1 is electrically connected to the positive electrode + of the power supply 10, the source S of the first transistor T1 is electrically connected to the positive electrode "+" of the power supply 10 through the inductor L, and the gate G of the first transistor T1 is electrically connected to the source S of the first transistor T1; the drain of the second transistor T2 is electrically connected to the source S of the first transistor T1, the source of the second transistor T2 is electrically connected to the negative electrode "-" of the power supply 10, and the gate of the second transistor T2 is electrically connected to the source of the second transistor T2 through the resistor R and the control signal receiving terminal 20 in sequence.

[0062] Combination Figure 1and Figure 2 , from t0 to t1: the gate-source voltage VGS of the first transistor T1 is high, and the second transistor T2 drives the first transistor T1 to be in the on state; the body diode D1 of the first transistor T1 is in the off state, and the current ISD flowing through the body diode D1 is zero; the drain-source voltage VDS of the first transistor T1 is the voltage VDD of the power supply 10. From t1 to t2: the gate-source voltage VGS of the first transistor T1 jumps from a high level to a low level, and the second transistor T2 drives the first transistor T1 from the on state to the off state; the body diode D1 enters the forward conduction state from the off state, and the current ISD flowing through the body diode D1 gradually increases from zero to IF; the drain-source voltage VDS of the first transistor T1 gradually decreases from VDD to VF. From t2 to t3: the gate-source voltage VGS of the first transistor T1 jumps from a low level to a high level; the current ISD flowing through the body diode D1 gradually decreases from IF to zero.

[0063] From time t3, the body diode D1 has a reverse recovery current. At time t4, the reverse voltage of the body diode D1 reaches the voltage VDD of the power supply 10 (that is, the drain-source voltage VDS of the first transistor T1 reaches the voltage VDD), di / dt changes from greater than zero to equal to zero, and the reverse recovery current of the body diode D1 reaches the maximum value. From time t4, the reverse recovery current gradually decays, di / dt changes from equal to zero to less than zero, and a negative voltage is established on the loop stray inductance L, and the terminal voltage of the body diode D1 overshoots. At time t5, the reverse voltage reaches the peak value (that is, the drain-source voltage VDS of the first transistor T1 has a spike). So far, it can be obtained that the negative voltage established on the stray inductance L is L*di / dt; when di / dt is large, the negative voltage is large, so the drain-source voltage VDS spike is large, which easily leads to overvoltage failure of the MOSFET; when di / dt is small, the negative voltage is small, so the drain-source voltage VDS spike is small, which can avoid overvoltage failure of the MOSFET.

[0064] Based on the above, an embodiment of the present invention provides a semiconductor element to reduce the rate of change of current over time during reverse recovery of the body diode, thereby reducing the negative voltage established on the loop stray inductance, improving the overshoot phenomenon of the terminal voltage of the body diode, controlling the drain-source voltage VDS peak to be smaller, avoiding MOSFET overvoltage failure, and ensuring good performance of the MOSFET. Figure 3 is a schematic cross-sectional structure diagram of a semiconductor element provided by an embodiment of the present invention, with reference to Figure 3 , the semiconductor element includes: a substrate 100, an epitaxial layer 110, an oxide layer 140, a gate polysilicon layer 150, a source polysilicon layer 160, a body region 120, a source region 130 and a source electrode 131;

[0065] The epitaxial layer 110 is located on one side of the substrate 100, and the side of the epitaxial layer 110 away from the substrate 100 includes a trench; the oxide layer 140 is located in the trench; the gate polysilicon layer 150 and the source polysilicon layer 160 are both embedded in the oxide layer 140, and the gate polysilicon layer 150 and the source polysilicon layer 160 are separated by the oxide layer 140, and the oxide layer 140 at least exposes the surface of the gate polysilicon layer 150 away from the substrate 100; the body region 12 The gate polysilicon layer 150 and the source region 130 are both formed in the end of the epitaxial layer 110 away from the substrate 100. The body region 120 and the source region 130 are both located on the left and right sides of the gate polysilicon layer 150. The body region 120 is located on the side of the source region 130 close to the substrate 100 relative to the source region 130. The source electrode 131 is located on the side of the body region 120 away from the substrate 100 and is electrically connected to the source region 130. The source polysilicon layer 160 is electrically connected to the source electrode 131. The source polysilicon layer 160 includes at least two source polysilicon sublayers ( Figure 3 In the figure, three layers are drawn as an example, namely, source polysilicon sublayer 161, source polysilicon sublayer 162, and source polysilicon sublayer 163. At least two source polysilicon sublayers are stacked in a direction perpendicular to the substrate. The type of doping ions in the gate polysilicon layer 150 is opposite to the type of doping ions in each source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench. Figure 3 For example, the concentration of doped ions in the source polysilicon sublayer 161 is greater than the concentration of doped ions in the source polysilicon sublayer 162 , and the concentration of doped ions in the source polysilicon sublayer 162 is greater than the concentration of doped ions in the source polysilicon sublayer 163 .

[0066] Among them, the gate polysilicon layer 150 serves as a control gate, and the source polysilicon layer 160 serves as a shielding gate. Since the source polysilicon layer 160 is electrically connected to the source electrode 131, the drain-source capacitor CDS of the semiconductor element is the capacitor between the source polysilicon layer 160 and the epitaxial layer 110. At this time, the source polysilicon layer 160 and the epitaxial layer 110 can be equivalent to two plates of the drain-source capacitor CDS. In addition, the body diode of the semiconductor element is distributed on both sides of the trench, namely the first region 101 and the second region 102. Generally, whether it is an N-channel or P-channel MOSFET, the type of doping ions of the gate polysilicon layer 150 and the source polysilicon layer 160 is the same, the type of doping ions of the source polysilicon layer 160 and the epitaxial layer 110 is the same, and the work function difference between the source polysilicon layer 160 and the epitaxial layer 110 is relatively small, so the equivalent spacing between the two plates of the drain-source capacitor CDS is relatively small, so that the capacitance of the drain-source capacitor CDS is relatively large.

[0067] In the technical solution of the embodiment of the present invention, the types of doping ions of the gate polysilicon layer 150 and the epitaxial layer 110 are set to be the same, and the types of doping ions of the gate polysilicon layer 150 and the source polysilicon layer 160 are opposite, that is, the types of doping ions of the source polysilicon layer 160 and the epitaxial layer 110 are opposite. In this way, the work function difference between the source polysilicon layer 160 and the epitaxial layer 110 is relatively large, that is, the work function difference between the source polysilicon layer 160 and the epitaxial layer 110 is increased, so the equivalent spacing between the two plates of the drain-source capacitor CDS is increased, thereby reducing the capacitance of the drain-source capacitor CDS.

[0068] The purpose of this setting is to combine Figure 2 , the process of the reverse recovery current of the body diode from zero point (t3 moment) to zero point (t6 moment) is also the process of charging the drain-source capacitor CDS, that is, the total charge of the drain-source capacitor CDS depends on the integral of the reverse recovery current from zero point to zero point when the body diode reverse recovers. Since the capacitance of the drain-source capacitor CDS is reduced, the total charge required to charge the drain-source capacitor CDS is reduced, so the current required to charge the overall drain-source capacitor CDS is reduced, then the maximum value of the body diode reverse recovery current is reduced, and the zero point of the reverse recovery current remains unchanged, so di / dt is reduced, and the negative voltage established on the loop stray inductance is reduced, thereby improving the phenomenon of overshoot of the terminal voltage of the body diode, making the drain-source voltage VDS peak smaller, avoiding MOSFET overvoltage failure, and ensuring the good performance of MOSFET. Among them, the charging time of the drain-source capacitor CDS is approximately considered unchanged.

[0069] It can be understood that the amplitude of the drain-source voltage VDS waveform oscillation is positively correlated with the energy stored in the parasitic inductance, and the energy stored in the parasitic inductance is positively correlated with the current. The size of the reverse recovery current spike is related to the properties of the device. The drain-source capacitor CDS needs to be fully charged while the body diode is reversely recovered. When the drain-source capacitor CDS is small, the amount of charge required for full charging is small. When the amount of charge required is small, because the time to fill the drain-source capacitor CDS is almost unchanged, the current is small, so the energy stored in the parasitic inductance is small, and the amplitude of the drain-source voltage VDS waveform oscillation is small.

[0070] It should be noted that the drain-source capacitance CDS has the characteristic of decreasing as the drain-source voltage VDS increases, and during the reverse recovery process of the body diode D1, the drain-source voltage VDS gradually increases from the low voltage segment to the high voltage segment, that is, during the reverse recovery process of the body diode D1, the drain-source capacitance CDS gradually decreases. As the drain-source voltage VDS continues to increase, the electric field is gradually distributed from top to bottom. When the drain-source voltage VDS is in the low voltage segment, the drain-source capacitance CDS is large, at this time the equivalent spacing between the two plates of the drain-source capacitance CDS is relatively close, the value of the equivalent spacing is small, and the change in the equivalent spacing value caused by the difference in work function is relatively large relative to the equivalent spacing at this time. That is, the difference in work function has a greater impact on the drain-source capacitance CDS when the drain-source voltage VDS is low. When the drain-source voltage VDS is in the high voltage segment, the drain-source capacitance CDS is small, at this time the equivalent spacing between the two plates of the drain-source capacitance CDS is relatively far, the value of the equivalent spacing is large, and the change in the equivalent spacing value caused by the difference in work function is relatively small relative to the equivalent spacing at this time. That is, the difference in work function has less effect on the drain-source capacitance CDS when the drain-source voltage VDS is low.

[0071] Therefore, based on the fact that the type of doping ions of the source polysilicon layer is opposite to the type of doping ions of the gate polysilicon layer, in the technical solution of the embodiment of the present invention, the source polysilicon layer is also provided to include at least two source polysilicon sublayers, and the concentration of doping ions of the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions of the source polysilicon sublayer far from the bottom of the trench. This increases the resistance of the source polysilicon sublayer close to the bottom of the trench, blocks the flow of charge on one plate of the drain-source capacitor CDS, and thus can reduce the capacitance value of the drain-source capacitor CDS in the high voltage section of the drain-source voltage VDS. This makes the capacitance between the drain and the source have a good reduction effect in the full voltage section of the drain-source voltage, reduces the total amount of charge required by the MOSFET during the reverse recovery of the body diode, thereby reducing the drain-source voltage VDS peak and improving the good performance of the MOSFET.

[0072] As a supplementary note, Figure 4 1 is a curve diagram showing the relationship between the drain-source capacitance and the drain-source voltage of a semiconductor element provided by an embodiment of the present invention. Figure 4The area enclosed by the drain-source capacitance CDS curve and the drain-source voltage VDS on the horizontal axis is the total charge charged in the drain-source capacitance CDS. By reducing the drain-source capacitance CDS in the low voltage segment of the drain-source voltage VDS, the area enclosed by the drain-source capacitance CDS curve and the drain-source voltage VDS on the horizontal axis can be reduced, thereby reducing the total charge that needs to be charged in the drain-source capacitance CDS. Among them, the drain-source capacitance CDS curve 30-1 is the curve corresponding to when the drain-source capacitance CDS in the low voltage segment of the drain-source voltage VDS is not reduced, and the drain-source capacitance CDS curve 30-2 is the curve corresponding to when the drain-source capacitance CDS in the full voltage segment of the drain-source voltage VDS is reduced.

[0073] As a supplementary note, Figure 5 1 is a comparison diagram of several waveform diagrams involved in the reverse recovery of the body diode provided in the embodiment of the present invention before and after optimization. Figure 5 , the solid ISD curve and the solid VDS curve are Figure 2 The ISD curve and VDS curve in the figure are the ISD curve and VDS curve of the body diode when the types of doping ions in the source polysilicon layer 160 and the gate polysilicon layer 150 of the semiconductor element are the same, and the reverse recovery of the body diode is not optimized at this time; the dotted ISD curve and the dotted VDS curve are the ISD curve and VDS curve of the body diode when the types of doping ions in the source polysilicon layer 160 and the gate polysilicon layer 150 of the semiconductor element are opposite, and the doping concentration of the gate polysilicon layer 150 gradually decreases from the top (away from the bottom of the trench) to the bottom (through the bottom of the trench), and the reverse recovery of the body diode is optimized at this time;

[0074] By comparison, it can be seen that at time t4, the maximum value of the body diode reverse recovery current in the dotted ISD curve is less than the maximum value of the body diode reverse recovery current in the solid ISD curve, and the zero point of the reverse recovery current remains unchanged, so the di / dt of the body diode reverse recovery current in the dotted ISD curve is less than the di / dt of the body diode reverse recovery current in the solid ISD curve, so setting the source polysilicon layer 160 of the semiconductor element and the gate polysilicon layer 150 to have opposite doping ions can reduce the di / dt of the body diode reverse recovery current. Correspondingly, at time t5, the VDS peak in the dotted VDS curve is less than the VDS peak in the solid VDS curve, so setting the source polysilicon layer 160 of the semiconductor element and the gate polysilicon layer 150 to have opposite doping ions can reduce the drain-source voltage VDS peak and improve the phenomenon of overshoot of the terminal voltage of the body diode.

[0075] On the basis of the above embodiments, in order to more specifically illustrate the configuration of the embodiments of the present invention, N-channel and P-channel MOSFETs are taken as examples for exemplary description, but are not intended to limit the present invention.

[0076] In one embodiment of the present invention, optionally, the doping ions of the substrate 100, the epitaxial layer 110, the source region 130 and the gate polysilicon layer 150 are all of P type, and the doping ions of the body region 120 and the source polysilicon layer 160 are all of N type. At this time, the channel type of the semiconductor element is N type, and the doping ions of the gate polysilicon layer 150, the source polysilicon layer 160 and the epitaxial layer 110 are all of P type. However, in the embodiment of the present invention, the doping ion type of the source polysilicon layer 160 is set to N type, so that the difference in work function between the source polysilicon layer 160 and the epitaxial layer 110 is increased, thereby reducing the drain-source capacitance CDS, and further reducing the negative voltage established on the loop stray inductance, ensuring that the drain-source voltage VDS peak is small.

[0077] In another embodiment of the present invention, optionally, the doping ions of the substrate 100, the epitaxial layer 110, the source region 130 and the gate polysilicon layer 150 are all of N type, and the doping ions of the body region 120 and the source polysilicon layer 160 are of P type. At this time, the channel type of the semiconductor element is P type, and the doping ions of the gate polysilicon layer 150, the source polysilicon layer 160 and the epitaxial layer 110 are originally N type, but in the embodiment of the present invention, the doping ion type of the source polysilicon layer 160 is set to P type, so that the difference in work function between the source polysilicon layer 160 and the epitaxial layer 110 is increased, thereby reducing the drain-source capacitance CDS, and then reducing the negative voltage established on the loop stray inductance, ensuring that the drain-source voltage VDS peak is small.

[0078] Optionally, the concentration of doped ions in the same source polysilicon sublayer is the same, that is, the concentration of doped ions in the source polysilicon sublayer 161 is uniformly distributed, the concentration of doped ions in the source polysilicon sublayer 162 is uniformly distributed, and the concentration of doped ions in the source polysilicon sublayer 163 is uniformly distributed, which can simplify the method of doped ion implantation. In another embodiment of the present invention, optionally, the concentration of doped ions in the same source polysilicon sublayer is distributed in a gradient, and the concentration of doped ions is positively correlated with the height of the doping position relative to the bottom of the trench. The concentration of doped ions in the source polysilicon sublayer 161 decreases gradually from top to bottom in a gradient, the concentration of doped ions in the source polysilicon sublayer 162 is uniformly distributed and gradually decreases in a gradient from top to bottom, and the concentration of doped ions in the source polysilicon sublayer 163 is uniformly distributed and gradually decreases in a gradient from top to bottom, so that the concentration of doped ions in the entire source polysilicon layer 160 is distributed in a gradient. The balance of the magnitude of the decrease of the drain-source capacitance CDS with the increase of the drain-source voltage VDS is further improved, so that the curve of the high drain-source capacitance CDS changing with the drain-source voltage VDS is smoother.

[0079] Continue to refer Figure 3Optionally, the gate polysilicon layer 150 is located on a side of the source polysilicon layer 160 away from the substrate 100; the oxide layer between the gate polysilicon layer 150 and the trench is the first oxide layer 141; the oxide layer between the gate polysilicon layer 150 and the source polysilicon layer 160 is the intermediate oxide layer 142; the oxide layer between the source polysilicon layer 160 and the trench is the second oxide layer 143; the intermediate oxide layer 142 and the first oxide layer 141 are integrally formed. The second oxide layer 143 is formed in one process step, and the intermediate oxide layer 142 and the first oxide layer 141 are formed in another process step.

[0080] On the basis of the above embodiments, the technical solution of the embodiment of the present invention is not only applicable to Figure 3 The semiconductor element with the structure shown is also applicable to semiconductor elements with other structures, which are exemplified below but are not intended to limit the present invention.

[0081] As another embodiment of the present invention, optionally, Figure 6 FIG. 1 is a schematic cross-sectional view of another semiconductor element provided by an embodiment of the present invention. Figure 6 , the gate polysilicon layer 150 surrounds the source polysilicon layer 160; the oxide layer 140 exposes the surface of the gate polysilicon layer 150 away from the substrate 100 and the surface of the source polysilicon layer 160 away from the substrate 100; the surface of the gate polysilicon layer 150 away from the substrate 100 is flush with the surface of the source polysilicon layer 160 away from the substrate 100; the distance between the surface of the gate polysilicon layer 150 close to the substrate 100 and the bottom of the trench is smaller than the distance between the surface of the source polysilicon layer 160 close to the substrate 100 and the bottom of the trench; the oxide layer between the gate polysilicon layer 150 and the trench is a first oxide layer 141; the oxide layer between the gate polysilicon layer 150 and the source polysilicon layer 160 is an intermediate oxide layer 142; the oxide layer between the source polysilicon layer 160 and the trench is a second oxide layer 143; the first oxide layer 141, the intermediate oxide layer 142 and the second oxide layer 143 are integrally formed. The first oxide layer 141 , the middle oxide layer 142 , and the second oxide layer 143 are integrally formed, which means that the first oxide layer 141 , the middle oxide layer 142 , and the second oxide layer 143 are formed in one process step.

[0082] Whether Figure 6 The semiconductor element of the structure shown is or Figure 3 The semiconductor device with the structure shown in the figure optimizes the principle of reverse recovery of the body diode. Figure 3 The optimization principle of the semiconductor element of the structure shown is the same. That is,

[0083] The type of doping ions of the source polysilicon layer 160 is set to be opposite to the type of doping ions of the gate polysilicon layer 150, so that the type of doping ions of the source polysilicon layer 160 is opposite to the type of doping ions of the epitaxial layer 110, and the difference in work function between the source polysilicon layer 160 and the epitaxial layer 110 is increased. On this basis, the source polysilicon layer 160 is set to include at least two source polysilicon sublayers, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench, further reducing the drain-source capacitance CDS at the bottom of the trench, so that the capacitance between the drain and the source has a good reduction effect in the full voltage range of the drain-source voltage VDS, thereby reducing the total charge required by the MOSFET during the reverse recovery of the body diode, thereby reducing the drain-source voltage VDS peak and ensuring the good performance of the MOSFET.

[0084] In one embodiment of the present invention, optionally, the materials of the first oxide layer 141 , the middle oxide layer 142 , and the second oxide layer 143 all include silicon oxide.

[0085] In one embodiment of the present invention, optionally, continue to refer to Figure 6 or Figure 3 The semiconductor element further includes a drain electrode 111 , which is located on a side of the substrate 100 away from the epitaxial layer 110 and is electrically connected to the substrate 100 .

[0086] An embodiment of the present invention further provides a method for preparing a semiconductor element, which can be used to prepare the semiconductor element in any of the above embodiments. Figure 7 1 is a flow chart of a method for preparing a semiconductor element provided by an embodiment of the present invention. Figure 7 , the method for preparing a semiconductor element comprises:

[0087] S10. Provide a substrate.

[0088] S11. Form an epitaxial layer on one side of the substrate, wherein a side of the epitaxial layer away from the substrate includes a trench.

[0089] S12. An oxide layer, a gate polysilicon layer and a source polysilicon layer are formed in the groove, wherein the gate polysilicon layer and the source polysilicon layer are both embedded in the oxide layer, and the gate polysilicon layer and the source polysilicon layer are separated by the oxide layer, and the oxide layer at least exposes the surface of the gate polysilicon layer away from the substrate; wherein the source polysilicon layer includes at least two source polysilicon sublayers, and the at least two source polysilicon sublayers are stacked in a direction perpendicular to the substrate; the type of doping ions in the gate polysilicon layer is opposite to the type of doping ions in each source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the groove is lower than the concentration of doping ions in the source polysilicon sublayer away from the bottom of the groove.

[0090] S13. Form a body region and a source region in one end of the epitaxial layer away from the substrate, wherein the body region and the source region are both located on the left and right sides of the gate polysilicon layer; relative to the source region, the body region is located on the side of the source region close to the substrate.

[0091] S14, forming a drain electrode on a side of the substrate away from the epitaxial layer, and forming a source electrode and a gate electrode on a side of the body region away from the substrate; wherein the source electrode is arranged to be electrically connected to the source region and the source polysilicon layer, respectively.

[0092] Based on the above, the embodiments of the present invention can be formed as follows: Figure 3 Or Figure 6 A semiconductor device is shown schematically.

[0093] In one embodiment of the present invention, optionally, the oxide layer includes a first oxide layer, an intermediate oxide layer and a second oxide layer, and step S12, forming an oxide layer, a gate polysilicon layer and a source polysilicon layer in the trench includes:

[0094] S1201, forming a second oxide layer at the bottom of the trench, the sidewalls of the trench, and the surface of the epitaxial layer away from the substrate.

[0095] Specifically, before forming the second oxide layer 143 on the sidewall of the groove, the bottom of the groove, and the surface of the epitaxial layer 110 away from the substrate 100 by chemical vapor deposition, the sidewall of the groove, the bottom of the groove, and the surface of the epitaxial layer 110 away from the substrate 100 can also be oxidized to grow a layer of oxide layer with good density on the sidewall of the groove, the bottom of the groove, and the surface of the epitaxial layer 110 away from the substrate 100 as the second oxide layer 143 of partial thickness. Then, the second oxide layer 143 of the remaining thickness is formed on its surface by chemical vapor deposition. The second oxide layer 143 is formed by combining the chemical vapor deposition method with the wet oxygen oxidation growth method, which can ensure the density of silicon oxide while preventing the stress of the second oxide layer 143 from being too large. In addition, the formation of the partial second oxide layer 143 by combining the chemical vapor deposition method can also increase the process time for forming the second oxide layer 143.

[0096] S1202. At least two first intrinsic polysilicon layers are formed in sequence in the space enclosed by the second oxide layer, and first type doped ions of different concentrations are injected into different first intrinsic polysilicon layers to form a source polysilicon layer; wherein the concentration of injected ions into the first intrinsic polysilicon layer near the bottom of the trench is lower than the concentration of injected ions into the first intrinsic polysilicon layer far from the bottom of the trench; and the total height of the at least two first intrinsic polysilicon layers in the trench is less than the depth of the trench.

[0097] Specifically, the first intrinsic polysilicon material can be deposited in the groove by chemical vapor deposition, and then the first intrinsic polysilicon material can be dry-etched so that the height of the first intrinsic polysilicon material formed after etching in the groove (i.e., the total height of at least two first intrinsic polysilicon layers) is less than the depth of the groove. Different concentrations of first type doping ions are injected into the first intrinsic polysilicon material after etching according to the distance from the bottom of the groove. The first intrinsic polysilicon material after etching is doped at least according to two different concentrations, and the first intrinsic polysilicon material after etching is divided into two layers, upper and lower. That is, at least two layers of the first intrinsic polysilicon layer are formed. Among them, the concentration of the ions injected into the first intrinsic polysilicon layer close to the bottom of the groove is lower than the concentration of the ions injected into the first intrinsic polysilicon layer far from the bottom of the groove.

[0098] S1203, removing the second oxide layer on the surface of the epitaxial layer away from the substrate and in the trench that is not covered by the source polysilicon layer.

[0099] Specifically, the second oxide layer 143 located on the surface of the epitaxial layer 110 away from the substrate 110 and in the trench that is not covered by the source polysilicon layer 160 may be removed by wet etching.

[0100] S1204 , forming an initial oxide layer on a side of the source polysilicon layer away from the substrate and on a side wall of the trench not covered by the source polysilicon layer.

[0101] Specifically, an initial oxide layer may be formed on a side of the source polysilicon layer 160 away from the substrate 110 and on a sidewall of the trench not covered by the source polysilicon layer 160 by chemical vapor deposition.

[0102] S1205, forming a second intrinsic polysilicon layer in the space surrounded by the initial oxide layer, wherein a surface of the second intrinsic polysilicon layer away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and injecting second type doping ions into the second intrinsic polysilicon layer to form a gate polysilicon layer.

[0103] Specifically, a second intrinsic polysilicon layer can be formed in the space surrounded by the initial oxide layer by chemical vapor deposition. The initial oxide layer between the gate polysilicon layer and the trench is the first oxide layer; the initial oxide layer between the gate polysilicon layer and the source polysilicon layer is the intermediate oxide layer; when the first type of doping ions are P-type doping ions, the second type of doping ions are N-type doping ions; when the first type of doping ions are N-type doping ions, the second type of doping ions are P-type doping ions.

[0104] Based on the above, the embodiments of the present invention can be formed as follows: Figure 3 A semiconductor device is shown schematically.

[0105] In another embodiment of the present invention, optionally, step S12, forming an oxide layer, a gate polysilicon layer and a source polysilicon layer in the trench includes:

[0106] S1211. Form an oxide layer in the trench.

[0107] Specifically, an oxide layer may be formed in the trench by a chemical vapor deposition method.

[0108] S1212, etching the oxide layer to form a source trench on a side of the oxide layer away from the substrate.

[0109] Specifically, a source trench may be formed on a side of the oxide layer away from the substrate by wet etching.

[0110] S1213. Form at least two first intrinsic polysilicon layers in the source trench, and inject first type doped ions of different concentrations into different first intrinsic polysilicon layers to form a source polysilicon layer; wherein the concentration of the injected ions in the first intrinsic polysilicon layer near the bottom of the trench is lower than the concentration of the injected ions in the first intrinsic polysilicon layer far from the bottom of the trench; among the at least two first intrinsic polysilicon layers, the surface of the first intrinsic polysilicon layer farthest from the substrate away from the substrate is flush with the surface of the epitaxial layer away from the substrate.

[0111] Specifically, a first intrinsic polysilicon layer may be formed in the source trench by chemical vapor deposition.

[0112] S1214, etching the oxide layer to form a gate trench on a side of the oxide layer away from the substrate, the gate trench surrounds the source polysilicon layer, and the gate trench and the source polysilicon are separated by the oxide layer.

[0113] Specifically, the oxide layer may be etched by wet etching to form a gate trench on a side of the oxide layer away from the substrate.

[0114] S1215, forming a second intrinsic polysilicon layer in the gate trench, wherein a surface of the second intrinsic polysilicon layer away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and injecting second type doping ions into the second intrinsic polysilicon layer to form a gate polysilicon layer.

[0115] Specifically, a second intrinsic polysilicon layer may be formed in the gate trench by chemical vapor deposition, wherein when the first type of doping ions are P-type doping ions, the second type of doping ions are N-type doping ions; and when the first type of doping ions are N-type doping ions, the second type of doping ions are P-type doping ions.

[0116] Based on the above, the embodiments of the present invention can be formed as follows: Figure 6 A semiconductor device is shown schematically.

[0117] The semiconductor element preparation method provided by the embodiment of the present invention and the semiconductor element provided by the embodiment of the present invention both belong to the same inventive concept, can achieve the same technical effect, and the repeated contents will not be repeated here.

[0118] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor element, characterized in that: include: substrate; An epitaxial layer is located on one side of the substrate, and a side of the epitaxial layer away from the substrate includes a trench; an oxide layer located in the trench; The gate polysilicon layer and the source polysilicon layer are both embedded in the oxide layer; the gate polysilicon layer and the source polysilicon layer are separated by the oxide layer, and the oxide layer at least exposes the surface of the gate polysilicon layer away from the substrate; The body region and the source region are both formed in one end of the epitaxial layer away from the substrate; the body region and the source region are both located on the left and right sides of the gate polysilicon layer; relative to the source region, the body region is located on the side of the source region close to the substrate; A source electrode, located at a side of the body region away from the substrate and electrically connected to the source region and the source polysilicon layer; Among them, the source polysilicon layer includes at least two source polysilicon sublayers, and the at least two source polysilicon sublayers are stacked in a direction perpendicular to the substrate; the type of doping ions in the gate polysilicon layer is opposite to the type of doping ions in each source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench.

2. The semiconductor device according to claim 1, characterized in that The concentration of doping ions in the same source polysilicon sublayer is the same.

3. The semiconductor device according to claim 1, wherein: The concentration of doped ions in the same source polysilicon sublayer is distributed in a gradient, and the concentration of doped ions is positively correlated with the height of the doped position relative to the bottom of the trench.

4. The semiconductor device according to claim 1, wherein: The doping ions of the substrate, the epitaxial layer, the source region and the gate polysilicon layer are all of P type; the doping ions of the body region and the source polysilicon layer are all of N type; Alternatively, the doping ions of the substrate, the epitaxial layer, the source region and the gate polysilicon layer are all of N type; and the doping ions of the body region and the source polysilicon layer are of P type.

5. The semiconductor device according to claim 1, wherein: The gate polysilicon layer is located on a side of the source polysilicon layer away from the substrate; The oxide layer between the gate polysilicon layer and the trench is a first oxide layer; The oxide layer between the gate polysilicon layer and the source polysilicon layer is an intermediate oxide layer; The oxide layer between the source polysilicon layer and the trench is a second oxide layer; Wherein, the intermediate oxide layer and the first oxide layer are integrally formed.

6. The semiconductor device according to claim 1, characterized in that The gate polysilicon layer surrounds the source polysilicon layer; The oxide layer exposes a surface of the gate polysilicon layer away from the substrate and a surface of the source polysilicon layer away from the substrate; the surface of the gate polysilicon layer away from the substrate is flush with the surface of the source polysilicon layer away from the substrate; the distance between the surface of the gate polysilicon layer close to the substrate and the bottom of the trench is smaller than the distance between the surface of the source polysilicon layer close to the substrate and the bottom of the trench; The oxide layer between the gate polysilicon layer and the trench is a first oxide layer; The oxide layer between the gate polysilicon layer and the source polysilicon layer is an intermediate oxide layer; The oxide layer between the source polysilicon layer and the trench is a second oxide layer; Wherein, the first oxide layer, the middle oxide layer and the second oxide layer are integrally formed.

7. The semiconductor device according to claim 1, wherein: Also includes: A drain electrode is located at a side of the substrate away from the epitaxial layer and is electrically connected to the substrate.

8. A method for preparing a semiconductor element, characterized in that: providing a substrate; forming an epitaxial layer on one side of the substrate, wherein a side of the epitaxial layer away from the substrate comprises a trench; An oxide layer, a gate polysilicon layer and a source polysilicon layer are formed in the trench, wherein the gate polysilicon layer and the source polysilicon layer are both embedded in the oxide layer, the gate polysilicon layer and the source polysilicon layer are separated by the oxide layer, and the oxide layer at least exposes a surface of the gate polysilicon layer away from the substrate; A body region and a source region are formed in one end of the epitaxial layer away from the substrate, wherein the body region and the source region are both located on the left and right sides of the gate polysilicon layer; relative to the source region, the body region is located on a side of the source region close to the substrate; forming a source electrode on a side of the body region away from the substrate; Among them, the source polysilicon layer includes at least two source polysilicon sublayers, and the at least two source polysilicon sublayers are stacked in a direction perpendicular to the substrate; the type of doping ions in the gate polysilicon layer is opposite to the type of doping ions in each source polysilicon sublayer, and the concentration of doping ions in the source polysilicon sublayer close to the bottom of the trench is lower than the concentration of doping ions in the source polysilicon sublayer far from the bottom of the trench.

9. The method for preparing a semiconductor element according to claim 8, characterized in that: The oxide layer includes a first oxide layer, an intermediate oxide layer and a second oxide layer; and forming an oxide layer, a gate polysilicon layer and a source polysilicon layer in the trench includes: forming a second oxide layer at the bottom of the trench, the sidewalls of the trench, and the surface of the epitaxial layer away from the substrate; At least two first intrinsic polysilicon layers are sequentially formed in the space surrounded by the second oxide layer, and first type doping ions of different concentrations are implanted into different first intrinsic polysilicon layers to form a source polysilicon layer; wherein the concentration of the implanted ions in the first intrinsic polysilicon layer close to the bottom of the trench is lower than the concentration of the implanted ions in the first intrinsic polysilicon layer far from the bottom of the trench; and the total height of the at least two first intrinsic polysilicon layers in the trench is less than the depth of the trench; removing the second oxide layer which is not covered by the source polysilicon layer and is located on the surface of the epitaxial layer away from the substrate and in the trench; forming an initial oxide layer on a side of the source polysilicon layer away from the substrate and on a sidewall of the trench not covered by the source polysilicon layer; forming a second intrinsic polysilicon layer in the space surrounded by the initial oxide layer, wherein a surface of the second intrinsic polysilicon layer away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and implanting second type doping ions into the second intrinsic polysilicon layer to form a gate polysilicon layer; Wherein, the initial oxide layer between the gate polysilicon layer and the trench is a first oxide layer; The initial oxide layer between the gate polysilicon layer and the source polysilicon layer is an intermediate oxide layer; When the first type doping ions are P-type doping ions, the second type doping ions are N-type doping ions; when the first type doping ions are N-type doping ions, the second type doping ions are P-type doping ions.

10. The method for preparing a semiconductor element according to claim 8, characterized in that: Forming an oxide layer, a gate polysilicon layer and a source polysilicon layer in the trench comprises: forming an oxide layer in the trench; Etching the oxide layer to form a source trench on a side of the oxide layer away from the substrate; At least two first intrinsic polysilicon layers are formed in the source trench, and first type doping ions of different concentrations are implanted into different first intrinsic polysilicon layers to form source polysilicon layers; wherein the concentration of the implanted ions in the first intrinsic polysilicon layer close to the bottom of the trench is lower than the concentration of the implanted ions in the first intrinsic polysilicon layer far from the bottom of the trench; and among the at least two first intrinsic polysilicon layers, the surface of the first intrinsic polysilicon layer farthest from the substrate away from the substrate is flush with the surface of the epitaxial layer away from the substrate; Etching the oxide layer to form a gate trench on a side of the oxide layer away from the substrate, wherein the gate trench surrounds the source polysilicon layer, and the gate trench is separated from the source polysilicon layer by the oxide layer; forming a second intrinsic polysilicon layer in the gate trench, wherein a surface of the second intrinsic polysilicon layer away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and implanting second type doping ions into the second intrinsic polysilicon layer to form a gate polysilicon layer; When the first type of doping ions are P-type doping ions, the second type of doping ions are N-type doping ions; when the first type of doping ions are N-type doping ions, the second type of doping ions are P-type doping ions.

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