A memristive feedback self-adjusting hyperchaotic waveform generator

Abstract

The present invention discloses a memristive feedback self-adjusting hyperchaotic waveform generator, which relates to the technical fields of electronics, communication and information engineering. Through a three-way integral summation operation circuit, using two multiplier circuits and two inverting operation units, a hyperchaotic signal with adjustable amplitude is output; by the resistance of a certain branch, the value of the amplitude change of the hyperchaotic signal output by the circuit is adjusted to achieve amplitude control. The amplitude control has two control entrances different from other circuits, which increases the flexibility of the hardware circuit and reduces the difficulty of circuit implementation and debugging, providing convenience for the application of hyperchaotic signals in electronics and information engineering.

Description

Technical Field

[0001] The present invention relates to the technical fields of electronics, communication, and information engineering, and particularly to a memristor feedback type self-adjusting hyperchaotic waveform generator. Background Art

[0002] As a broadband random signal, hyperchaotic signals have extensive applications in fields such as fluid stirring, search and prediction, instrumentation, communication, and radar. The amplification or attenuation of the signal amplitude and the control of the bias applied in engineering are not only the requirements of signal conditioning but also an important aspect of characterizing the circuit characteristics. Changing the amplitude and bias of hyperchaotic signals is a basic task of signal preprocessing or conditioning circuits. Constructing a self-adjusting circuit based on system parameters can reduce redundant circuit components or additional systems, achieving the purpose of streamlining the circuit, and has important engineering value.

[0003] Regarding the generation of self-adjusting chaotic signals, relevant patents have presented corresponding designed circuits. For example, Patent [Authorization Number CN107317668B] proposes a self-adjusting chaotic signal source, which realizes the amplitude adjustment of the chaotic signal output by the system through the adjustment of the variable resistor in the second branch, and realizes the polarity control of the chaotic signal through the adjustment of the DC power supply. However, this system cannot achieve the conditioning of hyperchaos. Another patent [Authorization Number CN105846991A] proposes a simple three-dimensional adjustable amplitude chaotic signal generator. This invention uses two groups of analog gating circuits and outputs a type of LORENZ chaotic attractor with adjustable magnitude through a three-way integral summation operation circuit. Similarly, this system can only condition chaotic signals and cannot output hyperchaotic signals. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a memristor feedback type self-adjusting hyperchaotic waveform generator. The memristor hyperchaotic system with amplitude control and bias control proposed by the present invention combines several multipliers and operational amplifiers with resistors and capacitors. Through the adjustment of variable resistors, the amplitude regulation of the hyperchaotic signal output by the system is realized, and the bias of the chaotic signal is adjusted through the DC power supply, realizing the self-adjustment of the hyperchaotic signal, providing a new choice for chaotic engineering applications.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A memristor feedback type self-adjusting hyperchaotic waveform generator according to the present invention includes a memristor, a product operation unit, a first to tenth resistor, a first to third capacitor, a first integral operation unit, an inverting proportional operation unit, a second integral operation unit, a third integral operation unit, and a first DC voltage source; wherein,

[0007] The output terminal of the memristor is connected to the input terminal of the product operation unit. The output terminal of the product operation unit is connected to one end of the third resistor. The other end of the third resistor is respectively connected to one end of the first resistor, one end of the second resistor, one end of the fourth resistor, one end of the eighth resistor, one end of the first capacitor, and the inverting input terminal of the first integral operation unit. The other end of the eighth resistor is connected to the first DC voltage source. The other end of the first capacitor is respectively connected to the output terminal of the first integral operation unit and one end of the ninth resistor. The other end of the ninth resistor is respectively connected to one end of the tenth resistor and the inverting input terminal of the inverting proportional operation unit. The other end of the tenth resistor is respectively connected to the output terminal of the inverting proportional operation unit, one end of the seventh resistor, and one end of the fifth resistor. The other end of the seventh resistor is respectively connected to one end of the third capacitor and the inverting input terminal of the third integral operation unit. The other end of the third capacitor is connected to the output terminal of the third integral operation unit. The other end of the fifth resistor is respectively connected to one end of the sixth resistor, one end of the second capacitor, and the inverting input terminal of the second integral operation unit. The other end of the second capacitor is connected to the output terminal of the second integral operation unit.

[0008] As a further optimized scheme of the memristor feedback type self-adjusting hyperchaotic waveform generator of the present invention, the memristor includes a first product operation unit, the tenth to seventeenth resistors, a fourth capacitor, a second DC voltage source, a first operational amplifier, a second operational amplifier, a third operational amplifier, and an absolute value circuit; wherein,

[0009] One end of the thirteenth resistor is respectively connected to one end of the fourteenth resistor, one end of the fourth capacitor, and the inverting input terminal of the first operational amplifier. The other end of the fourteenth resistor is connected to the output terminal of the first product operation unit. The output terminal of the first operational amplifier is connected to one end of the seventeenth resistor. The other end of the seventeenth resistor is connected to one end of the absolute value circuit. The other end of the absolute value circuit is connected to one end of the sixteenth resistor. The other end of the sixteenth resistor is respectively connected to one end of the fifteenth resistor and the inverting input terminal of the second operational amplifier. The output terminal of the second operational amplifier is connected to the other end of the fifteenth resistor and one end of the eleventh resistor. The other end of the eleventh resistor is respectively connected to one end of the tenth resistor, one end of the twelfth resistor, and the inverting input terminal of the third operational amplifier. The other end of the twelfth resistor is connected to the second DC voltage source. The other end of the tenth resistor is connected to the output terminal of the third operational amplifier.

[0010] As a further optimized scheme of the memristor feedback type self-adjusting hyperchaotic waveform generator of the present invention, the fourteenth resistor is a variable resistor.

[0011] When the present invention adopts the above technical solutions compared with the prior art, it has the following technical effects:

[0012] The present invention outputs an ultra-chaotic signal with adjustable amplitude through a three-way integral summation operation circuit, using two multiplier circuits and two inverting operation units; the value of the amplitude change of the ultra-chaotic signal output by the circuit is adjusted through the resistance of a certain branch to achieve amplitude control. The amplitude control has two control entrances different from other circuits, increasing the flexibility of the hardware circuit and reducing the difficulty of circuit implementation and debugging, which provides convenience for the application of ultra-chaotic signals in electronics and information engineering. Description of the Drawings

[0013] Figure 1 is the signal waveform diagram of x(t) of the memristor feedback type self-adjusting ultra-chaotic waveform generator;

[0014] Figure 2 is the signal waveform diagram of y(t) of the memristor feedback type self-adjusting ultra-chaotic waveform generator;

[0015] Figure 3a is the z-x phase trajectory of the memristor feedback type self-adjusting ultra-chaotic waveform generator under amplitude modulation, Figure 3b is the signal waveform diagram of z(t) of the memristor feedback type self-adjusting ultra-chaotic waveform generator under amplitude modulation;

[0016] Figure 4 is the phase trajectory and waveform change of the memristor feedback type self-adjusting ultra-chaotic waveform generator under bias; among them, (a) is the change of the phase trajectory position when n = -8, 0, 8; (b) is the change of the phase trajectory waveform when n = -8, 0, 8;

[0017] Figure 5a is the circuit diagram of the memristor feedback type self-adjusting ultra-chaotic waveform generator, Figure 5b is the circuit diagram of the memristor;

[0018] Figure 6 is the experimental simulation oscilloscope phase trajectory diagram of the memristor feedback type self-adjusting ultra-chaotic waveform generator; among them, (a) is the waveform diagram of the x(t) signal when the control resistance R 9 is 10KΩ, and (b) is the waveform diagram of the x(t) signal when the control resistance R 9 is 1KΩ;

[0019] Figure 7 is the circuit simulation diagram of the memristor feedback type self-adjusting ultra-chaotic waveform generator; among them, (a) is the waveform diagram of the y(t) signal when the control resistance R 9 is 10KΩ, and (b) is the waveform diagram of the y(t) signal when the control resistance R 9 is 1KΩ.

[0020] Figure 8It is the phase trajectory and waveform change circuit simulation diagram of the amplitude modulation characteristic of the memristor feedback type self-adjusting hyperchaotic waveform generator; among them, (a) is when the control resistance R 9 is 10KΩ, the z-x phase trajectory, (b) is when the control resistance R 9 is 1KΩ, the z-x phase trajectory, (c) is when the control resistance R 9 is 10KΩ, the waveform diagram of the z(t) signal, (d) is when the control resistance R 9 is 1KΩ, the waveform diagram of the z(t) signal.

[0021] Figure 9 It is the phase trajectory and waveform change circuit simulation diagram of the bias characteristic of the memristor feedback type self-adjusting hyperchaotic waveform generator: among them, (a), (b), and (c) are the changes in the phase trajectory positions when V 2 =1.5, 0, -1.5 respectively; (d), (e), and (f) are the changes in the phase trajectory waveforms when V 2 =1.5, 0, -1.5 respectively. Specific implementation mode

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0023] A memristor feedback type self-adjusting hyperchaotic waveform generator includes a memristor W(u), a product operation unit M 3 , the first to tenth resistors R 1 -R 7 , R 0 , R 13 , R 14 , the first to third capacitors C 1 -C 3 , the first integral operation unit U 1 , the inverting proportional operation unit U 2 , the second integral operation unit U 3 , the third integral operation unit U 5 , the first DC voltage source V 2 ; among them,

[0024] The output terminal of the memristor is connected to the input terminal of the product operation unit. The output terminal of the product operation unit is connected to one end of the third resistor. The other end of the third resistor is respectively connected to one end of the first resistor, one end of the second resistor, one end of the fourth resistor, one end of the eighth resistor, one end of the first capacitor, and the inverting input terminal of the first integral operation unit. The other end of the eighth resistor is connected to the first DC voltage source. The other end of the first capacitor is respectively connected to the output terminal of the first integral operation unit and one end of the ninth resistor. The other end of the ninth resistor is respectively connected to one end of the tenth resistor and the inverting input terminal of the inverting proportional operation unit. The other end of the tenth resistor is respectively connected to the output terminal of the inverting proportional operation unit, one end of the seventh resistor, and one end of the fifth resistor. The other end of the seventh resistor is respectively connected to one end of the third capacitor and the inverting input terminal of the third integral operation unit. The other end of the third capacitor is connected to the output terminal of the third integral operation unit. The other end of the fifth resistor is respectively connected to one end of the sixth resistor, one end of the second capacitor, and the inverting input terminal of the second integral operation unit. The other end of the second capacitor is connected to the output terminal of the second integral operation unit.

[0025] The memristor includes a first product operation unit, the tenth to seventeenth resistors R 10 , R 11 , R 12 , R 8 , R 9 , R 15 , R 16 , R 17 , the fourth capacitor C 4 , the second DC voltage source V 1 , the first operational amplifier U 6 , the second operational amplifier U 4 , the third operational amplifier U 9 and the absolute value circuit; wherein,

[0026] One end of the thirteenth resistor is respectively connected to one end of the fourteenth resistor, one end of the fourth capacitor, and the inverting input terminal of the first operational amplifier. The other end of the fourteenth resistor is connected to the output terminal of the first product operation unit. The output terminal of the first operational amplifier is connected to one end of the seventeenth resistor. The other end of the seventeenth resistor is connected to one end of the absolute value circuit. The other end of the absolute value circuit is connected to one end of the sixteenth resistor. The other end of the sixteenth resistor is respectively connected to one end of the fifteenth resistor and the inverting input terminal of the second operational amplifier. The output terminal of the second operational amplifier is connected to the other end of the fifteenth resistor and one end of the eleventh resistor. The other end of the eleventh resistor is respectively connected to one end of the tenth resistor, one end of the twelfth resistor, and the inverting input terminal of the third operational amplifier. The other end of the twelfth resistor is connected to the second DC voltage source. The other end of the tenth resistor is connected to the output terminal of the third operational amplifier.

[0027] The fourteenth resistor is a variable resistor.

[0028] The oscillation behavior of this system can be adjusted by the connection resistors of the corresponding branches. The memristive hyperchaotic circuit designed in the present invention has a more complex structure and dynamic behavior, can better meet the requirements of secure communication and information encryption, and helps to develop pseudo-random number generators and secure communication systems based on chaotic engineering applications.

[0029] As a new type of non-linear element, due to the introduction of non-linear feedback, the memristor has become a new type of circuit element commonly used to construct chaotic systems. Many circuits introduce memristors to obtain hyperchaos and study the multistable behavior caused by memristors. In recent years, with the development of the concept and devices of memristors, some classical systems and other dynamic systems have been successfully transformed into memristive systems. The generation of memristive hyperchaotic signals has important theoretical, physical significance and engineering value. The present invention proposes a hyperchaotic memristive circuit. By introducing memristive feedback, with the help of two multipliers and nine operational amplifiers, combined with several resistors and four capacitors, hyperchaos is output. The amplitude of the hyperchaotic signal is controlled by the resistor of a certain branch, and the bias control of the chaotic signal is achieved through the adjustment of the DC power supply.

[0030] The memristive feedback self-adjusting hyperchaotic waveform generator is based on the integrating circuits of four branches. Through two multipliers and nine operational amplifiers, combined with several resistors and four capacitors, four-channel hyperchaotic signals are output. The amplitude of the hyperchaotic signal is adjusted by the resistor on the memristive non-linear feedback branch.

[0031] In the memristive feedback self-adjusting hyperchaotic waveform generator, the first branch includes five input terminals and the DC voltage source V 2 , one end of the DC voltage source V 2 is grounded, and the other end is connected to R 0 and is connected to the input terminal of U 1 . Among them, the input signals -x, y, and z are respectively connected to the input terminals of the integrating operation unit U 1 , through the resistor R 2 , through the resistor R 4 ; the input signal x is connected to the memristor W(u), and the item xW(u) is output. The input signals -x and xW(u) are connected to R 1 through the product operation unit M 3 and then connected to the input terminal of the integrating operation unit U 3 . The output signal x of the integrating operation unit U 1 is connected to the inverting proportional operation unit U 1 , and the output signal -x is output from the output terminal of the inverting proportional operation unit U 2 . The second branch includes two input terminals, and its two input signals -x and y are respectively connected to the resistor R 2 through the resistor R 5 ...6 Connected to the integration operation unit U 3 , the integration operation unit U 3 The output terminal outputs a signal y, and the input signal -x of the second branch is the output signal of the first branch. The third branch has only one input terminal, that is, the output signal -x of the first branch is connected to the integration operation circuit U5 through the resistor R7, and the output terminal of the integration operation circuit U5 outputs a signal z.

[0032] In the first branch, the input signal x is connected to the memristor W(u), and W(u) includes a resistor R 8 , resistor R 9 , resistor R 10 , resistor R 11 , resistor R 12 , resistor R 15 , resistor R 16 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , resistor R 21 , capacitor C 4 , operational amplifier U 2 , operational amplifier U 6 , operational amplifier U 4 , operational amplifier U 8 , operational amplifier U 9 , product operation unit, diode D 1 , diode D 2 , DC voltage source V 1 .

[0033] The first branch includes an integration operation unit U 1 , an inverting proportional operation unit U 2 , a DC voltage source V 2 , resistor R 0 , resistor R 1 , resistor R 2 , resistor R 3 , resistor R 4 , resistor R 13 , resistor R 14 and capacitor C 1 , product unit M 3 , where the output terminal of the second branch is connected to the inverting input terminal of the integration operation unit U 2 through the resistor R 1 , the non-inverting input terminal of the integration operation unit U 1 is grounded, and the inverting input terminal of the integration operation unit U 1 is connected to one end of the capacitor C 1 , and the other end of the capacitor C 1 is connected to the integration operation unit U1 The output terminal of 13 is connected to the inverting input terminal of the inverting proportional operation unit U 2 through a resistor R. The non-inverting input terminal of the inverting proportional operation unit U 2 is grounded. The inverting input terminal of the inverting proportional operation unit U 2 is connected to one end of the resistor R 13 . And one end of the resistor R 5 in the second branch is connected to the output terminal of the inverting proportional operation unit U 2 , that is, it is connected to the output terminal of the first branch.

[0034] The second branch includes an integration operation unit U 3 , a resistor R 5 , a resistor R 6 , and a capacitor C 2 . Among them, the non-inverting input terminal of the integration operation unit U 2 is grounded. The inverting input terminal of the integration operation unit U 2 is connected to one end of the capacitor C 2 . The other end of the capacitor C 2 is connected to the input signal y through a resistor R 6 , and at the same time is connected to the input signal -x through a resistor R 5 . The input signal -x is the output signal of the first branch.

[0035] The third branch includes an integration operation unit U 5 , a resistor R 7 , and a capacitor C 3 . Among them, the resistor R 7 is connected to the inverting input terminal of the integration operation unit U 3 . The inverting input terminal of the integration operation unit U 3 is connected to one end of the capacitor C 3 . The other end of the capacitor C 3 and the output terminal of the integration operation unit U 3 are connected to the output terminal of the third branch.

[0036] For the hyperchaotic signal output by the memristor feedback type self-adjusting hyperchaotic waveform generator, the change in its amplitude can be achieved by adjusting the value of the resistor R 3 in the first branch.

[0037] Figure 3a is the z-x phase trajectory in the case of amplitude modulation of the memristor feedback type self-adjusting hyperchaotic waveform generator, Figure 3b is the signal waveform diagram of z(t) in the case of amplitude modulation of the memristor feedback type self-adjusting hyperchaotic waveform generator; Figure 4 is the phase trajectory and waveform change in the case of bias of the memristor feedback type self-adjusting hyperchaotic waveform generator; among them, Figure 4Among them, (a) shows the change in the phase trajectory position when n = -8, 0, 8; Figure 4 Among them, (b) shows the change in the phase trajectory waveform when n = -8, 0, 8; Figure 5a is the circuit diagram of the memristor feedback type self - regulating hyper - chaotic waveform generator, Figure 5b is the circuit diagram of the memristor; where, C 1 = C 2 = C 3 = 10 nF, R 1 = R 2 = 22.22 kΩ, R 3 = 10 kΩ, R 4 = 100 kΩ, R 5 = R 6 = 18.18 kΩ, R 7 = 500 kΩ, R 13 = R 14 = 10 kΩ. The equivalent circuit parameters of the corresponding memristive element are: C 4 = 10 nF, R 8 = 250 kΩ, R 9 = R 10 = R 12 = R 15 = R 16 = 10 kΩ, R 11 = 2.5 kΩ.

[0038] Figure 6 is the phase trajectory diagram of the oscilloscope in the experimental simulation of the memristor feedback type self - regulating hyper - chaotic waveform generator; where, Figure 6 Among them, (a) is the waveform diagram of the x(t) signal when the regulating resistor R 9 is 10 KΩ, Figure 6 Among them, (b) is the waveform diagram of the x(t) signal when the regulating resistor R 9 is 1 KΩ;

[0039] Figure 7 is the circuit simulation diagram of the memristor feedback type self - regulating hyper - chaotic waveform generator; where, Figure 7 Among them, (a) is the waveform diagram of the y(t) signal when the regulating resistor R 9 is 10 KΩ, Figure 7 Among them, (b) is the waveform diagram of the y(t) signal when the regulating resistor R 9 is 1 KΩ.

[0040] Figure 8 is the circuit simulation diagram of the phase trajectory and waveform change of the amplitude - modulation characteristic of the memristor feedback type self - regulating hyper - chaotic waveform generator; where, Figure 8 Among them, (a) is the z - x phase trajectory when the regulating resistor R 9 is 10 KΩ, Figure 8In (b), when the regulating resistor R 9 is 1 KΩ, the z-x phase trajectory is shown. Figure 8 In (c), when the regulating resistor R 9 is 10 KΩ, the waveform of the z(t) signal is shown. Figure 8 In (d), when the regulating resistor R 9 is 1 KΩ, the waveform of the z(t) signal is shown.

[0041] Figure 9 are the phase trajectories and waveform variation circuit simulation diagrams of the bias characteristics of the memristor feedback self-adjusting hyperchaotic waveform generator: Among them, Figure 9 in (a), (b), and (c), the changes in the phase trajectory positions are respectively when V 2 = 1.5, 0, -1.5; Figure 9 in (d), (e), and (f), the changes in the phase trajectory waveforms are respectively when V 2 = 1.5, 0, -1.5.

[0042] (1) The dynamic equation and circuit structure of the memristor feedback self-adjusting hyperchaotic waveform generator

[0043] The hyperchaotic memristor circuit of the present invention can be described by the following dynamic system equation.

[0044]

[0045] Its memristor equation is:

[0046]

[0047] Formally, this equation contains eight first-order linear feedbacks, one second-order nonlinear feedback, one internal nonlinear feedback, and a constant term for regulating the bias. When a = 11, b = 154, c = 14, d = 1.25, e = 1, m = 1, IC = (1, 0, 0, 1), the hyperchaotic attractor output by the system, at this time the Lyapunov exponents corresponding to the system are (0.5997, 0.0529, 0, -5.3768), and D KY = 3.1214.

[0048] This system can be realized by a closed feedback system composed of three branches. When implemented using a three-way integral summation operation loop, the circuit diagram is as shown in Figure 2 . Figure 1 is the signal waveform diagram of x(t) of the memristor feedback self-adjusting hyperchaotic waveform generator: where a = 11, b = 154, c = 14, d = 1.25, e = 1, IC = (1 0 0 1); Figure 2It is the signal waveform diagram of the memristive feedback self-adjusting hyperchaotic waveform generator y(t): where a = 11, b = 154, c = 14, d = 1.25, e = 1, and IC = (1 00 1). Transforming the above mathematical equation into a more specific circuit equation,

[0049]

[0050]

[0051] The circuit equation is consistent with the system dynamics equation. Here, the coefficients of each feedback term in the system are realized through resistor settings, and the coefficient m of the linear term can control the amplitude of the signal, which can be achieved by adjusting the resistor R 3 .

[0052] The first branch includes an integration operation unit U 1 , an inverting proportional operation unit U 2 , a DC voltage source V 2 , resistors R 0 , R 1 , R 2 , R 3 , R 4 , R 13 , R 14 , and a capacitor C 1 , a product unit M 3 . The output terminal of the second branch is connected to the inverting input terminal of the summing and integrating operation unit U 2 through a resistor R 1 . The non-inverting input terminal of the integration operation unit U 1 is grounded. The inverting input terminal of the summing and integrating operation unit U 1 is connected to one end of the capacitor C 1 . The other end of the capacitor C 1 and the output terminal of the summing and integrating operation unit U 1 are connected to the inverting input terminal of the inverting proportional operation unit U 13 through a resistor R 2 . The non-inverting input terminal of the inverting proportional operation unit U 2 is grounded. The inverting input terminal of the inverting proportional operation unit U 2 is connected to one end of the resistor R 13 . And one end of the resistor R 5 in the second branch and the output terminal of the inverting proportional operation unit U 2 , that is, connected to the output terminal of the first branch. The first branch includes five input terminals, where the input signals -x, y, and z pass through resistors R 1 , R 2 , R 4Input terminal of the connection integration operation unit U 1 ; The input signal x is connected to the memristor W(u), and the xW(u) term is output. The input signals -x and xW(u) pass through the product operation unit M 3 connected to R 3 and then connected to the input terminal of the integration operation unit U 1 . The output signal x of the integration operation unit U 1 is connected to the inverting proportional operation unit U 2 , and the output signal -x is output from the output terminal of the inverting proportional operation unit U 2 .

[0053] The second branch includes the integration operation unit U 3 , resistor R 5 , resistor R 6 , and capacitor C 2 . Among them, the non-inverting input terminal of the integration operation unit U 2 is grounded, and the inverting input terminal of the integration operation unit U 2 is connected to one end of the capacitor C 2 . The other end of the capacitor C 2 is connected to the input signal y through the resistor R 6 , and at the same time is connected to the input signal -x through the resistor R 5 . The input signal -x is the output signal of the first branch. The second branch includes two input terminals, and its two input signals -x and y are respectively connected to the integration operation unit U 5 through the resistor R 6 and the resistor R 3 . The output signal y is output from the output terminal of the integration operation unit U 3 , and the input signal -x of the second branch is the output signal of the first branch.

[0054] The third branch includes the integration operation unit U 5 , resistor R 7 , and capacitor C 3 . Among them, the resistor R 7 is connected to the inverting input terminal of the summing integration operation unit U 3 . The inverting input terminal of the integration operation unit U 3 is connected to one end of the capacitor C 3 . The other end of the capacitor C 3 and the output terminal of the integration operation unit U 3 are connected to the output terminal of the third branch. The third branch has only one input terminal, that is, the output signal -x of the first branch is used as the input signal of the third branch and is connected to the integration operation unit U 7 through the resistor R 5 . The output signal z is output from the output terminal of the integration operation unit U 5 .

[0055] (2) Amplitude control method

[0056] For the memristor feedback type self-adjusting hyperchaotic waveform generator described above, its characteristic is that the output hyperchaotic signal has a non-bifurcation knob for amplitude control, which can be achieved through the adjustment of the variable resistor R 9 When the coefficient m is introduced, the amplitude of the output three-dimensional chaotic signal also changes accordingly. This can be achieved by x→hx, y→hy, z→hz, u→u, t→t (h>0), and it only leaves an additional coefficient in the three-dimensional space:

[0057]

[0058] It can be seen that the change of the parameter m can control the amplitudes of the signals x, y and z, and can keep the amplitude of u unchanged, and has no effect on the frequencies of all signals

[0059] (3) Bias control method

[0060] For the memristor feedback type self-adjusting hyperchaotic waveform generator described above, its characteristic is that the output hyperchaotic signal has a non-bifurcation knob for bias control, which can be achieved through the adjustment of V 2 As can be seen from equation (1), x→x, y→y, z→z - n, u→u, t→t, and the system equation becomes:

[0061]

[0062] It can be seen that the polarity change of the chaotic signal in the z-axis direction can be achieved by introducing a DC feedback term n in the system equation to realize its bias control, and is controlled by V in the circuit equation 2 control.

[0063] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A memristor feedback type self-adjusting hyperchaotic waveform generator, characterized in that, it includes a memristor, a product operation unit, the first to tenth resistors, the first to third capacitors, a first integral operation unit, an inverting proportional operation unit, a second integral operation unit, a third integral operation unit, and a first DC voltage source; wherein, the output end of the memristor is connected to the input end of the product operation unit, the output end of the product operation unit is connected to one end of the third resistor, the other end of the third resistor is respectively connected to one end of the first resistor, one end of the second resistor, one end of the fourth resistor, one end of the eighth resistor, one end of the first capacitor, and the inverting input end of the first integral operation unit, the other end of the eighth resistor is connected to the first DC voltage source, the other end of the first capacitor is respectively connected to the output end of the first integral operation unit and one end of the ninth resistor, the other end of the ninth resistor is respectively connected to one end of the tenth resistor and the inverting input end of the inverting proportional operation unit, the other end of the tenth resistor is respectively connected to the output end of the inverting proportional operation unit, one end of the seventh resistor, and one end of the fifth resistor, the other end of the seventh resistor is respectively connected to one end of the third capacitor and the inverting input end of the third integral operation unit, the other end of the third capacitor is connected to the output end of the third integral operation unit, the other end of the fifth resistor is respectively connected to one end of the sixth resistor, one end of the second capacitor, and the inverting input end of the second integral operation unit, and the other end of the second capacitor is connected to the output end of the second integral operation unit.

2. A memristor feedback type self-adjusting hyperchaotic waveform generator according to claim 1, characterized in that, the memristor includes a first product operation unit, the tenth to seventeenth resistors, a fourth capacitor, a second DC voltage source, a first operational amplifier, a second operational amplifier, a third operational amplifier, and an absolute value circuit; wherein, one end of the thirteenth resistor is respectively connected to one end of the fourteenth resistor, one end of the fourth capacitor, and the inverting input end of the first operational amplifier, the other end of the fourteenth resistor is connected to the output end of the first product operation unit, the output end of the first operational amplifier is connected to one end of the seventeenth resistor, the other end of the seventeenth resistor is connected to one end of the absolute value circuit, the other end of the absolute value circuit is connected to one end of the sixteenth resistor, the other end of the sixteenth resistor is respectively connected to one end of the fifteenth resistor and the inverting input end of the second operational amplifier, the output end of the second operational amplifier is respectively connected to the other end of the fifteenth resistor and one end of the eleventh resistor, the other end of the eleventh resistor is respectively connected to one end of the tenth resistor, one end of the twelfth resistor, and the inverting input end of the third operational amplifier, the other end of the twelfth resistor is connected to the second DC voltage source, and the other end of the tenth resistor is connected to the output end of the third operational amplifier.

3. A memristor feedback type self-adjusting hyperchaotic waveform generator according to claim 2, characterized in that, the fourteenth resistor is a variable resistor.

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